Claims:We claim:
1. A 3-phase charger (100) comprising
a plurality of Silicon Carbide (SiC) switch pairs (102a and 102b, 102c and 102d, and 102e and 102f), wherein a first phase voltage, a second phase voltage and a third phase voltage are connected to the plurality of SiC switch pairs (102a and 102b, 102c and 102d, and 102e and 102f) through boost inductors (101a, 101b and 101c) respectively;
a plurality of capacitors (103a, 103b) connected in series with the plurality of SiC switch pairs (102a and 102b, 102c and 102d, and 102e and 102f);
a node (104a) formed by the boost inductor (101a) and the SiC switch pair (102a and 102b), wherein the node (104a) is connected to a primary winding (107a) of a first transformer (107) through a resonant capacitor (105a) and a resonant inductor (106a);
a node (104b) formed by the boost inductor (101b) and the SiC switch pair (102c and 102d), wherein the node (104b) is connected to a primary winding (108a) of a second transformer (108) a resonant capacitor (105b) and a resonant inductor (106b);
a node (104c) formed by the boost inductor (101c) and the SiC switch pair (102e and 102f), wherein the node (104c) is connected to a primary winding (109a) of a third transformer (109) through a resonant capacitor (105c) and a resonant inductor (106c);
the first transformer (107), wherein a secondary winding of the first transformer (107) is divided into two portions comprising equal turns (107b and 107c), wherein a center tap of the secondary winding is connected to a ground terminal and other end of each portion is connected to an output filter capacitor (111) through diodes (110a, 110b);
the second transformer (108), wherein a secondary winding of the second transformer (108) is divided into two portions comprising equal turns (108b and 108c), wherein a center tap of the secondary winding is connected to the ground terminal and other end of each portion is connected to an output filter capacitor (111) through diodes (110c, 110d);
the third transformer (109), wherein a secondary winding of the third transformer (109) is divided into two equal turns (109b and 109c), wherein a center tap of the secondary winding is connected to the ground terminal and other end of each portion is connected to an output filter capacitor (111) through diodes (110e, 110f); and
the output filter capacitor (111), wherein at least one load (112) is connected in parallel across the output filter capacitor (111).
2. The 3-phase charger, as claimed in claim 1, wherein the first phase voltage, the second phase voltage and the third phase voltage are equal in magnitude and frequency.
3. The 3-phase charger, as claimed in claim 1, wherein the second phase voltage is 120o out-of-phase with respect to the first phase voltage and the third phase voltage is 240o with respect to the first phase voltage.
4. The 3-phase charger, as claimed in claim 1, wherein the plurality of SiC switch pairs (102a and 102b, 102c and 102d, and 102e and 102f) operate in a complementary manner.
5. The 3-phase charger, as claimed in claim 1, wherein the plurality of capacitors (103a, 103b) form a DC link filter.
6. The 3-phase charger, as claimed in claim 1, wherein other end of the primary windings (107a, 108a, 109a) of the first, second and third transformers are connected to a mid-point of the capacitors (103a, 103b).
7. The 3-phase charger, as claimed in claim 1, wherein the ground terminal connects the middle point of secondary side windings to the negative terminal of the output filter capacitor (111) and the load (112).
8. The 3-phase charger, as claimed in claim 1, wherein the charger (100) comprises
an outer control loop (300B) for determining operating frequency for the SiC switch pairs (102a and 102b, 102c and 102d, and 102e and 102f); and
an inner control loop (300C) for determining a duty ratio of the SiC switch pairs (102a and 102b, 102c and 102d, and 102e and 102f).
9. The 3-phase charger, as claimed in claim 8, wherein the outer control loop (300B) comprises a voltage loop (300B1) and a current loop (300B2).
10. The 3-phase charger, as claimed in claim 11, wherein the outer control loop (300B) comprises
a compensator (301) for generating a reference signal;
a current loop compensator (303, 304) for generating a voltage corresponding to the operating frequency using the generated reference signal, wherein the current loop compensator (303, 304) comprises a compensator (303) and a Proportional + Resonant (PR) controller (304); and
a voltage-to-frequency (v-to-f) converter (305) for converting the generated voltage to an equivalent frequency.
11. The 3-phase charger, as claimed in claim 10, wherein the compensator (301, 303) is a proportional-integral (PI) compensator.
12. The 3-phase charger, as claimed in claim 8, wherein the inner control loop (300C) comprises a voltage loop (300C1) and a current loop (300C2).
13. The 3-phase charger, as claimed in claim 8, wherein the inner control loop (300C) comprises
a compensator (302) for generating a reference signal;
a product block for modulating the generated reference signal with a sinusoidal function of the first phase voltage, the second phase voltage and the third phase voltage respectively;
an error amplifier block for generating a current error using the modulated reference signal and a filtered inductor current through an external filter for each of the first phase voltage, the second phase voltage and the third phase voltage;
a plurality of compensator blocks (307a, 307b, and 307c) for generating a duty ratio error for each of the first phase voltage, the second phase voltage and the third phase voltage respectively;
a summation module for determining duty ratios for each of the first phase voltage, the second phase voltage and the third phase voltage using the generated duty ratio error for each of the first phase voltage, the second phase voltage and the third phase voltage and a feed-forward instantaneous duty ratio; and
a Pulse Width Modulation (PWM) generator (308) generating a gate signal using the determined duty ratios and the determined frequency.
14. The 3-phase charger, as claimed in claim 13, wherein the compensator (301, 303) is a proportional-integral (PI) compensator.
, Description:TECHNICAL FIELD
Embodiments disclosed herein relate to charging equipment and more particularly to using Silicon Carbide (SiC) based 3-phase input chargers for charging battery equipped devices.

BACKGROUND
Normally, a charger comprises of two power converter stages, wherein a first power converter stage converts AC to DC voltage which provides power factor correction and the second power converter stage converts DC to DC voltage with an isolation. Typically, the front end AC to DC conversion is performed by a boost converter, whereas the isolation with DC to DC conversion is provided by resonant converters. This two stage topology increases the component count and results in reduced efficiency, power density, and reliability.
All the existing single-stage topologies are restricted to single-phase input systems. Further, these converters use diode-bridge rectifiers at the front-end which limits their use for high power applications. The existing 3-phase input topologies are either two-stage or uses front-end diode bridge rectifier followed by resonant converter.
Further, the existing single-stage solutions are limited to single-phase input and are not scalable for 3-phase input systems. The existing single-stage AC/DC conversion without power factor correction introduces high ripple in output voltage. The devices in the existing single-stage topologies are subjected to high current and voltage stresses. Further, all the single-stage topologies uses front-end diode bridge rectifier which results in reduced efficiency in high power applications.
Further in the existing topologies, the intermediate bus voltage is adaptively varied to reduce the output voltage ripple, which adds to an additional controller complexities.

OBJECTS
The principal object of embodiments herein is to disclose a three-phase (3F) input single-stage topology for AC to DC conversion and DC-DC conversion, for use in chargers, wherein the charger uses wide band gap Silicon Carbide (SiC) devices.
These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating at least one embodiment and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.

BRIEF DESCRIPTION OF FIGURES
Embodiments herein are illustrated in the accompanying drawings, through out which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the drawings, in which:
FIG. 1 discloses a single-stage 3-phase input isolated AC/DC converter using a high breakdown voltage Silicon Carbide (SiC) device, according to embodiments as disclosed herein;
FIG. 2 depicts example input voltages of each phase for a complete cycle, according to embodiments as disclosed herein;
FIGs. 3A, 3B and 3C show the schematic of the closed-loop control, according to embodiments as disclosed herein;
FIGs. 4A, 4B and 4C depict the generation of duty ratios at different instants shown in FIG. 2, according to embodiments as disclosed herein;
FIG. 5 depicts the closed-loop simulated line voltage and its corresponding line (inductor) currents for all the three phases, according to embodiments as disclosed herein;
FIG. 6 depicts the simulated data for the variation in output power transfer considering each individual phases, according to embodiments as disclosed herein;
FIG. 7 depicts the total output power (Po) with all the three-phases combined, according to embodiments as disclosed herein;
FIG. 8 depicts the variable-frequency asymmetrical pulse-width modulation (VFAPWM) of the converter for different output power levels with respect to the 3-phase input voltage, according to embodiments as disclosed herein; and
FIG. 9 depicts an example closed-loop regulated output voltage and load current for 20~kW output power, according to embodiments as disclosed herein.

DETAILED DESCRIPTION
The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
The embodiments herein achieve a three-phase (3F) input single-stage topology for AC to DC conversion and DC-DC conversion, for use in chargers, wherein the charger uses wide band gap Silicon Carbide (SiC) devices. Referring now to the drawings, and more particularly to FIGS. 1 through 9, where similar reference characters denote corresponding features consistently throughout the figures, there are shown embodiments.
Embodiments herein disclose a single-stage topology for a charger for performing AC to DC conversion with isolation for 3-phase input using (Silicon Carbide) SiC devices.
FIG. 1 discloses a single-stage 3-phase input isolated AC/DC converter 100 using a high breakdown voltage Silicon Carbide (SiC) device. The input to the system v_1, v_2 and v_3 are the phase voltages of 3-phase AC power supply. The phase voltages (v_1, v_2 and v_3) are also referred to herein as a first voltage, a second voltage, and a third voltage respectively. The phase voltages v_1, v_2 and v_3 are equal in magnitude and frequency, but v_2 is 120o out-of-phase with respect to v_1 and v_3 is 120o out-of-phase with respect to v_2 or 240o with respect to v_1.
Each phase voltage is connected to a plurality of half-bridge configured SiC switches (Q_1 102a and Q_2 102b, Q_3 102c and Q_4 102d, and Q_5 102e and Q_6 102f) through boost inductors (L_1 101a, L_2 101b and L_3 101c) respectively. The phase voltage v_1 is connected to a first pair of SiC transistors Q_1 102a and Q_2 102b (hereinafter referred to collectively as a SiC pair or a switch pair) (i.e., switches) through a first boost inductor L_1 101a. In an example herein, the SiC transistors Q_1 102a and Q_2 102b are Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) transistors. The phase voltage v_2 is connected to a second pair of SiC transistors Q_3 102c and Q_4 102d (hereinafter referred to collectively as a SiC pair or a switch pair) (i.e., switches) through a second boost inductor L_2 101b. In an example herein, the SiC transistors Q_3 102c and Q_4 102d are MOSFET transistors. The phase voltage v_3 is connected to a third pair of SiC transistors Q_5 102e and Q_6 102f (hereinafter referred to collectively as a SiC pair or a switch pair) (i.e., switches) through a third boost inductor L_3 101c. In an example herein, the SiC transistors Q_5 102e and Q_6 102f are MOSFET transistors. Consider that iL1, iL2, and iL3 are the current through the inductors L1 101a, L2 101b, and L3 101c, respectively.
Each of the switch pairs operate in a complementary manner. When Q_1 102a is ON, Q_2 102b is OFF and when Q_2 102b is ON, Q_1 102a is OFF. When Q_3 102c is ON, Q_4 102d is OFF and when Q_4 102d is ON, Q_3 102c is OFF. When Q_5 102e is ON, Q_6 102f is OFF and when Q_6 102f is ON, Q_5 102e is OFF.
The capacitors C_1 103a and C_2 103b form the DC link filter capacitor and are connected in series. The series connected capacitors C_1 103a and C_2 103b are further connected in parallel with the SiC switch pairs (Q_1 102a, Q_2 102b), (Q_3 102c, Q_4 102d) and (Q_5 102e, Q_6 102f).
Node A 104a, which is formed by the inductor L_1 101a and switches Q_1 102a and Q_2 102b, is connected to the primary winding L_11 107a of a first transformer T_1 107 through the resonant capacitor C_r1 105a and resonant inductor L_r1 106a. Node B 104b, which is formed by the inductor L_2 101b and switches Q_3 102c and Q_4 102d, is connected to the primary winding L_21 108a of a second transformer T_2 108 through the resonant capacitor C_r2 105b and resonant inductor L_r2 106b. Node C 104c, which is formed by the inductor L_3 101c and switches Q_5 102e and Q_6 102f, is connected to primary winding L_31 109a of a third transformer T_3 109 through the resonant capacitor C_r3 105c and resonant inductor L_r3 106c. The other ends of all the primary windings L_11 107a, L_21 108a, and L_31 109a are connected to a node D 104d. Node D 104d is the mid-point of series connected DC link capacitors C_1 103a and C_2 103b.
The secondary winding of the transformers 107, 108, and 109 are divided into two portions, wherein each portion comprises an equal number of turns (L12 107b and L13 107c), (L22 108b and L23 108c) and (L32 109b and L33 109c) respectively. Each middle point (center tap) of the secondary winding is connected to the ground terminal of the respective secondary winding and this allows the transformer to provide two separate secondary voltages, which are equal in magnitude, but opposite in polarity. This ground terminal connects the middle point of secondary side windings to the negative terminal of an output filter capacitor C 111 and the load 112. The other end of each portion of the secondary side transformer windings of the T1 107 (L_12 107b and L_13 107c) are connected to the positive terminal of the output filter capacitor C 111 through the diodes D_11 110a and D_12 110b, respectively. The other end of the secondary side transformer windings of the T2 108 (L_22 108b and L_23 108c) are connected to the positive terminal of the output filter capacitor C 111 through the diodes D_21 110c and D_22 110d, respectively. The other end of the secondary side transformer windings of the T3 109 (L_32 109b and L_33 109c) are connected to the positive terminal of the output filter capacitor C 111 through the diodes D_31 110e and D_32 110f, respectively. The load 112 is connected in parallel with the capacitor C 111 and is supplied with DC power. The load 112 can be any device/module/system, that is being charged by the charger as depicted in FIG. 1. Examples of the load 112 are, but not limited to, a vehicle, a battery in a vehicle, an electronic device, and so on.
Embodiments herein integrate the first-stage PFC (Power Factor Controller) and the second-stage LLC converter to form a single-stage topology. As shown in FIG. 1, the controllable switches are common for both PFC and LLC stages. Embodiments herein parallel the output stage LLC converter for high power (fast) charging applications. This reduces the switching and driving requirements, thereby the driving losses of the converter. The input voltages of each phase for a complete cycle is shown in the example in FIG. 2. The input voltages can be subdivided into 6 intervals based on the criteria that any one of the phase voltage is zero. Embodiments herein regulate the DC link voltage at a pre-defined voltage level (such as, 1000V) throughout the operation. Thus, the duty ratio for each half-bridge leg can be calculated as
d=0.5-(v_in sin?wt)/v_DC
Where
v_in= Peak amplitude of input phase voltage
v_DC= DC link voltage
In an example, consider that the DC link voltage is 1000V, the range of duty ratio for the controllable switch can be at a maximum of 0.5, when the phase voltage is zero and at a minimum of 0.17 at the peak voltage. For any phase, the duty-cycle greater than 0.5 implies the controllable switch and the synchronous switch are interchanged for that phase.
FIGs. 3A, 3B and 3C show the schematic of the closed-loop control. As shown in the figure, the outer control loop (FIG. 3B - 300B) regulates the output voltage v_o of the converter (FIG. 1 and FIG. 3A – 300A), whereas the DC link voltage v_DC is regulated by the inner control loop (FIG. 3C – 300C). Using the output of inner control loop (FIG. 3A – 300A) and outer control loop (FIG. 3B – 300B), the PWM generator 308 generates the gate signals for all switch pairs.
The outer control loop comprises of two loops; a voltage loop 300B1 and a current loop 300B¬2. Using the error (v_ref-v_o) (where v_ref is the reference voltage (for example, 400V)), the voltage-loop compensator G_C 301 generates a reference signal for the current-loop. Then using the current error i_e, the current-loop compensator 303, 304 (a combination of G_C 303 and a Proportional + Resonant (PR) controller 304) generates the controlled voltage corresponds to the required pulse frequency of operation. This voltage is mapped to an equivalent frequency using a voltage-to-frequency converter (v-to-f) 305.
The inner control loop 300C comprises of two loops; a voltage loop 300C1 and a current loop 300C2. Using the error voltage (v_(DC,ref)-v_DC ), the voltage-loop compensator G_C 302 generates the current reference signal for the inner current-loop. This current reference is modulated with the sinusoidal function of each phase voltage. This is achieved by multiplying Sin (?t-?), where ?=?0,+120?^o,-120^o for the phase v_1, v_2, and v_3, respectively. Then, using this output of the product block and the filtered inductor (line) current, an error amplifier block generates the current error for the respective phases. The error amplifier block can generate the current error using the modulated reference signal for each phase and a respective filtered inductor current for each phase. The filtered inductor current of each phase is obtained using an external filter which is represented in FIG.3B-300C as G_FIL 306a , G_FIL 306b, and G_FIL 306c, respectively. Using this current error, the inner current-loop compensators G_C 307a, G_C 307b and G_C 307c generates the duty ratio error for respective switch pairs and upon adding with the feed-forward instantaneous duty ratio, the duty ratio control output ?(d?_1 ?,d?_2,d_3) for the respective phases are generated by a summation module. Using this duty ratio information and the output of v-to-f converter 305, a Pulse Width Modulation (PWM) generator 308 generates the gate-signal for respective switch pairs.
Embodiments herein consider the feedback compensators G_C 301, 302, 303, 307a, 307b, 307c as a proportional-integral (PI) compensator. However, it may be obvious to a person of ordinary skill that the compensator G_C 301, 302, 303, 307a, 307b, 307c can be of any type, such as, but not limited to, (proportional-integral-derivative) PID, PI + two-pole, 3rd Order or higher.
FIGs. 4A, 4B and 4C depict the generation of duty ratios at different instants I, II, and III (as shown in FIG. 2). The case I corresponds to the instant when the phase voltage v_1 is zero. Case II and Case III correspond to the instant when the phase voltages v_3=0 and v_2=0 respectively. The duty-cycle is generated by comparing the respective control signal (d_1, d_2,d_3) with the saw-tooth waveform of amplitude v_r and frequency of outer-loop F_s. The gate signal turns on when the respective phase control input is greater than the saw-tooth waveform. The gate signal turns off once the saw-tooth waveform crosses the control input.
FIG. 5 depicts the closed-loop simulated line voltage and its corresponding line (inductor) currents for all the three phases. It can be observed from the figure that all the line currents are in-phase with the line voltage, thus the improved power factor is achieved.
FIG. 6 depicts the simulated data for the variation in output power transfer considering each individual phases. It can be observed from the simulated result that the power transfer is maximum when the grid voltage is near the zero crossing and it is minimum at the peak of the grid voltage. However, in three-phase input system when one phase voltage is at the peak, any of the other phases which is near the zero crossing transfers the maximum power. Thus, there is always a continuous transfer of power and it is maximum when the combined voltage of all three phases is minimum, as shown in FIG. 7. This paralleling at the output side further reduces the output voltage ripple; thus, smaller value of filter capacitance is sufficient. Further, in embodiments disclosed herein, the intermediate bus voltage is maintained at around 1000 V (more than twice that of the line-to-line input voltage) throughout the charger operation. This improves the total harmonic distortion (THD) and reduces the input current distortion.
FIG. 8 depicts the VFAPWM for different output power levels with respect to the 3-phase input voltage. FIG. 8b shows the v-to-f converter output of outer-loop control for different output power levels with respect to the 3-phase input voltage shown in FIG. 8a. The outer current-loop PR controller is designed to have a resonant frequency of 300Hz, which is six times the frequency of input voltage, which is also evident from the v-to-f converter output shown in FIG. 8b. It can also be observed from the simulation that as the power level (load current) increases, the switching frequency decreases. When the output power level is 10~kW, the LLC (output) stage almost operates exactly at the resonant frequency; thus, the operating frequency at 10~kw is almost constant whereas for the other power levels (15~kW and 30 ~kW), the operating frequency oscillates within 5~kHz band throughout the operating region. FIG. 8c shows the duty cycle command ?(d?_1) for the v_1 phase half-bridge MOSFETs (Q_1 102a,Q_2 102b). For the first-half cycle, the duty ratio of Q_1 is always less than 0.5, whereas for the next half-cycle it is greater than 0.5.
FIG. 9 depicts an example closed-loop regulated output voltage and load current for 20~kW output power. FIG. 9(a) depicts the Input (Line) voltage. FIG. 9(b) depicts the Line (Inductor) currents of all phases. FIG. 9(c) depicts the output voltage (vo). FIG. 9(d) depicts the Load current (io). It can be observed that using a filter cap of 1500~uF, the peak-to-peak output voltage ripple is less than 1~V. Further, the output voltage is regulated at 400~V using the embodiments disclosed herein.
Embodiments herein improve the reliability and efficiency of the charger by using a very high power density and low part count. Embodiments herein perform both the function of power factor correction and isolation. Embodiments herein maintain the intermediate DC bus voltage irrespective of input and output operating conditions. Embodiments disclosed herein result in reduced output voltage ripple; hence a small value of output filter capacitance is sufficient. Embodiments herein enable an increase in the operating power level without any topology modification. Embodiments herein enable regulation of the output voltage by nullifying the voltage ripple using the resonant controller. Embodiments herein realize the proposed high power converter using SiC devices because of its high breakdown voltage and fast switching characteristics, which makes embodiments disclosed herein suitable for very high power charging applications.
The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of embodiments and examples, those skilled in the art will recognize that the embodiments and examples disclosed herein can be practiced with modification within the spirit of the embodiments as described herein.