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Decoder

Abstract: There are disclosed techniques for decoding and/or generating an audio signal and training an audio decoder and/or generator. An audio decoder (10), configured to generate an audio signal (16) from a bitstream (3), the bitstream (3) representing the audio signal (16), the audio signal being subdivided in a sequence of frames. The audio decoder (10) comprises: a first data provisioner (702) to provide first data (15), the first data (15) having mul- tiple channels; a first processing block (40, 50, 50a-50h) to output first output data (69) having mul- tiple channels (47), and a second processing block (45). The first processing block (50) comprises: a learnable layer (710) to receive the bitstream (3) and, for the given frame, output target data (12) representing the audio signal (16) in the given frame with multiple channels and multiple samples for the given frame; a conditioning learnable layer (71, 72, 73) to process the target data (12) to obtain conditioning feature parameters (74, 75) for the given frame; and a styling element (77) applying the conditioning feature parameters (74, 75) to the first data (15, 59a). The second processing block (45) combines the plurality of channels (47) of the second data (69) to obtain the audio signal (16).

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
26 October 2023
Publication Number
37/2024
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
Parent Application

Applicants

FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Hansastraße 27c 80686 München

Inventors

1. AHMED, Ahmed Mustafa Mahmoud
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS Am Wolfsmantel 33 91058 Erlangen
2. PIA, Nicola
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS Am Wolfsmantel 33 91058 Erlangen
3. BÜTHE, Jan
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS, Am Wolfsmantel 33 91058 Erlangen
4. KORSE, Srikanth
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS Am Wolfsmantel 33 91058 Erlangen
5. GUPTA, Kishan
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS, Am Wolfsmantel 33 91058 Erlangen
6. MULTRUS, Markus
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS, Am Wolfsmantel 33 91058 Erlangen
7. FUCHS, Guillaume
c/o Fraunhofer-Institut für Integrierte Schaltungen IIS Am Wolfsmantel 33 91058 Erlangen

Specification

Documents

Application Documents

# Name Date
1 202317073032-STATEMENT OF UNDERTAKING (FORM 3) [26-10-2023(online)].pdf 2023-10-26
2 202317073032-REQUEST FOR EXAMINATION (FORM-18) [26-10-2023(online)].pdf 2023-10-26
3 202317073032-NOTIFICATION OF INT. APPLN. NO. & FILING DATE (PCT-RO-105-PCT Pamphlet) [26-10-2023(online)].pdf 2023-10-26
4 202317073032-FORM 18 [26-10-2023(online)].pdf 2023-10-26
5 202317073032-FORM 1 [26-10-2023(online)].pdf 2023-10-26
6 202317073032-DRAWINGS [26-10-2023(online)].pdf 2023-10-26
7 202317073032-DECLARATION OF INVENTORSHIP (FORM 5) [26-10-2023(online)].pdf 2023-10-26
8 202317073032-COMPLETE SPECIFICATION [26-10-2023(online)].pdf 2023-10-26
9 202317073032-FORM-26 [17-01-2024(online)].pdf 2024-01-17
10 202317073032-Proof of Right [02-02-2024(online)].pdf 2024-02-02
11 202317073032-Others-090224.pdf 2024-03-01
12 202317073032-Correspondence-090224.pdf 2024-03-01
13 202317073032-FORM 3 [07-03-2024(online)].pdf 2024-03-07