FORM 2
THE PATENTS ACT, 1970 (39 OF 1970) & THE PATENT RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)
“AN OUTDOOR SMALL CELL (ODSC) SYSTEM”
We, Jio Platforms Limited, an Indian National, of Office - 101, Saffron, Nr. Centre Point, Panchwati 5 Rasta, Ambawadi, Ahmedabad - 380006, Gujarat, India.
The following specification particularly describes the invention and the manner in which it is to be performed.

AN OUTDOOR SMALL CELL (ODSC) SYSTEM
FIELD OF THE DISCLOSURE
5
[0001] Embodiments of the present disclosure generally relate to wireless communication systems. More particularly, embodiments of the present disclosure relates to an outdoor small cell (ODSC) system such as a Sub-6GHz 5th generation (5G) new radio (NR) four Transmit four Receive (4T4R) configuration ODSC system. 10
BACKGROUND OF THE DISCLOSURE
[0002] The following description of the related art is intended to provide background
information pertaining to the field of the disclosure. This section may include certain aspects
15 of the art that may be related to various features of the present disclosure. However, it should
be appreciated that this section is used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of the prior art.
[0003] Wireless communication technology has rapidly evolved over the past few decades,
20 with each generation bringing significant improvements and advancements. The first
generation of wireless communication technology was based on analog technology and offered
only voice services. However, with the advent of the second-generation (2G) technology,
digital communication and data services became possible, and text messaging was introduced.
Third generation (3G) technology marked the introduction of high-speed internet access,
25 mobile video calling, and location-based services. The fourth generation (4G) technology
revolutionized wireless communication with faster data speeds, better network coverage, and
improved security. Currently, the fifth generation (5G) technology is being deployed,
promising even faster data speeds, low latency, and the ability to connect multiple devices
simultaneously. With each generation, wireless communication technology has become more
30 advanced, sophisticated, and capable of delivering more services to its users.
[0004] Moreover, the 5G networks are generally based on small cell technology. Small cells use low-power and short-range wireless transmission systems (or base stations). A small geographical area or small-proximity indoor and outdoor space is covered by the small cells in
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the 5G networks. Also, 5G new radio (NR) outdoor small cell (ODSC) is medium power gNB
(next generation node B) which operates in micro class (typically 6.25 W or 38dBm per antenna
port). It complements macro-level wide-area solutions for coverage and capacity and is
particularly useful in hot zone/hot spot areas with high traffic and quality of service (QoS)
5 demands.
[0005] While a Macro gNB can offer satisfactory coverage and capacity in many situations, dense urban environments with tall buildings may experience intermittent mobile coverage issues. Simply adding more radio signal towers becomes impractical. Similarly, meeting the
10 high capacity demands of numerous mobile users in commercial hubs such as malls, hotels,
office blocks, and transportation hubs poses significant challenges. In such scenarios, deploying 5G Outdoor small cell (ODSC) solutions in hotspot locations becomes essential to enhance coverage and capacity, complementing the capabilities of 4G/5G gNB. This efficiently addresses the increased traffic demands in these areas.
15
[0006] As the ODSCs play an important role in the 5G networks, there is a requirement to optimize the cost and performance of these ODSCs. Currently, there is no existing solution to optimize the cost and performance of the ODSCs in an effective and efficient manner. Therefore, there is a need in the art to provide a cost and performance optimized outdoor small
20 cell design, for instance a cost and performance optimized Sub-6GHz 5G new radio (NR) 4T4R
Outdoor Small Cell (ODSC).
[0007] Thus, there exists an imperative need in the art to provide an optimised outdoor small cell (ODSC) system, which the present disclosure aims to address. 25
OBJECTS OF THE INVENTION
[0008] Some of the objects of the present disclosure, which at least one embodiment disclosed herein satisfies are listed herein below. 30
[0009] It is an object of the present disclosure to provide a solution that can enable a cost and performance optimized outdoor small cell (ODSC) design to provide an improved ODSC.
3

[0010] It is another object of the present disclosure to provide a solution that can provide an overall integrated system having a network processor (NW) processor and Field-Programmable Gate Arrays (FPGA) and/or Application-Specific Integrated Circuits (ASIC) for Baseband Transceiver on eighteen or more layers of a printed circuit board (PCB). 5
[0011] It is also an object of the present disclosure to provide a L1 layer development and bit stream generation in Field-Programmable Gate Arrays (FPGA) and/or Application-Specific Integrated Circuits (ASIC).
10 [0012] It is yet another object of the present disclosure to provide a solution that can provide
clock synchronization architecture using system synchronizer integrated circuit (IC).
[0013] It is yet another object of the present disclosure to provide a solution that can provide blind mating and cable less design in ODSC.
15
[0014] It is yet another object of the present disclosure to provide a solution that can achieve cost optimization of ODSC by eliminating the need for external power amplifier (PA) bias circuitry due to availability of on-chip biasing, by utilizing an off-the-shelf power-efficient 50-ohm matched power amplifier module (PAM).
20
[0015] It is yet another object of the present disclosure to provide improvement in the System Noise Figure resulting radio frequency (RF) Receiver sensitivity improvement and cost optimization by utilizing the off-the-shelf dual channel low noise amplifier (LNA) having sub 1dB Noise Figure (NF) in ODSC.
25
[0016] It is yet another object of the present disclosure to optimise the layout design of the ODSC to minimize RF trace losses on the top layers, thereby further minimizing degradation in the overall system noise figure (NF).
30 [0017] It is yet another object of the present disclosure to provide a solution that can achieve
cost optimization in the feedback path (reverse power determination circuitry) of RF frontend board section of the ODSC by implementing fixed attenuation using passive components instead of Digital Step Attenuator and control circuitry.
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[0018] It is yet another object of the present disclosure to provide a solution that can provide
in ODSC an external -48V input DC voltage which passes through a common electromagnetic
interference (EMI) / electromagnetic compatibility (EMC) input choke filter and then down
converts it to first 28V and 12V concurrently using industry standard bricks and then various
5 lower voltages, for cost and performance optimisation in ODSC.
SUMMARY OF THE DISCLOSURE
[0019] This section is provided to introduce certain aspects of the present disclosure in a
10 simplified form that are further described below in the detailed description. This summary is
not intended to identify the key features or the scope of the claimed subject matter.
[0020] An aspect of the present disclosure may relate to an outdoor small cell (ODSC) system. The ODSC system comprises a housing unit. The housing unit is configured to house at least
15 an integrated baseband and transceiver board (IBTB), a radio frequency front end board
(RFFEB), a cavity filter, and a multiple-input multiple-output (MIMO) antenna. The IBTB is configured to: (a) receive an external input direct current (DC) voltage, (b) pass the external input DC voltage through a common electromagnetic interference (EMI) and electromagnetic compatibility (EMC) input choke filter, and (c) down convert the external input DC voltage to
20 a plurality of signals concurrently. Further, the radio frequency front end board (RFFEB) is
blind mated to the IBTB. The RFFEB is configured to: a) receive a set of control signals from the IBTB along with a power supply through a connector Radio Frequency (RF) Front-End Control Interface Board, and b) provide a fixed attenuation in a feedback path of the RFFEB.
25 [0021] In an exemplary aspect of the present disclosure, the IBTB comprises a network
processor connected to at least a backhaul and a power supply unit. Further, the IBTB comprises a baseband processor chipset for L2 layer processing and L3 layer processing. Further, the IBTB comprises a field-programmable gate array (FPGA) chipset for L1 layer processing. Further, the IBTB comprises one or more temperature sensors for measuring a
30 temperature of one or more sections of the IBTB and for enabling an automatic action in an
event of a detection of thermal failure. Further, the IBTB comprises one or more transceivers for monitoring a power amplifier output by measuring a received power on an Analogue-to-Digital Converter (ADC) of the IBTB during utilization of a feedback chain. Further, the IBTB comprises a clock and synchronization circuit connected to at least the baseband processor
5

chipset and the one or more transceivers, wherein the clock and synchronization circuit is
configured to synchronize the IBTB with one or more units connected to the ODSC system,
and wherein the clock and synchronization circuit comprises at least one or more ultra-low
noise clock generation phase-locked loops (PLLs), a programmable oscillator and a system
5 synchronizer integrated circuit (system synchronizer IC).
[0022] In an exemplary aspect of the present disclosure, the clock and synchronization circuit is configured based on one of a Global Positioning System (GPS), a Precision Time Protocol (PTP), a Holdover technique and one or more clock generators. 10
[0023] In an exemplary aspect of the present disclosure, the external input DC voltage is received by the IBTB from a power supply unit, and wherein the external input DC voltage is in a range of -40V to -57V.
15 [0024] In an exemplary aspect of the present disclosure, the IBTB is designed on eighteen or
more layers of a printed circuit board (PCB) and wherein the PCB is based on a design protocol to route one or more signals between the eighteen or more layers.
[0025] In an exemplary aspect of the present disclosure, the IBTB is configured to down
20 convert the -48V input DC voltage to: (a) a 28V output signal and a 12V output signal
concurrently, based on one or more industry standard bricks, and (b) further convert the 28V
output signal and the 12V output signal to a set of target voltage output signals based on a set
of requirements of a set of devices connected to the IBTB, wherein the 28V output signal, the
12V output signal and the set of target voltage output signals are generated using at least one
25 of a power management integrated chipset (PMIC), one or more DC-DC converters and one or
more Linear and low-dropout (LDO) regulators devices.
[0026] In an exemplary aspect of the present disclosure, the RFFEB comprises a RF time
division duplex (TDD) switch. Further, the RFFEB comprises at least four transmit chains for
30 signal transmission, wherein each transmit chain from the four transmit chains carries matching
Balun, pre-driver amplifier and final RF power amplifier as final stage power amplifier (PA). Further, the RFFEB comprises four receive chains for signal reception, wherein one or more pairs of dual channels low noise amplifiers (LNAs) cater to two receive chains from the four receive chains having band pass surface acoustic wave (SAW) filter and a matching network.
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Further, the RFFEB comprises four observation chains which function as digital pre-distortion (DPD) feedback paths from one or more power amplifier modules (PAMs) to at least one of a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) for linearization. 5
[0027] In an exemplary aspect of the present disclosure, each PAM from the one or more PAMs is an off-the-shelf power efficient 50-ohm matched PAM.
[0028] In an exemplary aspect of the present disclosure, each pair of dual channels LNA from
10 the one or more pairs of dual channels LNAs has a sub 1dB Noise Figure (NF) for minimizing
RF trace losses on one or more top layers in the ODSC system.
[0029] In an exemplary aspect of the present disclosure, the RFFEB is configured to provide
the fixed attenuation for optimizing a cost in the feedback path of the RF frontend board section
15 of the ODSC.
[0030] In an exemplary aspect of the present disclosure, the cavity filter comprises a four-port cavity filter for a four Transmit four Receive (4T4R) configuration providing a steeper roll-off outside an operating band. 20
[0031] In an exemplary aspect of the present disclosure, the MIMO antenna comprises four-port cross-polarized patch antennas for the 4T4R configuration.
[0032] In an exemplary aspect of the present disclosure, the IBTB is configured to down
25 convert the external input DC voltage to the plurality of signals concurrently, based on one or
more industry standard bricks.
DESCRIPTION OF THE DRAWINGS
30 [0033] The accompanying drawings, which are incorporated herein, and constitute a part of
this disclosure, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Also, the embodiments shown in the
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figures are not to be construed as limiting the disclosure, but the possible variants of the method
and system according to the disclosure are illustrated herein to highlight the advantages of the
disclosure. It will be appreciated by those skilled in the art that disclosure of such drawings
includes disclosure of electrical components or circuitry commonly used to implement such
5 components.
[0034] FIG. 1 illustrates an exemplary block diagram of an outdoor small cell (ODSC) system [100], in accordance with exemplary embodiments of the present disclosure.
10 [0035] FIG. 1a illustrates an exemplary block diagram of an integrated baseband and
transceiver board (IBTB) [102], in accordance with exemplary embodiments of the present disclosure.
[0036] FIG. 1b illustrates an exemplary block diagram of a radio frequency front end board
15 (RFFEB) [104], in accordance with exemplary embodiments of the present disclosure.
[0037] FIG. 1c illustrates an exemplary block diagram depicting a clock and synchronization circuit [110] in connection with network processor [102a] and FPGA/ASIC [102f], in accordance with exemplary embodiments of the present disclosure. 20
[0038] FIG. 2 illustrates an exemplary high-level block diagram of a four-transmitter-four-receiver 5th generation new radio outdoor small cell (4T4R 5G NR ODSC) [100], in accordance with exemplary embodiments of the present disclosure.
25 [0039] FIG. 3 illustrates an exemplary circuit diagram of transmission (Tx) and receiver (Rx)
Chain pair of RF Front End Board (RFFEB) [104], in accordance with exemplary embodiments of the present disclosure.
[0040] FIG. 4 illustrates an exemplary block diagram of a power supply unit for the IBTB
30 [102] in accordance with exemplary embodiments of the present disclosure.
[0041] The foregoing shall be more apparent from the following more detailed description of the disclosure.
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DETAILED DESCRIPTION
[0042] In the following description, for the purposes of explanation, various specific details
are set forth in order to provide a thorough understanding of embodiments of the present
5 disclosure. It will be apparent, however, that embodiments of the present disclosure may be
practiced without these specific details. Several features described hereafter may each be used independently of one another or with any combination of other features. An individual feature may not address any of the problems discussed above or might address only some of the problems discussed above.
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[0043] The ensuing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may
15 be made in the function and arrangement of elements without departing from the spirit and
scope of the disclosure as set forth.
[0044] Specific details are given in the following description to provide a thorough
understanding of the embodiments. However, it will be understood by one of ordinary skill in
20 the art that the embodiments may be practiced without these specific details. For example,
circuits, systems, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail.
[0045] The word “exemplary” and/or “demonstrative” is used herein to mean serving as an
25 example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed
herein is not limited by such examples. In addition, any aspect or design described herein as
“exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or
advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary
structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent
30 that the terms “includes,” “has,” “contains,” and other similar words are used in either the
detailed description or the claims, such terms are intended to be inclusive—in a manner similar to the term “comprising” as an open transition word—without precluding any additional or other elements.
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[0046] As used herein, a “processing unit” or “processor” or “operating processor” includes
one or more processors, wherein processor refers to any logic circuitry for processing
instructions. A processor may be a general-purpose processor, a special purpose processor, a
conventional processor, a digital signal processor, a plurality of microprocessors, one or more
5 microprocessors in association with a (Digital Signal Processing) DSP core, a controller, a
microcontroller, Application Specific Integrated Circuits, Field Programmable Gate Array
circuits, any other type of integrated circuits, etc. The processor may perform signal coding
data processing, input/output processing, and/or any other functionality that enables the
working of the system according to the present disclosure. More specifically, the processor or
10 processing unit is a hardware processor.
[0047] As used herein, “a user equipment”, “a user device”, “a smart-user-device”, “a smart-device”, “an electronic device”, “a mobile device”, “a handheld device”, “a wireless communication device”, “a mobile communication device”, “a communication device” may be any electrical, electronic and/or computing device or equipment. The user equipment/device may include, but is not limited to, a mobile phone, smart phone, laptop, a general-purpose computer, desktop, personal digital assistant, tablet computer, wearable device or any other computing device. Also, the user device may contain at least one input means configured to receive an input from unit(s) which are required to implement the features of the present disclosure.
[0048] Further, in accordance with the present disclosure, it is to be acknowledged that the functionality described for the various components/units can be implemented interchangeably. While specific embodiments may disclose a particular functionality of these units for clarity, it
25 is recognized that various configurations and combinations thereof are within the scope of the
disclosure. The functionality of specific units as disclosed in the disclosure should not be construed as limiting the scope of the present disclosure. Consequently, alternative arrangements and substitutions of units, provided they achieve the intended functionality described herein, are considered to be encompassed within the scope of the present disclosure.
30
[0049] As discussed in the background section, the current known solutions have several shortcomings. The present disclosure aims to overcome the above-mentioned and other existing problems in this field of technology by providing an improved outdoor small cell (ODSC) system. The present disclosure aims to overcome the above-mentioned and other
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existing problems in this field of technology by providing a solution for enabling a cost and
performance optimized outdoor small cell design to provide a cost and performance optimized
ODSC, for instance a cost and performance optimized Sub-6GHz 5G new radio (NR) 4T4R
Outdoor Small Cell (ODSC). The 5G NR gNB brings together an application layer, media
5 access control (MAC) layer and baseband layer based on Baseband Processor chipset, radio
frequency (RF) transceiver based on field programmable gate array (FPGA) and RF front end module (FEM) which includes RF power amplifiers, Low noise amplifiers (LNA), RF switch and cavity filter—all in a passively cooled enclosure. Mainly, the 5G NR Outdoor Small cell of the proposed solution has a design that is compact with integrated antenna solution without
10 any use of cable, thus, making it a cable-less design. It can be easily installed on Tower sites
and Lampposts. It is quick to deploy and delivers high performance with low power consumption, thus, making it a power efficient solution. It offers two 1Gbps Fiber Optic connections (e.g., small form-factor pluggable (SFP) connections) as a backhaul connection to networks.
15
[0050] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. Also, some features of Fig. 1, Fig. 1a, Fig. 1b, Fig. 1c, and Fig. 2 may be used in conjunction with each other for clarity of explanation in this disclosure.
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[0051] Referring to Figure 1, an exemplary block diagram of an outdoor small cell (ODSC) system [100], is shown, in accordance with the exemplary implementations of the present disclosure. The ODSC system [100] comprises at least one housing unit [101] that encompasses at least one integrated baseband and transceiver board (IBTB) [102], at least one radio
25 frequency front end board (RFFEB) [104], at least one cavity filter [106], and at least one
multiple-input multiple-output (MIMO) antenna [108], however the present disclosure is not limited thereto and the improved ODSC system [100] may also include other known units or components to facilitate one or more functionalities of the ODSC system [100]. Also, all of the components/ units of the ODSC system [100] are assumed to be connected to or in
30 communication with each other unless otherwise indicated below. Also, in Fig. 1 only a few
units are shown, however, the ODSC system [100] may comprise multiple such units or the ODSC system [100] may comprise any such numbers of said units, as required to implement the features of the present disclosure. Further, in an implementation, the ODSC system [100] may be in communication with the user device (may also referred herein as a UE). In another
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implementation, the ODSC system [100] may reside at a network end. It will be appreciated by those skilled in the art that disclosure of such drawings/block diagrams includes disclosure of electrical components and connections between said electronic components, and electronic components or circuitry commonly used to implement such components. 5
[0052] Further, an exemplary block diagram of the IBTB [102] is depicted in FIG. 1a, in accordance with exemplary embodiments of the present disclosure. Also, an exemplary block diagram of the RFFEB [104] is depicted in FIG. 1b, in accordance with exemplary embodiments of the present disclosure. Additionally, an exemplary block diagram depicting
10 the clock and synchronization circuit [110] integrated at the (IBTB) [102] is shown in FIG. 1c, in accordance with exemplary embodiments of the present disclosure. Unless otherwise indicated below, in an implementation of the present disclosure, one or more units or components as shown in Fig. 1, Fig. 1a, Fig. 1b, Fig. 1c may be connected to each other in a manner that is obvious to a person skilled in the art to implement the features as disclosed in
15 the present disclosure.
[0053] Also, in an implementation, the ODSC system [100] may be an improved four-transmitter-four-receiver 5th generation new radio outdoor small cell (4T4R 5G NR ODSC) [200]. FIG. 2 illustrates an exemplary high-level (i.e., overview) block diagram of the four-
20 transmitter-four-receiver (4T4R) 5th generation (5G) new radio (NR) outdoor small cell (ODSC) (4T4R 5G NR ODSC) [200], in accordance with exemplary embodiments of the present disclosure. The improved ODSC system [100] or the 4T4R 5G NR ODSC may be, but is not limited to, a medium power gNB (next generation Node B) which operates in micro class (typically ≤ 38dBm per antenna port, but the disclosure is not limited thereto). It complements
25 macro-level wide-area network solutions for coverage and capacity and is particularly useful in hot zone/hot spot areas with high traffic and Quality of Standard (QoS) demands. As shown in FIG.1 / FIG. 2 the improved ODSC system [100] / the 4T4R 5G NR ODSC [200] is an integration of different boards and Sub-Modules / Sub-Units.
30 [0054] Particularly, the outdoor small cell (ODSC) system [100] comprises a housing unit [101]. Further, the housing unit [101] is configured to house at least the integrated baseband and transceiver board (IBTB) [102], the radio frequency front end board (RFFEB) [104], the cavity filter [106], and the multiple-input multiple-output (MIMO) antenna [108]. In an implementation, the IBTB [102] is designed on eighteen or more layers of a printed circuit
12

board (PCB) wherein the PCB is based on a design protocol to route one or more signals between the eighteen or more layers.
[0055] The IBTB [102] is configured to receive an external input direct current (DC) voltage.
5 Further, the IBTB [102] is configured to pass the external input DC voltage through a common
electromagnetic interference (EMI) and electromagnetic compatibility (EMC) input choke filter. Here, an EMI filter (Electromagnetic interference filter) is an electrical device or circuit used to suppress or filter out high-frequency noise current present on power and signal lines, i.e., it suppresses the conducted EMI on power and signal lines. By filtering out the noise
10 current, the EMI filter protects sensitive electronic devices/systems connected on the line from
harmful impacts of such noise current and ensures reliable operation of the devices. Further, an EMC filter is used for suppressing line-conducted interferences. Integrating EMC/EMI filters directly into the power unit results in higher power density. A common EMI/EMC input choke filter may combine low losses, low voltage drops, minimal signal impact with efficient
15 EMC/EMI filtering.
[0056] Further, once the external input direct current (DC) voltage is received at the IBTB [102], the IBTB [102] is then configured to down convert the external input DC voltage to a plurality of signals concurrently, based on one or more industry standard bricks. These industry
20 standard brick(s) refer to a power brick(s), that may be an AC to DC or DC to DC power
converter which can be mounted on a printed circuit board (PCB). These power bricks are built like switched power supplies and consist of components such as switching transistors, switching controllers and energy storage devices. The power bricks may step down or boost the input voltage and provide either single or multiple outputs.
25
[0057] More specifically for this, in an implementation, a power supply unit in connection to the IBTB [102] may receive the external input DC voltage of -48V. In another implementation, the external input DC voltage may be any voltage from a range of -40V to -57V. Further, in an implementation, the external input DC voltage of -48V may be converted concurrently into
30 28V output signal and 12V output signals, based on one or more industry standard bricks. In
another implementation, the one external input DC voltage from the range of -40V to -57V is down converted into different voltage levels as may be required to implement the features of the present disclosure. Also, the 28V and 12V output signals (or any such other output signals that may be generated by down converting the external input DC voltage) may be further
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broken down into a set of target voltage output signals based on a set of requirements of a set
of devices / a set of components connected to the IBTB [102]. Also, in an implementation, one
or more of the 28V output signal, the 12V output signal and the set of target voltage output
signals are generated using at least one of a power management integrated chipset (PMIC),
5 switching buck/boost regulator(s), one or more Linear and low-dropout (LDO) regulator
devices, and one or more DC-DC converters. Here, the PMIC refers to an integrated circuit chip that converts or controls the power supply and provides a suitable voltage or current for the normal operation of the load. Further, switching buck/boost regulator takes a DC input voltage and produces a DC output voltage that is opposite in polarity to the input. Further,
10 linear and low-dropout (LDO) regulators are a simple, inexpensive way to provide a regulated
output voltage that is powered from a higher voltage input in a variety of applications. Furthermore, the DC-DC converters are used to convert the voltage of a direct current (DC) source from one level to another, ensuring stable and efficient power delivery to various electronic devices and systems.
15
[0058] Further, referring to Figure. 4 which illustrates an exemplary block diagram of a power supply unit [400] connected to the IBTB [102] in accordance with exemplary embodiments of the present disclosure. In an implementation, the power supply unit [400] may be integrated at the IBTB [102]. In another implementation, the power supply unit [400] may be present outside
20 but operably coupled to the IBTB [102]. Particularly, Figure 4 depicts the down conversion of
the external input DC voltage at the power supply unit [400] connected to the IBTB [102]. As depicted in Figure 4, the external input DC voltage for instance -48V is received by the power supply unit [400] connected to the IBTB [102]. Thereafter, at the power supply unit [400] connected to the IBTB [102], -48V is passed through a common electromagnetic interference
25 (EMI) and electromagnetic compatibility (EMC) input choke filter [402]. The EMI/EMC input
choke filter facilitates concurrent down conversion of the external input DC voltage (that is once the -48V input DC voltage is passed through the EMI and EMC input choke filter [402], it is then down converted to a 28V output signal and a 12V output signal), based on one or more industry standard bricks. The concurrent down conversion of the external input DC
30 voltage via the common electromagnetic interference (EMI) and electromagnetic compatibility
(EMC) input choke filter [402] reduces the cost and space associated with the ODSC system [100], otherwise in absence of the common EMI and EMC choke filter [402] two such filters each for 28V and 12V may have to be used for this down conversion into two different voltages. In an implementation, the down converted 28V and/or 12 V DC supply is further passed to
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switching buck/boost regulator(s) and/or one or more linear and low-dropout (LDO) regulator
devices [404] for further generation of the set of target voltage output signals (i.e., the set of
lower /down converted voltage output signals). Also, in an implementation the down converted
voltage output signal(s) or the set of target voltage output signals may be provided to a radio
5 frequency front end power amplifier section [104d] based on a requirement such as signal
transmission, etc.
[0059] Also, as indicated in the Figure 1a, the IBTB [102] comprises at least a network processor [102a], wherein the network processor [102a] is connected to at least a backhaul and
10 the power supply unit. The backhaul, as used herein, may be at least one of a set of copper
links, a set of fiber links, and a set of wireless links that connects a core network of a telecommunication network or one or more backbone networks of the telecommunication network with a set of smaller subnetworks within the telecommunication network. The IBTB [102] may comprise complex sub-systems such as the network processor [102a] for processing
15 digital high-speed signals, switching power supplies, clock section and radio frequency (RF)
signal section. In an implementation, the IBTB [102] is designed on 18 or more layers of printed circuit board (PCB). More particularly, the IBTB [102] may be designed on the multi-layer printed circuit board (PCB) such that the multi-layer PCB may route a set of RF signals and a set of predefined signals running on high speed on adjacent layers and operate in micro class
20 for providing the solutions for coverage and capacity in heterogenous network along with the
macro cells. Further, the PCB design includes the unique design techniques to route RF signals and PCIe Gen 3.0 (Peripheral Component Interconnect Express Generation 3.0) signals running on high speed, such as 8 giga-transfers per second (8 GT/s), on adjacent layers. Further, the IBTB [102] comprises one or more baseband and transceiver modules [102b], one or more
25 control units [102c], one or more controller circuits [102d], and one or more clock and
synchronization circuit (CSC) [110]. A baseband processor chipset in the baseband and transceiver module [102b] may facilitate L2 layer processing and L3 layer processing. Further, the IBTB [102] comprises a field-programmable gate array (FPGA) chipset for L1 layer processing. Moreover, in an implementation, the one or more controller circuits [102d] operates
30 in line with at least one of a L1-PHY (Physical layer L1 / Lower PHY layer), Digital Up-
Conversion (DUC), Digital Down-Conversion (DDC), Crest Factor Reduction (CFR), Digital Pre-Distortion (DPD), Time division duplex (TDD) Controller. Further, the IBTB [102] comprises one or more temperature sensors for measuring a temperature of one or more
15

sections of the IBTB [102] and for enabling an automatic action in an event of a detection of
thermal failure. One or more transceivers in the baseband and transceiver module [102b] may
facilitate monitoring of a power amplifier output by measuring a received power on an
Analogue-to-Digital Converter (ADC) of the IBTB [102] during utilization of a feedback chain.
5 Also, the baseband and transceiver module [102b], may comprise one or more of a baseband
processor, a transmitter device, and a receiver device. The transceiver module of the baseband
and transceiver module [102b] may facilitate a digital interface for the analog RF signal chain
which may facilitate an easy integration to the ASIC/FPGA for the baseband processing.
Further, the baseband processor of the baseband and transceiver module [102b] may facilitate
10 processing of a user data, in a digital domain, between a transceiver device and an end
application.
[0060] Further, the clock and synchronization circuit (CSC) [110] may be connected to at least the baseband processor chipset and the one or more transceivers. Also, the CSC [110] may be
15 configured to synchronize the IBTB [102] with one or more units connected to the ODSC
system [100]. Further as depicted in Fig. 1c, in an implementation, the CSC [110] comprises at least one or more ultra-low noise clock generation phase-locked loops (PLLs) [110a], a programmable oscillator [110b], and a system synchronizer integrated circuit (system synchronizer IC) [110c]. The ultra-low noise clock generation phase-locked loops (PLL)
20 [110a] provides stable and low noise signals for high frequency clock, and serial data
communications. The programmable oscillator [110b] is an oscillator in which the resonator frequency is post-processed to a desired output frequency utilizing an integer-mode or fractional-phase-locked loop (PLL). The Programmable oscillator [110b] and the system synchronizer [110c] performs phase locking and locks to a common frequency with constant
25 phase differences. Pertinently, such clock generation PLLs may be helpful in high-speed serial
communication buses that provide high data rate communications. Further, as generally known in the art, the PLL-based frequency synthesizers using integer N and fractional N topologies provide stable, low noise signals for high frequency clock, serial data communications, and radar applications for frequencies up to tens of gigahertz. Further, the programmable oscillator
30 [110b] and the system synchronizer IC) [110c] facilitate phase locking, thereby locking to a
common frequency with a constant phase difference. Also, in an implementation, the clock and synchronization circuit is configured based on one of a Global Positioning System (GPS), a Precision Time Protocol (PTP), a holdover technique and one or more clock generators. Here,
16

a clock generator is an electronic oscillator that produces a clock signal for use in synchronizing
a circuit's operation; and the PTP is a protocol to synchronize clocks in a communication
network and is accurate up to less than a microsecond and is measured in nanoseconds. Further,
holdover is a technique used in telecommunications to maintain accurate timing and
5 synchronization of equipment in the event of a temporary loss of timing signals.
[0061] Furthermore, the network processor [102a] of the IBTB [102] comprises an integrated circuit capable of facilitating one or more functionalities of the telecommunication network such as a voice communication functionality, and a data communication functionality, etc., wherein such network processor [102a] may be any processor that may be obvious to a person skilled in the art to implement the technical features as disclosed in the present disclosure. In an implementation, the network processor [102a] works in conjunction with one or more units of the IBTB [102] and/or with one or more other units of the ODSC system [100] to provide a required network coverage and capacity at one or more hot zones/hot spot areas with high traffic and Quality of Standard (QoS) demands. The clock and synchronization circuit [110] is configured to synchronize the IBTB [102] with one or more units connected to the ODSC [100]. Therefore, complete system of the ODSC [100] is synchronized within the IBTB [102] and to its externally connected unit(s) using the clock and synchronization circuit [110] on board. Also, the clock and synchronization circuit [110] also takes care of holdover requirement as per telecom standards.
[0062] Also, the radio frequency front end board (RFFEB) [104] is blind mated to the IBTB [102]. The RFFEB [104] is configured to receive a set of control signals from the IBTB [102] along with a power supply through a connector RF Front-End Control Interface Board and
25 provide a fixed attenuation in a feedback path of the RFFEB [104]. The feedback path is a
reverse power determination circuitry, and in an implementation, a feedback path is shown in Fig. 3. Blind mating is a connection through one or more blind mating connectors, such as one or more mating bullets, to provide a robust connection between the blind mated components. The blind mating connectors have self-aligning features for sliding/ snapping plug(s) for
30 connection between the one or more blind mating connectors. In an implementation, the
RFFEB [104] may be blind mated to the cavity filter [106] and the multiple-input multiple-output (MIMO) antenna [108]. Furthermore, a blind mated connection between the IBTB [202] and an RFFEB [204] of the 4T4R 5G NR ODSC is also indicated in FIG. 2. Further, as shown
17

in Fig. 2, the 4T4R 5G NR ODSC [200] includes an IBTB [202] which further comprises at
least a network processor [202a] connected to a backhaul, a baseband and transceiver module
[202b], one or more control units [202c], and one or more controller circuits [202d]. For the
purpose of clarity, it is pertinent to mention that here the IBTB [202] is same as the IBTB [102],
5 the network processor [202a] is same as the network processor [102a], the baseband and
transceiver module [202b] is same as the baseband and transceiver module [102b], the control unit [102c] is same as the control unit [202c], and the controller circuit [102d] is same as the controller circuit [202d]. Further, the RFFEB [204] is blind mated to a cavity filter [208] and a multiple input multiple output antenna [210]. Here, the cavity filter [106] may be construed as
10 a type of resonant filter that may be used for allowing or rejecting signals in a desired range of
frequencies. Further, the MIMO antenna [108] may be construed as an antenna technology for wireless communications in which multiple antennas are used at the transmitting end as well as at the receiving end. Reiterating from above, the blind mating is a connection through one or more blind mating connectors, such as one or more mating bullets, to provide a robust
15 connection between the blind mated components such as: the IBTB [202] and the RFFEB
[204]; and the RFFEB [204], the cavity filter [106], and the MIMO antenna [108]. The blind mating of the IBTB [102] to the RFFEB [104] also enables removal of complexities involved in routing of cables for avoiding RF signal oscillations. Further, blind mating may also facilitate in reduced production costs, installation costs, and maintenance costs, shorter assembly time,
20 fewer errors during assembly, shorter downtime, eliminating requirement of specialized tools,
and fewer mismatched connections.
[0063] Additionally, in an implementation, the cavity filter [106] comprises a 4-port cavity filter for a 4T4R configuration providing a steeper roll-off outside an operating band, and the
25 MIMO antenna [108] comprises a set of 4-port cross-polarized patch antennas for the 4T4R
configuration, however the present disclosure is not limited thereto and any configuration of the cavity filter [106] and the MIMO antenna [108] may be considered depending on use case/requirement. Also, the cavity filter [106] in accordance with the implementation of features as disclosed in the present disclosure enables a reduced loss of signals and also
30 contributes to reduced overall power consumption. In an implementation, the configuration of
the cavity filter [106] may be based on a number of the MIMO antenna [108] used in the ODSC [100].
18

[0064] Furthermore, in an implementation, the RFFEB [104] comprises: (a) a RF time division
duplex (TDD) switch [104f]; (b) at least four transmit chains for signal transmission, wherein
each transmit chain from the four transmit chains carries matching Balun, pre-driver amplifier
and final RF power amplifier as final stage power amplifier (PA); (c) four receive chains for
5 signal reception, wherein one or more pairs of dual channels low noise amplifiers (LNAs) cater
to two receive chains from the four receive chains having band pass surface acoustic wave (SAW) filter and a matching network; (d) four observation chains which function as digital pre-distortion (DPD) feedback paths from one or more power amplifier modules (PAMs) to at least one of a field-programmable gate array (FPGA) and an application-specific integrated
10 circuit (ASIC) for linearization. Referring to FIG.2 that depicts the 4T4R 5G NR ODSC
including the RFFEB [204]. As shown in FIG. 2, that the RFFEB [204] includes similar units such as, but not limited to, four RF chains (such as RF chain 1 [204a], RF chain 2 [204b], RF chain 3 [204c] and RF chain 4 [204d]), and a unit [206] including a driver amplifier, a digital step attenuator, a PA, a LNA, a circulator and TDD switch. Also, in an implementation, each
15 PAM from the one or more PAMs is an off-the-shelf power efficient 50-ohm matched PAM
however, the present disclosure is not limited thereto. Further, in an implementation, each pair of dual channels LNA from the one or more pairs of dual channels LNAs has, but not limited to, a sub 1dB Noise Figure (NF) for minimizing RF trace losses on one or more top layers in the ODSC system [100] which improves the system noise figure, receiver sensitivity and cost.
20 Each pair of dual channels LNA caters to two receive chain having band pass SAW filter and
matching network. Further, in an implementation, the RFFEB [104] is configured to provide the fixed attenuation for optimizing a cost in the feedback path of the RF frontend board section of the ODSC.
25 [0065] Also, referring to the FIG. 3 that illustrates an exemplary block diagram of transmission
(Tx) and receiver (Rx) Chain pair of RF Front End Board/Module, in accordance with exemplary embodiments of the present disclosure. The RF front end board receives the control signals from IBTB along with the power supply through a connector RFFE Board that consists of 4 transmit chains for signal transmission, 4 receive chains for signal reception and 4
30 observation chains which function as DPD feedback paths from PAM modules to FPGA/ASIC
for linearization. Each transmit chain carries matching Balun (i.e., a balancing unit), a pre-driver amplifier and a Final RF power amplifier as final stage PA. Also, each observation chain carries directional coupler, fixed attenuation network using passive components and Band Pass
19

Filter. RF TDD switch is a switch used in the Rx Front End for protecting the receiver from
reverse transmit power from antenna, under port open and impedance mismatch. Circulator
and Cavity filter are used between each RF switch to antenna port. The RF Front End Board
(RFFEB) blind mates with Integrated Baseband and Transceiver Board (IBTB) thus removing
5 the complexity of cable routing to avoid RF signal oscillations. The RF mating bullets provides
robust connection between IBTB and RFFEB that the existing systems failed to provide. This ODSC system [100] design is validated to provide its target 25W output transmit power, but the disclosure is not limited thereto.
10 [0066] Therefore, an overall integrated system having NW processor and FPGA/ASIC for
Baseband Transceiver is provided where all these are integrated on 18 or more layers Integrated baseband and Transceiver board. Also, clock synchronization architecture using system synchronizer IC based on GPS/PTP/Holdover and clock generators is provided along with L1 layer development and bit stream generation in FPGA/ASIC, in blind mating and cable less
15 ODSC design. Further, cost optimization is achieved by eliminating the need for external PA
bias circuitry due to availability of on-chip biasing. This improvement is realized by utilizing an off-the-shelf power-efficient 50-ohm matched power amplifier module (PAM). Also, improvement in the System Noise Figure is provided resulting in RF Receiver sensitivity improvement and cost optimization by utilizing the off-the-shelf dual channel LNA having sub
20 1dB Noise Figure (NF). Furthermore, the layout design of the ODSC is also optimized to
minimize RF trace losses on the top layers, thereby further minimizing degradation in the overall system noise figure (NF). Additionally, cost optimization is achieved in the feedback path (reverse power determination circuitry) of RF frontend board section by implementing fixed attenuation using passive components instead of Digital Step Attenuator and control
25 circuitry. The external -48V input DC voltage which passes through a common EMI/EMC
input choke filter and then down converts it to first 28V and 12V concurrently, using industry standard bricks and then various lower voltages, further optimises the cost and performance of the ODSC.
30 [0067] As is evident from the above, the present disclosure provides a technically advanced
solution of enabling an outdoor small cell (ODSC) system to provide a cost and performance optimized ODSC such as a Sub-6GHz 5G new radio (NR) 4T4R Outdoor Small Cell (ODSC). The ODSC as disclosed in the present disclosure is technically advanced over the existing ODSCs as in this an integrated antenna solution is used which blind mates with RF Front End
20

board, thus, making it a cable less design and easy to deploy on street furniture and electric
light pole. Also, it meets all the RF performance requirements mentioned in the
telecommunication standards after integrating TDD based 5G NR ODSC with Crest Factor
Reduction (CFR) and Digital Pre-Distortion (DPD) modules in Digital Front End line-up and
5 is a cost-effective solution as compared to the available solutions.
[0068] While considerable emphasis has been placed herein on the disclosed implementations,
it will be appreciated that many implementations can be made and that many changes can be
made to the implementations without departing from the principles of the present disclosure.
10 These and other changes in the implementations of the present disclosure will be apparent to
those skilled in the art, whereby it is to be understood that the foregoing descriptive matter to be implemented is illustrative and non-limiting.
21

We Claim:
1. An outdoor small cell (ODSC) system [100], the ODSC system [100] comprising:
5 - a housing unit [101], wherein the housing unit [101] is configured to house at least:
o an integrated baseband and transceiver board (IBTB) [102], wherein the IBTB [102] is configured to:
receive an external input direct current (DC) voltage,
pass the external input DC voltage through a common electromagnetic
10 interference (EMI) and electromagnetic compatibility (EMC) input
choke filter [402], and
down convert the external input DC voltage to a plurality of signals
concurrently
o a radio frequency front end board (RFFEB) [104] blind mated to the IBTB
15 [102], wherein the RFFEB [104] is configured to:
receive a set of control signals from the IBTB [102] along with a power supply through a connector Radio Frequency (RF) Front-End Control Interface Board, and
provide a fixed attenuation in a feedback path of the RFFEB [104];
20 o a cavity filter [106]; and
o a multiple-input multiple-output (MIMO) antenna [108].
2. The ODSC system [100] as claimed in claim 1, wherein the IBTB [102] comprises:
- a network processor [102a] connected to at least a backhaul and a power supply
25 unit,
- a baseband processor chipset for L2 layer processing and L3 layer processing,
- a field-programmable gate array (FPGA) chipset for L1 layer processing,
- one or more temperature sensors for measuring a temperature of one or more sections of the IBTB [102] and for enabling an automatic action in an event of a
30 detection of thermal failure,
- one or more transceivers for monitoring a power amplifier output by measuring a
received power on an Analogue-to-Digital Converter (ADC) of the IBTB [102]
during utilization of a feedback chain, and
22

- a clock and synchronization circuit [110] connected to at least the baseband
processor chipset and the one or more transceivers, wherein the clock and
synchronization circuit [110] is configured to synchronize the IBTB [102] with one
or more units connected to the ODSC system [100], and wherein the clock and
5 synchronization circuit [110] comprises at least one or more ultra-low noise clock
generation phase-locked loops (PLLs) [110a], a programmable oscillator [110b], and a system synchronizer integrated circuit (system synchronizer IC) [110c].
3. The ODSC system [100] as claimed in claim 2, wherein the clock and synchronization
10 circuit [110] is configured based on one of a Global Positioning System (GPS), a
Precision Time Protocol (PTP), a holdover technique and one or more clock generators.
4. The ODSC system [100] as claimed in claim 1, wherein the external input DC voltage
is received by the IBTB [102] via a power supply unit [400], and wherein the external
15 input DC voltage is in a range of -40V to -57V.
5. The ODSC system [100] as claimed in claim 1, wherein the IBTB [102] is designed on
eighteen or more layers of a printed circuit board (PCB) and wherein:
the PCB is based on a design protocol to route one or more signals between an
20 eighteen or more layers.
6. The ODSC system [100] as claimed in claim 4, wherein the IBTB [102] is configured
to down convert a -48V input DC voltage to:
a 28V output signal and a 12V output signal concurrently, based on one or more
25 industry standard bricks, and
further convert the 28V output signal and the 12V output signal to a set of target voltage output signals based on a set of requirements of a set of devices connected to the IBTB [102], wherein the 28V output signal, the 12V output signal and the set of target voltage output signals are generated using at least
30 one of a power management integrated chipset (PMIC), one or more DC-DC
converters and one or more Linear and low-dropout (LDO) regulator devices.
7. The ODSC system [100] as claimed in claim 1, wherein the RFFEB [104] comprises:
a RF time division duplex (TDD) switch [104f],
23

at least four transmit chains for signal transmission, wherein each transmit chain from the four transmit chains carries matching Balun, pre-driver amplifier and final RF power amplifier as final stage power amplifier (PA),
four receive chains for signal reception, wherein one or more pairs of dual
5 channels low noise amplifiers (LNAs) cater to two receive chains from the four
receive chains having band pass surface acoustic wave (SAW) filter and a matching network, and
four observation chains which function as digital pre-distortion (DPD) feedback
paths from one or more power amplifier modules (PAMs) to at least one of a
10 field-programmable gate array (FPGA) and an application-specific integrated
circuit (ASIC) for linearization.
8. The ODSC system [100] as claimed in claim 7, wherein each PAM from the one or
more PAMs is an off-the-shelf power efficient 50-ohm matched PAM. 15
9. The ODSC system [100] as claimed in claim 7, wherein each pair of dual channels LNA
from the one or more pairs of dual channels LNAs has a sub 1dB Noise Figure (NF) for minimizing RF trace losses on one or more top layers in the ODSC system [100].
20 10. The ODSC system [100] as claimed in claim 1, wherein the RFFEB [104] is configured
to provide the fixed attenuation for optimizing a cost in the feedback path of the RFFEB section of the ODSC system [100].
11. The ODSC system [100] as claimed in claim 1, wherein the cavity filter [106] comprises
25 a four-port cavity filter [106] for a four Transmit four Receive (4T4R) configuration
providing a steeper roll-off outside an operating band.
12. The ODSC system [100] as claimed in claim 11, wherein the MIMO antenna [108]
comprises four-port cross-polarized patch antennas for the 4T4R configuration.
30
13. The ODSC system [100] as claimed in claim 1, wherein the IBTB [102] is configured
to down convert the external input DC voltage to the plurality of signals concurrently, based on one or more industry standard bricks.