FORM 2
THE PATENTS ACT, 1970 (39 OF 1970) & THE PATENT RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)
“METHOD AND SYSTEM FOR BOUNDARY SCAN TESTING OF JOINT TEST ACTION GROUP (JTAG) COMPLIANT
DEVICES”
We, Jio Platforms Limited, an Indian National, of Office - 101, Saffron, Nr. Centre Point, Panchwati 5 Rasta, Ambawadi, Ahmedabad - 380006, Gujarat, India.
The following specification particularly describes the invention and the manner in which it is to be performed.

METHOD AND SYSTEM FOR BOUNDARY SCAN TESTING OF JOINT TEST ACTION GROUP (JTAG) COMPLIANT DEVICES
FIELD OF INVENTION
[0001] Embodiments of the present disclosure generally relate to testing of electronic components. More particularly, embodiments of the present disclosure relate to a method and system for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output Radio Unit (MRU).
BACKGROUND OF THE DISCLOSURE
[0002] The following description of the related art is intended to provide background information pertaining to the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, it should be appreciated that this section is used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of the prior art.
[0003] Wireless communication systems and other systems also employ various electronic components such as processor, integrated circuits, etc. A typical radio unit may comprise a printed circuit board (PCB) and a mix of integrated circuits (ICs) of different packages and footprints. Assembly issues in PCB manufacturing, such as open circuits, shorts, and incorrect component placements, can lead to product failures and costly rework. Therefore, testing and debugging of electronic components is essential to ensure the quality, reliability, and safety of these electronic devices. Existing solutions related to testing the electronic components require physical access to each test point on the board, which is a tedious, time-consuming, and labour-intensive process. This not only increases the cost of

production but also delays the manufacturing process significantly. Due to the necessity of physical access for each test point, these traditional methods are not able to provide comprehensive coverage of all components and interconnections on the board, especially when it comes to intricate and complex ICs (Integrated Circuits). This may lead to some faults going undetected, potentially causing product failures later on. When a product failure does occur, especially after deployment, identifying the source of the problem can be extremely time-consuming due to the lack of comprehensive pre-deployment testing. This lengthy debugging process can further increase costs in terms of labour and downtime. Further, existing methods can lead to high Mean Time to Repair (MTTR) due to inefficient testing and debugging mechanisms.
[0004] JTAG (Joint Test Action Group) refers to a standard for testing and debugging electronic devices, particularly integrated circuits and printed circuit boards. It is commonly used in the development and production of electronic devices to verify and test hardware components. It enables features like boundary scan testing, which can test the interconnections between integrated circuits on a PCB without the need for functional test access points (i.e., physical or logical points on a device or system where test signals can be applied, and responses are obtained to observe during functional testing). That is, the JTAG testing enables to determine the assembly defect for any active component in PCB without waiting for their functional testing. For the testing and debugging of the components employed in the wireless communication systems and to ensure the performance and reliability requirements, JTAG can be used during development and manufacturing. Boundary scan is a test technique that involves devices designed with shift registers placed between each device pin and an internal logic. Each shift register is called a boundary scan cell. These boundary scan cells allow to control and observe what happens at each input and output pin. In order to run boundary scan testing it is necessary to have some information about the implementation of JTAG on the enabled devices on a board. This information comes from the BSDL (Boundary Scan Description Language) files for these devices. BSDL files are text

files that describe the boundary scan architecture and behaviour of a digital integrated circuit (IC) or component. Thus, a JTAG / boundary scan test, unlike functional test, provides high precision fault information to help with rapid repair. Furthermore, JTAG testing also provides the capability to view both the physical location of a fault on the layout of the board and the logical design of the area of the circuit in which the fault exists on the schematic.
[0005] As discussed above, the traditional testing methods require physical access to test points, and the detection and diagnosis of these issues is time-consuming and labour-intensive. Moreover, the existing solutions also failed to perform JTAG testing on the intricate and complex ICs (Integrated Circuits) in an efficient and effective manner. The JTAG testing offered by the existing solutions is not able to provide comprehensive coverage of JTAG-compliant devices in a massive multiple input and multiple output radio unit (MRU). This not only increases the operational expenditure but also negatively impacts the overall maintainability of the product. Furthermore, with the traditional testing methods, each unit requires a significant amount of time to be tested, which reduces the overall rate of production, thereby impacting the manufacturing throughput and efficiency.
[0006] Thus, there exists an imperative need in the art to provide a solution for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output radio unit (MRU), which the present disclosure aims to address.
SUMMARY OF THE DISCLOSURE
[0007] This section is provided to introduce certain aspects of the present disclosure in a simplified form that are further described below in the detailed description. This summary is not intended to identify the key features or the scope of the claimed subject matter.

[0008] An aspect of the present disclosure may relate to a method for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output Radio Unit (MRU). The method comprises receiving, by a receiving unit, a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices. Further, the method comprises determining, by a determining unit, a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester. Further, the method comprises establishing, by a processing unit, a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins. Further, the method comprises categorizing, by the processing unit, each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, or a logic device. Further, the method comprises generating, by a generating unit, at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files. Further, the method comprises generating, by the generating unit, a set of results after completion of execution of the generated at least one test code.
[0009] In an exemplary aspect of the present disclosure, the method further comprises switching between a single JTAG chain configuration and the daisy chain configuration using a jumper that controls an enable pin of each of one or more level shifters, wherein in the single JTAG chain configuration, one or more pins of each Application-Specific Integrated Circuit (ASIC) of the JTAG compliant devices are connected to one or more individual JTAG connectors directly, and in the daisy chain configuration, a Test Data Output (TDO) pin of the ASIC is connected to a Test Data Input (TDI) pin of a subsequent ASIC of the daisy chain configuration.
[0010] In an exemplary aspect of the present disclosure, the method further comprises connecting a plurality of peripheral devices to the ASIC via one or more interfaces, wherein the plurality of peripheral devices comprises, a memory device, an Ethernet PHY transceiver, a re-timer, a universal asynchronous receiver /

transmitter (UART) connector, an Inter-Integrated Circuit (I2C) switch, a multiplexer, an I2C serial peripheral interface (SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock synchronizer, an analog-to-digital converter (ADC), a digital to analog converter (DAC), and a digital step attenuator (DSA).
[0011] In an exemplary aspect of the present disclosure, the one or more interfaces for connecting peripheral devices comprise at least one from among an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed interconnects, or any combination thereof.
[0012] In an exemplary aspect of the present disclosure, the method further comprises performing one or more additional tests related to reading/writing registers, measuring voltages or currents, checking temperature sensors, or verifying manufacture IDs.
[0013] In an exemplary aspect of the present disclosure, the test codes are generated based on one of using a library of test files, and a template stored in a database.
[0014] Another aspect of the present disclosure may relate to a system for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output Radio Unit (MRU). The system comprises a receiving unit configured to receive a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices. Further, the system comprises a determining unit connected to at least the receiving unit, the determining unit is configured to determine a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester. Further, the system comprises a processing unit connected to at least the determining unit, the processing unit is configured to establish a daisy chain configuration based on an information

associated with the set of BSDL files and the determined set of non-logical pins.
Further, the processing unit connected to at least the determining unit, the
processing unit is configured to categorize each of the set of JTAG-compliant
devices in to at least one of a passive device, a test device, and a logic device.
5 Further, the system comprises a generating unit connected to at least the processing
unit, the generating unit is configured to generate at least one test code based on the
categorized set of JTAG-compliant devices and the information associated with the
set of BSDL files. Further, the generating unit connected to at least the processing
unit, the generating unit is configured to generate a set of results after completion
10 of execution of the generated at least one test code.
[0015] Yet another aspect of the present disclosure may relate to a non-transitory computer readable storage medium storing instructions for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and
15 multiple output radio unit (MRU), the instructions include executable code which,
when executed by one or more units of a system, causes: a receiving unit of the system to receive a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices. Further, the instructions include executable code which, when executed causes a determining unit of the system to
20 determine a set of non-logical pins for each of the set of JTAG-compliant devices
within a JTAG tester. Further, the instructions include executable code which, when executed causes a processing unit of the system to establish a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins. Further, the instructions include executable code
25 which, when executed causes the processing unit of the system further to categorize
each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device. Further, the instructions include executable code which, when executed causes a generating unit of the system to: generate at least one test code based on the categorized set of JTAG-compliant devices and the
30 information associated with the set of BSDL files; and to generate a set of results
after completion of execution of the generated at least one test code.
7

[0016] Yet another aspect of the present disclosure may relate to a user equipment
in communication with a system for boundary scan testing of joint test action group
(JTAG)-compliant devices in a massive MIMO Radio Unit (MRU). The user
5 equipment comprises at least a user interface configured to receive a set of results
related to the boundary scan testing of the JTAG-compliant devices. The set of results is generated by the system based on: (a) receiving, by a receiving unit via JTAG tester, a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices; (b) determining, by a
10 determining unit, a set of non-logical pins for each of the set of JTAG-compliant
devices within a JTAG tester; (c) establishing, by a processing unit, a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins; (d) categorizing, by the processing unit, each of the set of JTAG-compliant devices in to at least one of a passive device, a test
15 device, and a logic device; (e) generating, by a generating unit, at least one test code
based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and (f) generating, by the generating unit, the set of results after completion of execution of the generated at least one test code.
20 OBJECTS OF THE DISCLOSURE
[0017] Some of the objects of the present disclosure, which at least one embodiment disclosed herein satisfies are listed herein below.
25 [0018] It is an object of the present disclosure to provide a method and system for
boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output radio unit (MRU).
[0019] It is another object of the present disclosure to provide a solution that
30 performs comprehensive testing in less time compared to traditional testing
methods, improving manufacturing efficiency and throughput.
8

[0020] It is yet another object of the present disclosure to provide a solution that ensures testing of the entire printed circuit board with maximum coverage in one go. 5
[0021] It is yet another object of the present disclosure to provide solution that reduces time spent on debugging, especially in the case of field-deployed failure units.
10 [0022] It is yet another object of the present disclosure to provide a solution that
enhances maintainability of the product and thereby lower operational expenditure related to product failures of field-deployed units.
[0023] It is yet another object of the present disclosure to provide a solution that
15 helps to pinpoint the exact location of issues on field failure units, leading to a
reduction in debugging time and thus a lower failure turnaround time.
[0024] It is yet another object of the present disclosure to provide a solution that
uses relatively low-cost components like buffers/level shifters, switches and
20 jumpers to switch from single chain to daisy chain JTAG mode, offering a cost-
effective solution.
DESCRIPTION OF THE DRAWINGS
25 [0025] The accompanying drawings, which are incorporated herein, and constitute
a part of this disclosure, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present
30 disclosure. Also, the embodiments shown in the figures are not to be construed as
limiting the disclosure, but the possible variants of the method and system
9

according to the disclosure are illustrated herein to highlight the advantages of the disclosure. It will be appreciated by those skilled in the art that disclosure of such drawings includes disclosure of electrical components or circuitry commonly used to implement such components. 5
[0026] Fig. 1 shows a basic architecture of hardware system design for joint test action group (JTAG) boundary scan test.
[0027] Fig. 2 shows various basic peripheral devices and interfaces connected to an
10 application specific integrated circuit (ASIC) in a joint test action group (JTAG)
system for boundary scan test.
[0028] Fig. 3 illustrates an exemplary block diagram of a system for boundary scan
testing of joint test action group (JTAG)-compliant devices in a massive multiple
15 input and multiple output radio unit (MRU), in accordance with exemplary
implementations of the present disclosure.
[0029] Fig. 4 illustrates a method flow diagram for boundary scan testing of joint
test action group (JTAG)-compliant devices in a massive multiple input and
20 multiple output radio unit (MRU), in accordance with exemplary implementations
of the present disclosure.
[0030] Fig. 5 illustrates an exemplary method flow diagram for development of
boundary scan testing of a 5G Integrated Massive MIMO Radio Unit (MRU)
25 device, in accordance with exemplary embodiments of the present disclosure.
[0031] Fig. 6A illustrates a first part of an exemplary scenario flow diagram for boundary scan test of 5G new radio (NR) integrated MRU, in accordance with exemplary embodiments of the present disclosure. 30
10

[0032] Fig. 6B illustrates a second part of an exemplary scenario flow diagram for boundary scan test of 5G NR IMRU, in accordance with exemplary embodiments of the present disclosure.
5 [0033] Fig. 7 shows exemplary JTAG Boundary Scan Test results, in accordance
with an embodiment of the present disclosure.
[0034] The foregoing shall be more apparent from the following more detailed description of the disclosure. 10
DETAILED DESCRIPTION
[0035] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of
15 embodiments of the present disclosure. It will be apparent, however, that
embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter may each be used independently of one another or with any combination of other features. An individual feature may not address any of the problems discussed above or might address only some of the
20 problems discussed above.
[0036] The ensuing description provides exemplary embodiments only, and is not
intended to limit the scope, applicability, or configuration of the disclosure. Rather,
the ensuing description of the exemplary embodiments will provide those skilled in
25 the art with an enabling description for implementing an exemplary embodiment.
It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as set forth.
30 [0037] Specific details are given in the following description to provide a thorough
understanding of the embodiments. However, it will be understood by one of
11

ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. 5
[0038] Also, it is noted that individual embodiments may be described as a process
which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure
diagram, or a block diagram. Although a flowchart may describe the operations as
a sequential process, many of the operations may be performed in parallel or
10 concurrently. In addition, the order of the operations may be re-arranged. A process
is terminated when its operations are completed but could have additional steps not included in a figure.
[0039] The word “exemplary” and/or “demonstrative” is used herein to mean
15 serving as an example, instance, or illustration. For the avoidance of doubt, the
subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques
20 known to those of ordinary skill in the art. Furthermore, to the extent that the terms
“includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive—in a manner similar to the term “comprising” as an open transition word—without precluding any additional or other elements.
25
[0040] As used herein, a “processing unit” or “processor” or “operating processor” includes one or more processors, wherein processor refers to any logic circuitry for processing instructions. A processor may be a general-purpose processor, a special purpose processor, a conventional processor, a digital signal processor, a plurality
30 of microprocessors, one or more microprocessors in association with a (Digital
Signal Processing) DSP core, a controller, a microcontroller, Application Specific
12

Integrated Circuits, Field Programmable Gate Array circuits, any other type of
integrated circuits, etc. The processor may perform signal coding data processing,
input/output processing, and/or any other functionality that enables the working of
the system according to the present disclosure. More specifically, the processor or
5 processing unit is a hardware processor.
[0041] As used herein, “a user equipment”, “a user device”, “a smart-user-device”, “a smart-device”, “an electronic device”, “a mobile device”, “a handheld device”, “a wireless communication device”, “a mobile communication device”, “a
10 communication device” may be any electrical, electronic and/or computing device
or equipment, capable of implementing the features of the present disclosure. The user equipment/device may include, but is not limited to, a mobile phone, smart phone, laptop, a general-purpose computer, desktop, personal digital assistant, tablet computer, wearable device or any other computing device which is capable
15 of implementing at least some of the features of the present disclosure. Also, the
user device may contain at least one input means configured to receive an input from unit(s) which are required to implement one or more features of the present disclosure.
20 [0042] As used herein, “storage unit” or “memory unit” refers to a machine or
computer-readable medium including any mechanism for storing information in a form readable by a computer or similar machine. For example, a computer-readable medium includes read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices or other
25 types of machine-accessible storage media. The storage unit stores at least the data
that may be required by one or more units of the system to perform their respective functions.
[0043] As used herein “interface” or “user interface refers to a shared boundary
30 across which two or more separate components of a system exchange information
or data. The interface may also be referred to a set of rules or protocols that define
13

communication or interaction of one or more modules or one or more units with each other, which also includes the methods, functions, or procedures that may be called.
5 [0044] All modules, units, components used herein, unless explicitly excluded
herein, may be software modules or hardware processors, the processors being a
general-purpose processor, a special purpose processor, a conventional processor,
a digital signal processor (DSP), a plurality of microprocessors, one or more
microprocessors in association with a DSP core, a controller, a microcontroller,
10 Application Specific Integrated Circuits (ASIC), Field Programmable Gate Array
circuits (FPGA), any other type of integrated circuits, etc.
[0045] As used herein the transceiver unit include at least one receiver and at least
one transmitter configured respectively for receiving and transmitting data, signals,
15 information or a combination thereof between units/components within the system
and/or connected with the system.
[0046] Further, in accordance with the present disclosure, it is to be acknowledged that the functionality described for the various components/units can be
20 implemented interchangeably. While specific embodiments may disclose a
particular functionality of these units for clarity, it is recognized that various configurations and combinations thereof are within the scope of the disclosure. The functionality of specific units as disclosed in the disclosure should not be construed as limiting the scope of the present disclosure. Consequently, alternative
25 arrangements and substitutions of units, provided they achieve the intended
functionality described herein, are considered to be encompassed within the scope of the present disclosure.
[0047] As discussed in the background section, the current known solutions have
30 several shortcomings. The existing solutions require physical access to each test
point on the board, which is a tedious, time-consuming, and labour-intensive
14

process. This not only increases the cost of production but also delays the
manufacturing process significantly. Due to the necessity of physical access for
each test point, these traditional methods are not able to provide comprehensive
coverage of all components and interconnections on the board, especially when it
5 comes to intricate and complex ICs (Integrated Circuits). This may lead to some
faults going undetected, potentially causing product failures later on. When a product failure does occur, especially after deployment, identifying the source of the problem can be extremely time-consuming due to the lack of comprehensive pre-deployment testing. This lengthy debugging process can further increase costs
10 in terms of labour and downtime. Further, existing methods can lead to high Mean
Time to Repair (MTTR) due to inefficient testing and debugging mechanisms. This not only increases the operational expenditure but also negatively impacts the overall maintainability of the product. Furthermore, with the traditional testing methods, each unit requires a significant amount of time to be tested, which reduces
15 the overall rate of production, thereby impacting the manufacturing throughput and
efficiency. The present disclosure aims to overcome the above-mentioned and other existing problems in this field of technology by providing method and system of boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output (MIMO) Radio Unit (MRU). The
20 present disclosure addresses these problems by using a more efficient,
comprehensive, and less labour-intensive testing process, significantly improving the testing coverage, reducing the time required for testing, and enhancing the maintainability of field-deployed units. The system design uses level-shifters/buffers, transistor switches and jumpers to control single chain to daisy
25 chaining mode for JTAG boundary scan test. The unique hardware design with
inter-integrated circuit (I2C) switch(es)/ multiplexer(s) (MUX(es)), I2C serial peripheral interface (SPI) bridges and input output (IO) expanders helps in testing the entire board with maximum coverage in one go. In operation, a set of Boundary Scan Description Language (BSDL) files associated with one or more joint test
30 action group (JTAG) compliant devices is received. Then a set of non-logical pins
for each of the one or more JTAG compliant devices is determined. Further, a JTAG
15

daisy chain connecting each of the one or more JTAG compliant devices is
generated based on the determined set of non-logical pins. Further, it is determined
if the JTAG daisy connection is complete. Then each of the one or more JTAG
compliant devices is segregated in at least one of passive devices, test devices and
5 logic devices. Further, a set of test codes for each of the segregated one or more
JTAG compliant devices is generated. Further, a set of additional I2C and serial peripheral interface (SPI) circuit codes is generated to enable generating control signal to access Inter-Integrated Circuit (I2C) devices and SPI slave devices. Further, it is determined that if the SPI slave acknowledges I2C address or select
10 the SPI slave and readback. Further, one or more other tests are performed, which
include at least read/write registers and perform mathematical calculation based on device function such as (i) measuring current and voltage using sensors, (ii) measuring temperature of different temperature sensors, (iii) manufacturing identifiers (IDs), die identifiers (die IDs), or physical identifiers (PHY IDs) as per
15 availability; and generating a report based on the one or more other tests. As used
herein an “manufacturing ID” or a “die IDs” or a “PHY ID” is a unique ID assigned to a particular type of device. That is each type of devices is associated with a corresponding identifier referred as the “manufacturing ID” or the “die ID” or the “PHY ID”. In an implementation said corresponding identifier comprises a unique
20 alpha numeric value.
[0048] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.
25 [0049] FIG. 1 shows a basic architecture of hardware system design for joint test
action group (JTAG) boundary scan test. As shown, the JTAG compliant integrated circuit (IC) or the application-specific IC (ASIC) may have several specific pins, such as a TDI (Test Data Input) pin, a TDO (Test Data Output) pin, a TMS (Test Mode Select) pin, a TCK (Test Clock) pin and an optional TRST (Test Reset) pin
30 (not shown). These pins form the fundamental components of the JTAG
architecture, allowing test data to be serially shifted into and out of the IC to perform
16

the test and control operations. When these pins of the ASIC are connected to their
corresponding individual JTAG connector directly, a single JTAG chain is formed.
This setup is useful for simpler testing scenarios where only one device is tested at
a time. However, the system also supports a daisy chain configuration for more
5 complex, interconnected testing scenarios. For example, as shown in FIG. 1, the
daisy chain is enabled when the TDO pin of a first ASIC (ASIC-1) is connected to the TDI pin of a second ASIC (ASIC-2), the TDO pin of the second ASIC (ASIC-2) is connected to the TDI pin of a third ASIC (ASIC-3), and the TDO pin of the third ASIC (ASIC-3) is connected to the TDO pin assigned to the first JTAG
10 connector. The system may also use transistors, level shifters and jumpers such that
a switching action can be performed for switching from single mode to daisy chain mode with a single change in the placement of the jumper. The jumper controls the enable pin of the level shifters that either directs the TDO pin signal directly from the ASIC to its own individual direct the JTAG connector or directs the TDO pin
15 signal to the TDI pin of next ASIC. Depending on the state of the jumper, the TDO
pin signal from the ASIC is either directed to its own JTAG connector (single mode) or to the TDI pin of the next ASIC in the chain (daisy chain mode).
[0050] FIG. 2 shows various basic peripheral devices and interfaces connected to
20 an application specific integrated circuit (ASIC) in a joint test action group (JTAG)
system for boundary scan test. As shown in Fig. 2, there may be different periphery
devices like memory devices, Ethernet PHY transceivers, re-timers, universal
asynchronous receiver / transmitter (UART) connectors, Inter-Integrated Circuit
(I2C) switches/multiplexors (MUXs), I2C serial peripheral interface (SPI) bridges,
25 general-purpose input/output (GPIO) expanders, temperature sensors, current
sensors, real time clocks, micro controllers, oscillators, clock synchronizers, analog
to digital converters (ADCs), digital to analog converters (DACs), digital step
attenuators (DSAs) etc. that are connected to each of the ASICs. They are connected
through various interfaces like an Inter-Integrated Circuit (I2C), a serial peripheral
30 interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced
gigabit media independent interface (RGMII), and other high-speed interconnects.
17

[0051] Referring to FIG. 3, an exemplary block diagram of a system [300] for
boundary scan testing of joint test action group (JTAG)-compliant devices in a
massive multiple input and multiple output (MIMO) Radio Unit (MRU), is shown,
5 in accordance with the exemplary implementations of the present disclosure. The
system [300] comprises at least one receiving unit [302], at least one determining unit [304], at least one processing unit [306], and at least one generating unit [308]. Also, all of the components/ units of the system [300] are assumed to be connected to each other unless otherwise indicated below. Also, in Fig. 3 only a few units are
10 shown, however, the system [300] may comprise multiple such units or the system
[300] may comprise any such numbers of said units, as required to implement the features of the present disclosure. Further, in an implementation, the system [300] may be connected to or in communication with a user device (may also referred herein as a user equipment or UE) to implement the features of the present
15 disclosure.
[0052] The system [300] is configured for boundary scan testing of the joint test
action group (JTAG)-compliant devices in a massive multiple input and multiple
output (MIMO) Radio Unit (MRU), with the help of the interconnection between
20 the components/units of the system [300].
[0053] First, a JTAG tester may be set up for operation. This may involve powering up the JTAG tester and connecting the system under test (SUT), i.e., the JTAG-compliant devices to the JTAG tester. The tester may be loaded with the appropriate
25 software and set in a ready state for performing the test. The receiving unit [302]
may receive a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices. The BSDL files are integral to the JTAG testing process. They are used to define how the JTAG is implemented in a specific device. The BSDL files corresponding to the JTAG-compliant devices
30 are loaded into the tester. These files contain information about the device’s
identity, the device's boundary-scan cells, and their order. Further, in an exemplary
18

implementation, power, ground termination nets (i.e., the points within a circuit or
system where the ground connections are terminated) associated with the devices
may be categorized after receiving the BSDL files. After receiving the BSDL files
for the JTAG-compliant devices, the power nets and ground nets are identified, as
5 these are not going to be tested.
[0054] Further, the determining unit [304], connected to at least the receiving unit [302], may determine a set of non-logical pins for each of the set of JTAG-compliant devices within the JTAG tester. Here, the determination unit [304]
10 determines the non-logical pins for the each JTAG compliant device (i.e., the TDI
(Test Data In) pin, TDO (Test Data Out) pin, TCK (Test Clock) pin, and TMS (Test Mode Select) pin). These pins may not be part of the each JTAG-compliant device’s core functionality, but they play an essential role in the boundary scan test, enabling the tester to exercise control over the device’s input and output behaviour.
15
[0055] Further, the processing unit [306], connected to at least the determining unit [304], may establish a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins. In a JTAG system or the system under test (SUT) comprising the set of JTAG-compliant
20 devices, multiple JTAG-compliant devices may often be connected in the daisy
chain configuration, wherein the TDO (Test Data Output) pin of one device is connected to the TDI (Test Data Input) pin of the next device. This setup allows for the propagation of the test data from one device to the next in the chain. The tester establishes this daisy chain based on the information gathered from the BSDL files
25 and the known configuration of the SUT. In an implementation, the processing unit
[306] may switch between a single JTAG chain configuration and the daisy chain configuration using a jumper that controls an enable pin of each of one or more level shifters, wherein in the single JTAG chain configuration, one or more pins of each Application-Specific Integrated Circuit (ASIC) of the JTAG compliant
30 devices are connected to one or more individual JTAG connectors directly, and in
the daisy chain configuration, a Test Data Output (TDO) pin of the ASIC is
19

connected to a Test Data Input (TDI) pin of a subsequent ASIC of the daisy chain
configuration. Further, in an implementation, the processing unit [306] may connect
a plurality of peripheral devices to the ASIC via one or more interfaces, wherein
the plurality of peripheral devices comprises a memory device, an Ethernet PHY
5 transceiver, a re-timer, a universal asynchronous receiver / transmitter (UART)
connector, an inter-integrated circuit (I2C) switch, a multiplexer, I2C serial peripheral interface (SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock synchronizer, an analog-to digital converter (ADC), a digital to
10 analog converter (DAC), and a digital step attenuator (DSA). Also, in an
implementation, the one or more interfaces for connecting peripheral devices comprise at least one from among an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed
15 interconnects, or any combination thereof.
[0056] Further, the processing unit [306] may categorize each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device. The processing unit [306] checks whether the daisy chain has been correctly
20 established. This may be done by running a test that checks if identity codes of all
devices are correctly detected. If the identity codes’ values match their corresponding expected values, the processing unit [306] may infer that the daisy chain has been correctly set up. The processing unit [306] categorizes each device into one of the following types: the passive device (for e.g., devices such as, but not
25 limited to, resistors, capacitors, inductors), the test device (for e.g., devices such as,
but not limited to, integrated circuits having boundary scan file to support JTAG test), and the logic device (for e.g., logical gates such as, but not limited to, AND gate, OR gate, NOT gate, NAND gate, and buffers, etc.). This classification informs how the tester will interact with each device and what tests it may perform. For
30 example, tests related to memories (EEPROM (electrically erasable programmable
read-only memory) tests, SD (secure digital) card tests, etc.), tests related to sensors
20

(temperature sensor test, current sensor test, etc.), etc. as also shown in Fig. 7 which shows exemplary JTAG Boundary Scan Test results.
[0057] Further, the generating unit [308], connected to at least the processing unit
5 [306], may generate at least one test code based on the categorized set of JTAG-
compliant devices and the information associated with the set of BSDL files. Based on the device type and the information in the BSDL file, the tester generates appropriate test codes. These are a sequence of inputs that the tester will apply to each device to carry out the boundary scan test. If a new device is encountered, the
10 tester may generate a new test code based on a template or library of test files, that
is, the test codes may be generated based on at least one of using a library of test files, and a template stored in a database. Here, a template refers to an existing code in the library of test files using which a component can be tested, or in case a new component is encountered, then a modification may be made to the existing test
15 code to generate the new test code for the new component.
[0058] Besides the JTAG boundary scan test, the tester might also interact with the
Inter-Integrated Circuit (I2C) and the serial peripheral interface (SPI) devices on
the SUT. For this, it may generate additional I2C and SPI circuit codes to enable
20 generating control signals to access these devices. The tester checks whether the
I2C slave correctly acknowledges the I2C address. This could involve selecting the SPI slave, sending a command or data, and waiting for an acknowledgment signal. The acknowledgment is then read back and verified.
25 [0059] Further, the generating unit [308] may generate a set of results after
completion of execution of the generated at least one test code. In an implementation, the test code may be implemented within a simulation environment. In an implementation, the processing unit [306] may perform one or more additional tests related to reading/writing registers, measuring voltages or
30 currents, checking temperature sensors, or verifying manufacture IDs. These tests
may be specific to the device under test and its functionality. After all tests have
21

been completed, the generating unit [308] may compile the results and generate a comprehensive report. This report may provide details related to any issues found during the testing process and provide crucial information for diagnosing and fixing those issues. 5
[0060] Referring to FIG. 4, an exemplary flow diagram of method [400] for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output (MIMO) Radio Unit (MRU), in accordance with exemplary implementations of the present disclosure is shown. In
10 an implementation the method [400] is performed by the system [300]. Further, in
an implementation, the system [300] may be present in a server device to implement the features of the present disclosure. Also, as shown in Figure 4, the method [400] starts at step [402]. Further, FIG. 5 illustrates an exemplary method flow diagram for development of boundary scan testing of a 5G Integrated Massive MIMO Radio
15 Unit (MRU) device, in accordance with exemplary embodiments of the present
disclosure. For the purpose of clear explanation, some features of FIG. 4 and FIG. 5 may be used in conjunction with each other.
[0061] First, a testing system (JTAG tester) may be set up for operation. This may
20 involve powering up the JTAG tester and connecting the system under test (SUT),
i.e., the JTAG-compliant devices to the JTAG tester. The tester may be loaded with
the appropriate software and set in a ready state for performing the test. At step 402,
the method of the present disclosure comprises receiving, by a receiving unit [302],
a set of boundary scan description language (BSDL) files corresponding to a set of
25 JTAG-compliant devices (as also shown in block 502 of Fig. 5). The BSDL files
are integral to the JTAG testing process. They are used to define how the JTAG is
implemented in a specific device. The BSDL files corresponding to the JTAG-
compliant devices are loaded into the tester. These files contain information about
the device’s identity, the device's boundary-scan cells, and their order. In an
30 exemplary implementation, power, ground termination nets (i.e., the points within
a circuit or system where the ground connections are terminated) associated with
22

the devices may be categorized after receiving the BSDL files (as also shown in block 504 of Fig. 5). After receiving the BSDL files for the JTAG-compliant devices, the power nets and ground nets are identified, as these are not going to be tested. 5
[0062] Further, at step 404, the method of the present disclosure comprises
determining, by a determining unit [304], a set of non-logical pins for each of the
set of JTAG-compliant devices within a JTAG tester. Here, the determination unit
[304] determines the non-logical pins for the each JTAG compliant device (i.e., the
10 TDI (Test Data In) pin, TDO (Test Data Out) pin, TCK (Test Clock) pin, and TMS
(Test Mode Select) pin). These pins may not be part of the each JTAG-compliant device’s core functionality, but they play an essential role in the boundary scan test, enabling the tester to exercise control over the device’s input and output behaviour.
15 [0063] Further, at step 406, the method of the present disclosure comprises
establishing, by a processing unit [306], a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins (as also shown in block 506 of Fig. 5). In a JTAG system or the system under test (SUT), multiple JTAG-compliant devices may often be connected in a
20 daisy chain configuration, wherein the TDO (Test Data Output) pin of one device
is connected to the TDI (Test Data Input) pin of the next device. This setup allows for the propagation of test data from one device to the next in the chain. The tester establishes this daisy chain based on the information gathered from the BSDL files and the known configuration of the SUT. In an implementation, the processing unit
25 [306] may switch between a single JTAG chain configuration and the daisy chain
configuration using a jumper that controls an enable pin of each of one or more of level shifters, wherein in the single JTAG chain configuration, one or more pins of each Application-Specific Integrated Circuit (ASIC) of the JTAG compliant devices are connected to one or more individual JTAG connectors directly, and in
30 the daisy chain configuration, a Test Data Output (TDO) pin of the ASIC is
connected to a Test Data Input (TDI) pin of a subsequent ASIC of the daisy chain
23

configuration. Further, in an implementation, the processing unit [306] may connect
a plurality of peripheral devices to the ASIC via interfaces, wherein the plurality of
peripheral devices comprises a memory device, an Ethernet PHY transceiver, a re-
timer, a universal asynchronous receiver / transmitter (UART) connector, an inter-
5 integrated circuit (I2C) switches/ a multiplexer, an I2C serial peripheral interface
(SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature
sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock
synchronizer, an analog-to digital converter (ADC), a digital to analog converter
(DAC), and a digital step attenuator (DSA). Also, in an implementation, the one or
10 more interfaces for connecting peripheral devices comprise at least one from among
an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed interconnects, or any combination thereof.
15
[0064] Further, at step 408, the method of the present disclosure comprises categorizing, by the processing unit [306], each of the set of JTAG-compliant devices in to at least one of a passive device (as also shown in block 508 of Fig. 5), a test device (as also shown in block 510 of Fig. 5), and a logic device (as also
20 shown in block 512 of Fig. 5). The processing unit [306] checks whether the daisy
chain has been correctly established. This may be done by running a test that checks if identity codes of all devices are correctly detected. If the identity codes’ values match their corresponding expected values, the processing unit [306] may infer that the daisy chain has been correctly set up. The processing unit [306] categorizes each
25 device into one of the following types: the passive device (for e.g., devices such as,
but not limited to, resistors, capacitors, inductors), the test device (for e.g., devices such as, but not limited to, integrated circuits having boundary scan file to support JTAG test), and the logic device (for e.g., logical gates such as, but not limited to, AND gate, OR gate, NOT gate, NAND gate, and buffers, etc.). This classification
30 informs how the tester will interact with each device and what tests it may perform.
For example, tests related to memories (EEPROM (electrically erasable
24

programmable read-only memory) tests, SD (secure digital) card tests, etc.), tests related to sensors (temperature sensor test, current sensor test, etc.), etc. as also shown in Fig. 7 which shows exemplary JTAG Boundary Scan Test results.
5 [0065] Further, at step 410, the method of the present disclosure comprises
generating, by a generating unit [308], at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files (as also shown in block 514, 516, and 518 of Fig. 5). Based on the device type and the information in the BSDL file, the tester generates
10 appropriate test codes. These are a sequence of inputs that the tester will apply to
each device to carry out the boundary scan test. If a new device is encountered, the tester may generate a new test code based on a template, else if the test files for a device are already available, then the test codes available in a database may be used (as also shown in block 514, 516, and 518 of Fig. 5), that is, the test codes may be
15 generated based on at least one of: using a library of test files, and a template stored
in a database. Here, a template refers to an existing code in the library of test files using which a component can be tested, or in case a new component is encountered, then a modification may be made to the existing test code to generate the new test code for the new component.
20
[0066] Besides the JTAG boundary scan test, the tester might also interact with the Inter-Integrated Circuit (I2C) and the serial peripheral interface (SPI) devices on the SUT. For this, it may generate additional I2C and SPI circuit codes to enable generating control signals to access these devices (as also shown in block 520 of
25 Fig. 5). The tester checks whether the I2C slave correctly acknowledges the I2C
address. This could involve selecting the SPI slave device, sending a command or data, and waiting for an acknowledgment signal. The acknowledgment is then read back and verified.
30 [0067] Further, at step 412, the method of the present disclosure comprises
generating, by the generating unit [308], a set of results after completion of
25

execution of the generated at least one test code. In an implementation, the test code
may be implemented within a simulation environment. In an implementation, the
processing unit [306] may perform one or more additional tests related to
reading/writing registers, measuring voltages or currents, checking temperature
5 sensors, or verifying manufacture IDs (as also shown in block 524 of Fig. 5). These
tests may be specific to the device under test and its functionality. After all tests
have been completed, the generating unit [308] may compile the results and
generate a comprehensive report. This report may detail any issues found during
the testing process and provide crucial information for diagnosing and fixing those
10 issues.
[0068] Now, referring to FIG. 6A that illustrates a first part of an exemplary scenario flow diagram for boundary scan test of 5G NR IMRU (5th generation new radio integrated massive multiple input multiple output radio unit), in accordance
15 with exemplary embodiments of the present disclosure, and FIG. 6B that illustrates
a second part of an exemplary scenario flow diagram for boundary scan test of 5G NR IMRU, in accordance with exemplary embodiments of the present disclosure. A person skilled in the art would appreciate that the process of FIG. 6A and 6B is provided for understanding purposes only and does not limit or restrict the
20 disclosure in any possible manner. As shown in FIG. 6A and 6B, at block 602, it is
checked if the daisy chain configuration of the JTAG compliant devices is complete or not, i.e., whether codes of all the JTAG compliant devices are correctly detected or not. If the daisy chain configuration of the JTAG compliant devices is not complete, then it leads to flag failure at block 604 (indicating the intended device
25 scan, detection, and/or test has failed). If the daisy chain configuration of the JTAG
compliant devices is complete, then it leads to block 606 at which general-purpose input/output (GPIO) devices and the JTAG compliant devices are configured such that the devices are out of reset. Further, it is checked if connection test is passed at block 608. This is the connection test for all pins for the JTAG-compliant devices.
30 If the connection test is not passed, then it leads to flag failure at block 610. If the
connection test is passed, then it leads to blocks 614, 612, and 638. These three
26

steps/executions and their further associated executions may be done in parallel. At
block 614 following the block 608, it is checked if the memories are connected
directly to the ASIC. If the memories are connected directly to the ASIC, then an
individual detailed memory test is performed at block 618. If the test is passed, then
5 the device passes the boundary scan test as shown in block 620. Also, at block 612
following the block 608, it is checked if the I2C devices and/or the SPI slave devices are connected directly to the ASIC. If the I2C devices and/or the SPI slave devices are connected directly to the ASIC, it is checked if the slaves acknowledge the I2C address or the SPI slave readback is success at block 622. If the slaves do not
10 acknowledge the I2C address (or SPI slave readback is a failure), then it leads to
flag failure at block 616. If the slaves acknowledge the I2C address (or SPI slave readback is a success), then other detailed tests like read/write registers and perform mathematical calculation based on device function, are performed at block 624. If the tests pass at block 626, then the device passes the boundary scan test as shown
15 in block 628. If the tests are not passed at block 626, then it leads to a flag failure
at block 648. Also, at block 612, when it is checked if the I2C devices and/or the SPI slave devices are connected directly to the ASIC, if it is determined that the I2C devices and/or the SPI slave devices are not connected directly to the ASIC, then the I2C slaves may be connected to the ASIC through switch(es) or multiplexers at
20 block 630. Further, it is checked if the switch(es) or multiplexers acknowledge the
I2C address at block 632. If the switch(es) or multiplexers do not acknowledge the I2C address, then it leads to the flag failure at block 634. If the switch(es) or multiplexers acknowledge the I2C address, then respective channel of switch(es) or multiplexers is selected at block 636, and it is checked if the slaves acknowledge
25 the I2C address or the SPI slave readback is success at block 622. Also, at block
638 following the block 608, the Ethernet physical layer or SFP (Small Form-factor Pluggable) module, or UART (universal asynchronous receiver-transmitter) module may be connected directly to the ASIC. Further, the individual tests may be performed at block 640. If these individual tests are failed, then it leads to the flag
30 failure at block 642. If these individual tests are passed, then the devices pass the
boundary scan test as shown in block 644.
27

[0069] Also, Referring to Fig. 7 which shows exemplary JTAG Boundary Scan
Test results, in accordance with an embodiment of the present disclosure. In Fig. 7,
an exemplary set of results for implemented boundary scan testing results of 5G NR
5 Integrated MRU board is shown. In Fig. 7, it is depicted that by implementing the
features of the disclosure as discussed above, the test time of 51 out of 85 active
peripherals may be, for example, less than 4 minutes, and the overall test coverage
of 60% may be achieved. A person skilled in the art would appreciate that the above
exemplary test results as shown with reference to Fig. 7 do not restrict or limit the
10 present disclosure in any possible manner and the test time and the overall test
coverage may vary, for instance, based on a number of components on an Integrated MRU board and/or a type of components on the Integrated MRU board.
[0070] The present disclosure further discloses a user equipment in communication
15 with a system [300] for boundary scan testing of joint test action group (JTAG)-
compliant devices in a massive MIMO Radio Unit (MRU). The user equipment comprises at least a user interface configured to receive a set of results related to the boundary scan testing of the JTAG-compliant devices. The set of results is generated by the system [300] based on: (a) receiving, by a receiving unit [302] via
20 JTAG tester, a set of boundary scan description language (BSDL) files
corresponding to a set of JTAG-compliant devices; (b) determining, by a determining unit [304], a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester; (c) establishing, by a processing unit [306], a daisy chain configuration based on an information associated with the set of
25 BSDL files and the determined set of non-logical pins; (d) categorizing, by the
processing unit [306], each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device; (e) generating, by a generating unit [308], at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and (f)
30 generating, by the generating unit [308], the set of results after completion of
execution of the generated at least one test code.
28

[0071] The present disclosure further discloses a non-transitory computer readable
storage medium storing instructions for boundary scan testing of joint test action
group (JTAG)-compliant devices in a massive multiple input and multiple output
5 Radio Unit (MRU), the instructions include executable code which, when executed
by a one or more units of a system [300], causes: a receiving unit [302] of the system [300] to receive a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices. Further, the instructions include executable code which, when executed causes a determining unit [304] of the
10 system [300] to determine a set of non-logical pins for each of the set of JTAG-
compliant devices within a JTAG tester. Further, the instructions include executable code which, when executed causes a processing unit [306] of the system [300] to establish a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins. Further, the
15 instructions include executable code which, when executed causes the processing
unit [306] of the system [300] further to categorize each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device. Further, the instructions include executable code which, when executed causes a generating unit [308] of the system [300] to: generate at least one test code
20 based on the categorized set of JTAG-compliant devices and the information
associated with the set of BSDL files; and to generate a set of results after completion of execution of the generated at least one test code.
[0072] As is evident from the above, the present disclosure provides a technically
25 advanced solution for boundary scan testing of joint test action group (JTAG)-
compliant devices in a massive multiple input and multiple output (MIMO) Radio
Unit (MRU). The present solution performs comprehensive testing in less time
compared to traditional testing methods, improving manufacturing efficiency and
throughput. Further, the present solution ensures testing of the entire board with
30 maximum coverage in one go. Further, the present solution reduces the time spent
on debugging, especially in the case of field-deployed failure units. Further, the
29

present solution enhances the maintainability of the product and reduces operational
expenditure related to product failures of field-deployed units. Further, the present
solution helps to pinpoint the exact location of issues on field failure units, leading
to a reduction in debugging time and thus a lower failure turnaround time. Further,
5 the present solution uses relatively low-cost components like buffers/level shifters,
switches and jumpers to switch from single chain to daisy chain JTAG mode, offering a cost-effective solution.
[0073] While considerable emphasis has been placed herein on the disclosed
10 implementations, it will be appreciated that many implementations can be made and
that many changes can be made to the implementations without departing from the
principles of the present disclosure. These and other changes in the implementations
of the present disclosure will be apparent to those skilled in the art, whereby it is to
be understood that the foregoing descriptive matter to be implemented is illustrative
15 and non-limiting.
30

We Claim:
1. A method [400] for boundary scan testing of joint test action group (JTAG)-
compliant devices in a massive multiple input and multiple output Radio Unit
(MRU), the method [400] comprising:
receiving, by a receiving unit [302], a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices;
determining, by a determining unit [304], a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester;
establishing, by a processing unit [306], a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins;
categorizing, by the processing unit [306], each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device;
generating, by a generating unit [308], at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and
generating, by the generating unit [308], a set of results after completion of execution of the generated at least one test code.
2. The method [400] as claimed in claim 1, further comprising: switching
between a single JTAG chain configuration and the daisy chain configuration
using a jumper that controls an enable pin of each of one or more level
shifters, wherein in the single JTAG chain configuration, one or more pins of
each Application-Specific Integrated Circuit (ASIC) of the JTAG compliant
devices are connected to one or more individual JTAG connectors directly,
and in the daisy chain configuration, a Test Data Output (TDO) pin of the
ASIC is connected to a Test Data Input (TDI) pin of a subsequent ASIC of
the daisy chain configuration.

3. The method [400] as claimed in claim 2, further comprising: connecting a plurality of peripheral devices to the ASIC via one or more interfaces, wherein the plurality of peripheral devices comprises, a memory device, an Ethernet PHY transceiver, a re-timer, a universal asynchronous receiver / transmitter (UART) connector, an Inter-Integrated Circuit (I2C) switch, a multiplexer, an I2C serial peripheral interface (SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock synchronizer, an analog-to-digital converter (ADC), a digital to analog converter (DAC), and a digital step attenuator (DSA).
4. The method [400] as claimed in claim 3, wherein the one or more interfaces for connecting peripheral devices comprise at least one from among an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed interconnects, or any combination thereof.
5. The method [400] as claimed in claim 1, comprising: performing one or more additional tests related to reading/writing registers, measuring voltages or currents, checking temperature sensors, or verifying manufacture IDs.
6. The method [400] as claimed in claim 1, wherein the test codes are generated based on one of: using a library of test files, and a template stored in a database.
7. A system [300] for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive Radio Unit (MRU), the system [300] comprises:

a receiving unit [302] configured to receive a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices;
a determining unit [304] connected to at least the receiving unit [302], the determining unit [304] configured to determine a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester;
a processing unit [306] connected to at least the determining unit [304], the processing unit [306] configured to establish a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins;
the processing unit [306] connected to at least the determining unit [304], the processing unit [306] configured to categorize each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device;
a generating unit [308] connected to at least the processing unit [306], the generating unit [308] configured to generate at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and
the generating unit [308] connected to at least the processing unit [306], the generating unit [308] configured to generate a set of results after completion of execution of the generated at least one test code.
The system [300] as claimed in claim 7, wherein the processing unit [306] is further configured to switch between a single JTAG chain configuration and the daisy chain configuration using a jumper that controls an enable pin of each of one or more level shifters, wherein in the single JTAG chain configuration, one or more pins of each Application-Specific Integrated Circuit (ASIC) of the JTAG compliant devices are connected to one or more individual JTAG connectors directly, and in the daisy chain configuration, a Test Data Output (TDO) pin of the ASIC is connected to a Test Data Input (TDI) pin of a subsequent ASIC of the daisy chain configuration.

9. The system [300] as claimed in claim 8, wherein the processing unit [306] is further configured to connect a plurality of peripheral devices to the ASIC via one or more interfaces, wherein the plurality of peripheral devices comprises a memory device, an Ethernet PHY transceiver, a re-timer, a universal asynchronous receiver / transmitter (UART) connector, an inter-integrated circuit (I2C) switch, a multiplexer, I2C serial peripheral interface (SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock synchronizer, an analog-to digital converter (ADC), a digital to analog converter (DAC), and a digital step attenuator (DSA).
10. The system [300] as claimed in claim 9, wherein the one or more interfaces for connecting peripheral devices comprise at least one from among an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed interconnects, or any combination thereof.
11. The system [300] as claimed in claim 7, wherein the processing unit [306] is configured to perform one or more additional tests related to reading/writing registers, measuring voltages or currents, checking temperature sensors, or verifying manufacture IDs.
12. The system [300] as claimed in claim 7, wherein the test codes are generated based on one of: using a library of test files, and a template stored in a database.
13. A user equipment in communication with a system [300] for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive MIMO Radio Unit (MRU), the user equipment comprising at least:

a user interface configured to receive a set of results related to the boundary scan testing of the JTAG-compliant devices, wherein the set of results is generated by the system [300] based on:
receiving, by a receiving unit [302] via JTAG tester, a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices;
determining, by a determining unit [304], a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester;
establishing, by a processing unit [306], a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins;
categorizing, by the processing unit [306], each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device;
generating, by a generating unit [308], at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and
generating, by the generating unit [308], the set of results after completion of execution of the generated at least one test code.