DESC:FIELD
The present disclosure relates generally to the field of security systems. More particularly, the present disclosure relates to a tamper detection device.
BACKGROUND
The background information herein below relates to the present disclosure but is not necessarily prior art.
Currently available passive and active Radio Frequency Identification (RFID) or Near Field Communication (NFC) based security seals/tags with tamper flags are not capable of detecting a tamper event in real time unless they are polled by an RFID/NFC reader. In the absence of RFID/NFC reader, a skilled counterfeiter can tamper with such a tag/seal and reassemble the same without leaving any electronic trace i.e. without changing the status of the tamper flag. Further, the conventional security systems are not capable of detecting unauthorized intrusions into the containers which are made without touching/damaging the seals, for example, by drilling holes through the containers. Such tampering events are not recorded by the tamper seal. Hence, under such a condition, when the tamper flag is read by an RFID reader, it will show a non-tampered status even though the seal/tag has been tampered with, which is not desired.
Furthermore, the conventional seal comprises transducers, a logical gate, a processing unit, a capacitor, a power supply unit, and a tamper tag. These components, except for the tamper tag, are assembled on one side and installed inside the container. The tamper tag is mounted outside the container to allow a reader to determine the seal's status, indicating whether it has been tampered with. The internal components are connected to the external tamper tag via a set of conductive tracks.
Due to the split installation of components—some inside the container and some outside—there is a high risk that counterfeiters may tamper with the conductive tracks or cables used for these connections. If a counterfeiter short-circuits one of these conductive tracks, the logical gate, which is responsible for changing the state of the tamper tag, remains unaffected because it is located with the processing unit inside the container, before the conductive track. Consequently, the processing unit detects the tampering but cannot communicate this to the tamper tag, as the short-circuited conductive track prevents the change in the tamper tag's status. This flaw allows a counterfeiter to tamper with the seal without altering its status indication.
There is, therefore, felt a need for developing a tamper detection device that eliminates the above-mentioned drawbacks.
OBJECTS
Some of the objects of the present disclosure, which at least one embodiment herein satisfies, are as follows:
It is an object of the present disclosure to ameliorate one or more problems of the prior art or to at least provide a useful alternative;
An object of the present disclosure is to provide a tamper detection device.
Another object of the present disclosure is to provide a tamper detection device that detects a tamper event and state of the device in real time.
Yet another object of the present disclosure is to provide a tamper detection device that detects a tamper event even if the device is not damaged/broken during tampering.
Still another object of the present disclosure is to provide a tamper detection device that uses a combination of RFID+NFC communication technology to obviate the need for more expensive technology or elaborate solutions involving high power consumption communication technologies like Bluetooth/BLE, Wi-Fi.
Yet another object of the present disclosure is to provide a tamper detection device that detects the tamper event even if the conductive tracks are short circuited.
Still another object of the present disclosure is to provide a tamper detection device that provides different logical gate arrangement to ensure it directly influences the tamper tag's state, even in the presence of tampering attempts, by incorporating tamper detection logic that operates independently of the conductive tracks
Other objects and advantages of the present disclosure will be more apparent from the following description, which is not intended to limit the scope of the present disclosure.
SUMMARY
The present disclosure envisages a tamper detection device. The device is configured to be affixed to an operative surface of a container to detect unauthorized intrusion (if any). The device comprises: at least one transducer, configured to detect a tamper event, and generate a corresponding trigger signal upon detection of the tamper event; a power supply unit, configured to provide power to at least one component of the device; a processing unit in communication with the power supply unit and the transducer, the processing unit is configured to receive the trigger signal from the transducer and process the trigger signal to generate a corresponding tamper detection signal; a logical gate, configured be in communication with the processing unit to receive the tamper detection signal, the logical gate is configured to be operable in an open state and a close state and further configured to change the state relative to the tamper detection signal upon occurrence of unauthorized intrusion event(s) (if any); a tamper tag in communication with the logical gate, the tamper tag is configured to store a tamper flag value and further configured to receive the tamper detection signal from the logical gate to change the tamper flag value, wherein the tamper flag value indicates a tamper status of the device; a plurality of conductive tracks, configured to separately connect the logical gate, the tamper tag and at least one of the transducer with the processing unit; a capacitor, configured to be in communication with the processing unit to facilitate power supply in absence of the power supply unit. The device is characterized such that the logical gate is mounted on the operative terminals of the tamper tag, thereby facilitating the generation of the tamper detection signal when at least one of the conductive tracks is short-circuited, thus causing the tamper state of the device to change from “non-tampered” to “tampered” state in response to unauthorized intrusion.
In an embodiment, the unauthorized intrusion event(s) includes:
• receiving the trigger signal from at least one of the transducer; and
• detecting a cut-off of power supply from the power supply unit.
In an embodiment, the transducer, the power supply unit, the capacitor and the processing unit are collectively acts as a circuit module on an operative inner surface of the container.
In an embodiment, the tamper tag, the logical gate are collectively acts as an antenna module on an operative outer surface of the container.
In an embodiment, the device includes an antenna, configured to be mounted on the antenna module in communication with the tamper tag. The antenna is configured to transmit the state of the device to a reader when the tag is scanned by the reader. The antenna is selected from a group consisting of a Radio Frequency Identification (RFID) antenna, a Near Field Communication (NFC) antenna, and an NFC+RFID antenna.
In an embodiment, the circuit module is in communication with the antenna module by means of the plurality of conductive tracks.
In an embodiment, the plurality of conductive tracks includes a first conductive track, a second conductive track, and a third conductive track. The first conductive track connects the logical gate with the processing unit, the second conductive track connects the tamper tag with the processing unit, and the third conductive track connects the tamper tag with the processing unit.
In an embodiment, the short circuiting of any one of the first conductive track with the second conductive track, or the first conductive track with third conductive track or the second conductive track with the third conductive track results in generation of the tamper detection signal to thereby change in the state of device from “non-tampered” to a “Tampered” state.
In an embodiment, the transducer includes a first transducer and a second transducer. The first transducer is configured to sense the change in pressure of the container and typically selected from group of a pressure transducer. The second transducer is configured to sense the presence of light in the container in an operative configuration of the device and typically selected from a group of a photoelectric transducer.
In an embodiment, the antenna module includes an LED indicator, in communication with the tamper tag. The LED indicator is configured to blink at different predetermined interval to indicate the state of the device, and selected from the group consisting of arming state, armed state, non-tampered state, and tampered state.
In an embodiment, the circuit module includes a set of sensors, configured to detect at least one critical parameter corresponding to a change in the state of said logical gate and generate a corresponding sensed signal.
In an embodiment, the LED indicator is configured to be in communication with said set of sensors. The LED signal is configured to receive the sensed signal from the set of sensors and is further configured to indicate the state of the device.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWING
A tamper detection device of the present disclosure will now be described with the help of the accompanying drawing, in which:
Figure 1 illustrates a block diagram of a conventional tamper detection device (Prior art);
Figure 2 illustrates a fixing arrangement of the conventional tamper detection device of Figure 1 on a container door; (Prior art)Figure 3A the operation of the logical gate (transistor) connected to the terminals of the tamper tag when zero potential voltage (OFF) is applied across the base of the logical gate;
Figure 3B illustrates the operation of the logical gate (transistor) connected to the terminals of the tamper tag when a desired potential voltage (ON) is applied across the base of the logical gate;
Figure 4A illustrates a circuit diagram showing the logical gate and the tamper tag connected via a plurality of conductive tracks, with zero potential voltage applied across the circuit in the conventional tamper detection device;
Figure 4B illustrates a circuit diagram showing the logical gate and the tamper tag connected via a plurality of conductive tracks, with a desired potential voltage applied across the circuit in the conventional tamper detection device;
Figure 5 illustrates a block diagram of the tamper detection device, in accordance with the present disclosure.
Figure 6 illustrates a circuit diagram showing the power supply unit, the transducers, connected via a plurality of conductive tracks with LED indicator, and the tamper tag in accordance with the present disclosure.
Figure 7A illustrates a circuit diagram showing the tamper tag and the logical gate connected to the terminals of the tamper tag with zero potential voltage applied across the circuit via a plurality of conductive tracks, in accordance with the first embodiment of the present disclosure;
Figure 7B illustrates a circuit diagram showing the tamper tag and the logical gate connected to the terminals of the tamper tag, with the conductive tracks short-circuited and zero potential voltage applied across the circuit, in accordance with the first embodiment of the present disclosure;
Figure 8A illustrates a circuit diagram showing the tamper tag and the logical gate connected to the terminals of the tamper tag with a desired potential voltage applied across the circuit via a plurality of conductive tracks, in accordance with the second embodiment of the present disclosure;
Figure 8B illustrates a circuit diagram showing the tamper tag and the logical gate connected to the terminals of the tamper tag, with the conductive tracks short-circuited and desired potential voltage applied across the circuit, in accordance with the second embodiment of the present disclosure; and
Figure 9A through Figure 9I illustrates flow charts depicting indication of various states of the tamper detection device of Figure 5.
LIST OF REFERENCE NUMERALS USED IN DETAILED DESCRIPTION AND DRAWING
100’– Conventional tamper detection device
100 – Tamper detection device of the present disclosure
102 –Tamper Tag
104 –Processing unit
106 – First transducer
108 – Auxiliary Capacitor
110 – Second transducer
112 – Logical Gate (BJT/MOSFET)
114 – Battery (Power supply unit)
116 – Sensor
118 – LED indicator
120 – Reader
122a–first conductive track
122b– second conductive track
122c– third conductive track
124– short circuit conductive track
202 – Door frame
204 – Edge of the door
206 – Container door
208– Inner face of the container door
DETAILED DESCRIPTION
Embodiments, of the present disclosure, will now be described with reference to the accompanying drawing.
Embodiments are provided so as to thoroughly and fully convey the scope of the present disclosure to the person skilled in the art. Numerous details, are set forth, relating to specific components, and methods, to provide a complete understanding of embodiments of the present disclosure. It will be apparent to the person skilled in the art that the details provided in the embodiments should not be construed to limit the scope of the present disclosure. In some embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.
The terminology used, in the present disclosure, is only for the purpose of explaining a particular embodiment and such terminology shall not be considered to limit the scope of the present disclosure. As used in the present disclosure, the forms "a,” "an," and "the" may be intended to include the plural forms as well, unless the context clearly suggests otherwise. The terms "comprises," "comprising," “including,” and “having,” are open ended transitional phrases and therefore specify the presence of stated features, integers, steps, operations, elements, modules, units and/or components, but do not forbid the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
When an element is referred to as being "mounted on," “engaged to,” "connected to," or "coupled to" another element, it may be directly on, engaged, connected or coupled to the other element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed elements.
Existing security seals/tags (100’) are not capable of detecting tamper events that are carried out without damaging/breaking the seals. Therefore, a security seal can be skillfully tampered with, without affecting the value of tamper flag within the seal, such that when the tamper flag is read by a reader, it will show a non-tampered status even though the seal/tag has been tampered with. Figure 1 illustrates a block diagram of a conventional tamper detection device (100’) or seal (Prior art).
Further, the conventional seal or device (100’) comprises transducers, a logical gate (112), a processing unit (104), a capacitor (108), a power supply unit (114), and a tamper tag (102) as shown in Figure 1. These components, except for the tamper tag (102), are assembled on one side and installed inside the container. The tamper tag (102) is mounted outside the container to allow a reader to determine the seal's status, indicating whether it has been tampered with. The internal components are connected to the external tamper tag (102) via a set of conductive tracks. Figure 2 illustrates a fixing arrangement of the tamper detection device of Figure 1 on a container door.
The logical gate (112) is used as switching element between two terminals of tamper tag; that control the impedance characteristics between said two terminals of the said tampered tag. Impedance can be low or high based on the biasing characteristics of the said logical gate. Tamper status of the tamper tag is controlled by this impedance. The antenna transmits the tamper status of the device to a reader when a tag is read by reader. Once a tamper tag finds the “tampered” state it permanently record in its EEPROM that cannot be undone by any means.
In case OFF state of the logical gate (112) as shown in Figure 3A: The logical gate (112), typically a transistor, is in the OFF state when zero potential voltage (0V) is applied across its base (for a npn Bipolar Junction Transistor (BJT)) or gate (for a normally open Field-Effect Transistor (FET)). In this state, the transistor does not conduct current between its collector and emitter (for a BJT) or between its drain and source (for a FET). Therefore, when the logical gate (112) is OFF, it induces a high impedance across the operative terminals of the tamper tag (102). The high impedance effectively means that the circuit between the tamper tag (102)’s terminals and the logical gate (112)'s output is non-conductive. The resistance in the path is very high, and thus, minimal current flows through the path. When tamper tag is scanned by the reader and tamper tag finds high impedance between it’s terminals; antenna transmits the “tampered” state of the device to a reader. In case of ON state of the logical gate (112) as shown in Figure 3B: The logical gate (112) is considered to be in the ON state when a desired potential voltage, such as 5V, is applied across its base (for a BJT) or gate (for an FET). Applying this voltage forward-biases the transistor, allowing it to conduct between its collector and emitter (for a BJT) or between its drain and source (for an FET). When the logical gate (112) is ON, it induces a low impedance across the operative terminals of the tamper tag (102). The low impedance means that the circuit between the tamper tag (102)’s terminals and the logical gate (112)’s output becomes conductive. The resistance in this path is significantly reduced, allowing current to flow freely. When tamper tag is scanned by the reader and tamper tag finds low resistance between it’s terminals; antenna transmits the “non-tampered” state of the device to a reader.
Further due to split installation of components—some inside the container and some outside—there is a high risk that counterfeiters may tamper with the conductive tracks or cables used for these connections. If a counterfeiter short-circuits one of these conductive tracks, the logical gate (112), which is responsible for changing the state of the tamper tag (102), remains unaffected because it is located with the processing unit (104) inside the container, before the conductive track. Consequently, the processing unit (104) detects the tampering but cannot communicate this to the tamper tag (102), as the short-circuited conductive track prevents the change in the tamper tag (102)'s status. This flaw allows a counterfeiter to tamper with the seal without altering its status indication.
As depicted in Figure 4A, the logical gate (112) (typically a transistor) is connected to the operative terminals of the tamper tag (102) through a plurality of conductive tracks (122a, 122b, 122c). The conductive tracks serve as electrical pathways that facilitate communication and interaction between the logical gate (112) and the tamper tag (102). When the logical gate (112) is in the OFF state as shown in Figure 4A (i.e., zero potential voltage applied across its base for a BJT or gate for an FET), it behaves as a non-conductive element. In this state, the logical gate (112) introduces a high impedance between its output and the tamper tag (102) terminals. However, a counterfeiter may attempt to bypass or disrupt the tamper tag (102) by creating a short circuit between any two of the conductive tracks using a short-circuit conductive track 124 as shown in figure 4B. For example, if Track 122a and Track 122b are short-circuited, or if Track 122b and Track 122c are short-circuited, the conductive material creates an unintended low-resistance path (low impedance) between these tracks and across the terminals of the tamper tag (102). The short-circuit provides a direct electrical path with very low resistance, thus reducing the overall impedance observed across the tamper tag (102) terminals. In the case of the conventional tamper detection device, the presence of low impedance due to short-circuited tracks does not necessarily result in a change in the tamper tag (102)’s status. This is because the tamper tag (102) may not have the capability to distinguish between a legitimate operational signal and an induced short-circuit condition. As a result, the tamper tag (102) fails to detect the tampering event caused by the short circuit, leading to no change in its status in case of the conventional device (100’). The conventional tamper detection device (100’), therefore, does not register the unauthorized intervention accurately.
To overcome the aforementioned problem, a tamper status detecting device (hereinafter referred as “device 100”) of the present disclosure is envisaged.
The tamper detection device 100 is affixed to a product for detecting an unauthorized intrusion of the product including containers, store rooms, storage containers, shipping containers, bottles, luggage, valuable commodities and the like. In case of rooms/containers, the device 100 may be affixed to one or more doors of the rooms/containers.
Referring to Figures 5, the tamper detection device 100 of the present disclosure comprises a tamper tag 102, a processing unit 104, a logical gate 112, a power supply unit 114, at least one transducer (106 and 110), a plurality of conductive tracks (122a, 122b, 122c) and a capacitor 108.
The transducer 106, 110 is configured to detect at least one tamper event, and is further configured generate at least one trigger signal upon detection of the at least one tamper event.
The logical gate 112 is configured to be operable in states consisting of open state and closed state.
The processing unit 104 is configured in communication with the power supply unit 114 to receive power. The processing unit 104 is configured to receive power from the power supply unit 114. The processing unit 104 is further configured to cooperate with the transducer 106, 110 and the logical gate 112 to generate a tamper detection signal for changing the state of the logical gate 112 upon the occurrence of an event selected from a group of events consisting of:
(i) receiving the trigger signal from the transducer (106, 110); and
(ii) detecting a cut-off of power supply from the power supply unit 114.
The tamper tag 102 is connected to the logical gate 112. The tamper tag comprises a set of sensors 116 connected to the logical gate 112. The sensors 116 are configured to detect at least one critical parameter corresponding to a change in the state of the logical gate 112 and generate a sensed signal. The tamper tag 102 further comprises an LED indicator 118 configured to communicate with the set of sensors. The LED indicator 118 is configured to receive the sensed signal from the set of sensors 116, and is further configured to indicate the state of the device 100.
The Conductive Tracks (122a, 122b, 122c) are configured to connect the logical gate (112), the tamper tag (102), and the transducers (106, 110) with the processing unit (104). The conductive tracks facilitate the necessary electrical connections for signal transmission. The conductive tracks include a first conductive track (122a) connecting the logical gate (112) with the processing unit (104), a second conductive track (122b) connecting the tamper tag (102) with the processing unit (104) and a third conductive track (122c) connecting the tamper tag (102) with the processing unit (104).
The terminals of the tamper tag 102 is connected to the logical gate 112 that is driven by the processing unit 104. The proposed configuration is pivotal as it enables the generation of the tamper detection signal when any of the conductive tracks (122a, 122b, 122c) is short-circuited. The logical gate (112), in response to the tamper detection signal, changes the device’s state from “non-tampered” to “tampered,” thereby indicating unauthorized intrusion. The short-circuiting any of the conductive tracks (122a with 122b, 122a with 122c, or 122b with 122c) generates the tamper detection signal, thereby changing the device's state to “tampered” in an operative configuration of the device (100).
Figure 6 illustrates a circuit diagram showing the power supply unit, the transducers, connected via a plurality of conductive tracks with LED indicator, and the tamper tag in accordance with the present disclosure.
In the first embodiment, the logical gate (112) is directly connected to the operative terminals of the tamper tag (102) via conductive tracks. The proposed setup is illustrated in Figure 7A. The key point here is the behavior of the circuit when the logical gate (112) is in the OFF state and when a counterfeiter attempts to short-circuit the conductive tracks. The logical gate (112) is directly interfaced with the operative terminals of the tamper tag (102). The connection is established through conductive tracks, labeled as Track 122a, Track 122b, and Track 122c, as shown in Figure 7A. When the logical gate (112) is in the OFF state, zero potential voltage is applied across its base. This induces a high impedance across the terminals of the tamper tag (102), preventing significant current flow through the circuit. When a counterfeiter attempts to short-circuit any of the conductive tracks (122a, 122b, 122c) using the short-circuiting conductive track (124). This action is aimed at bypassing the intended impedance characteristics of the circuit. When the short-circuiting conductive track (124) is used, it creates an alternative low-resistance path across the conductive tracks. In the OFF state, the short circuit does not alter the impedance of the circuit significantly, as the logical gate (112)’s high impedance dominates. Despite the short-circuiting attempt, the circuit impedance remains high, as the logical gate (112) in the OFF state continues to block significant current flow. Therefore, there is no immediate change in the impedance profile. However, the presence of the short-circuiting path alters the expected flow of electrical signals. The change in the flow triggers the logical gate (112) to re-evaluate the status of the tamper tag (102). Consequently, the logical gate (112) transitions the tamper tag (102)’s state from “Non-tampered” to “Tampered” in the operative configuration shown in Figure 7B.
In the second embodiment, the logical gate (112) is again directly connected to the operative terminals of the tamper tag (102) via conductive tracks, as illustrated in Figure 8A. The critical aspect here is how the circuit behaves when the logical gate (112) is in the ON state (representing tag’s present status “Non-tampered”) and when a counterfeiter attempts to short-circuit the conductive tracks. Similar to the first embodiment, the logical gate (112) interfaces directly with the operative terminals of the tamper tag (102) through conductive tracks (Track 122a, Track 122b, Track 122c), as depicted in Figure 8A. When the logical gate (112) is in the ON state, a desired potential voltage (e.g., 5V) is applied across its base, inducing a low impedance across the tamper tag (102) terminals. This condition allows current to flow freely through the circuit, maintaining a low-resistance path. When the counterfeiter attempts to short-circuit any of the conductive tracks (122a, 122b, 122c) using the short-circuiting conductive track (124). This action aims to manipulate the circuit’s impedance characteristics. When the short-circuiting conductive track (124) is introduced, it creates an alternative low resistance path across the conductive tracks and alters the impedance across the conductive tracks. In the ON state, this modification changes the impedance profile of the circuit from low impedance to high impedance, as the short-circuit path provides a low-resistance route. The introduction of the short-circuiting track changes the impedance from low to high. This transition is critical because the logical gate (112), now in the ON state, detects the impedance shift. The change in impedance triggers the logical gate (112) to re-assess the tamper tag (102)’s status. As a result, the logical gate (112) alters the state of the tamper tag (102) from “Non-tampered” to “Tampered,” as depicted in the operative configuration shown in Figure 8B.
In an embodiment, the LED indicator is configured to blink at different predetermined rates to indicate the state of the device 100 selected from the group consisting of arming state, armed state, non-tampered state, and tampered state.
In an embodiment, the tag 102 further includes an antenna for transmitting the state of the device 100 to a reader when the tag 102 is scanned by the reader 120. The antenna may be selected from the group consisting of a Radio Frequency Identification (RFID) antenna, a Near Field Communication (NFC) antenna, and an NFC+RFID antenna. Accordingly, the tamper flag value can be read by an RFID/NFC reader 120.
In an exemplary embodiment, the device 100 includes two transducers 106, 110. One pair of output terminals/leads of the processing unit 104 is connected to the first transducer 106 and another pair of output terminals/leads of the processing unit 104 is connected to the second transducer110. The first and second transducers 106, 110 are configured to detect tamper events, and the processing unit 104 is further configured to change the state of the logical gate, upon detection of the tamper events. The change in state of logical gate is sensed by the sensors which generates corresponding sensed signals. These signals are received by an LED indicator to indicate the state of the device 100.
The first and second transducers (106, 110) are selected from the group consisting of a pressure transducer, a flow meter sensor, a temperature sensor, a piezoelectric transducer, a photoelectric transducer, a capacitive sensor and the like.
In an embodiment of Figure 5, the first transducer 106 is a pressure transducer and the second transducer 110 is a photoelectric transducer. The device 100 is attached to a container door 206 such that the tamper tag 102 is stuck on the outside of the door 206.The first transducer 106 is placed on a bridge located between the door frame 202 and the edge 204 of the door 206. The second transducer 110is housed within a flag stuck on the inner face 208 of the door 206 such that it is exposed to light only when the door 206 is opened.
The pressure transducer is selected from the group consisting of, but not limited to force sensing resistor (FSR), tactile switch, strain gauge, and the like. The photoelectric transducer is selected from the group consisting of, but not limited to LED (Light emitting diode), light dependent resistor (LDR), photo diode, photo transistor, and the like.
In an embodiment, the logical gate 112 is in an open state before use. When the container is loaded and the container door 206 is closed (i.e. locked) after fixing the device 100, the pressure transducer may experience a pressure. When the pressure experienced by the pressure transducer reaches a pre-defined threshold value, and light sensor detects pre-defined darkness, the processing unit 104 closes the logical gate 112. The threshold pressure value for triggering a closing event can be controlled by adding additional electronic components to regulate the output of the pressure transducer or by selecting the pressure transducer accordingly. The state of the device 100 is conveyed by the LED indicator by blinking.
Once the logical gate 112 is closed, the processing unit 104 may be programmed to open the logical gate 112 after a pre-set delay, only when any one of the following conditions are met:
i. when the pressure on the pressure transducer changes by a pre-determined value, wherein the pre-determined value can be controlled by adding additional electronic components to regulate the output of the pressure transducer or by selecting the transducer accordingly;
ii. when a pre-determined amount of light falls on the surface of the photoelectric transducer, wherein the pre-determined amount can be controlled by adding additional electronic components to regulate the output of the photoelectric transducer or by selecting the photoelectric transducer accordingly; and
iii. when there is any attempt of removal of the power supply unit / battery from the tamper status detecting device 100.
Once the logical gate 112 is opened due to either of the above three conditions, the logical gate 112 cannot be closed again. Thus, when the user scans the tamper tag 102 using the reader, the status of the device 100 is shown as “tampered” or “unlocked”.
The pre-set delay of the processing unit 104 ensures that any light falling on the photoelectric transducer before the door 206 is completely closed, does not trigger a false signal to open the logical gate. Once the door 206 is completely secured, the inside of the container should be completely dark.
In an exemplary embodiment, the pressure transducer is placed on the bridge between the frame 202 and the edge 204 of the door 206 and the photoelectric transducer 110 is fixed on the inner side of the door 206. When the door 206 is opened, the bridge of the pressure transducer 106 is squeezed between the frame 202 and the edge 204 of the door 206. This exerts pressure on the pressure transducer 106. When the pressure experienced by the pressure transducer 106 changes by the pre-determined value, the pressure transducer 106 generates a trigger signal for opening the logical gate 112 to the processing unit 104. The state of the device 100 is conveyed by the LED indicator by blinking.
Any attempt to open the door 206 or access the container by drilling a hole through the side of the container will also trigger a tamper event due to light falling on the photoelectric transducer. Similarly, any attempt to open or dislodge the door 206 from the hinges will trigger a tamper event due to change in the pressure experienced by the pressure transducer.
In an embodiment, the auxiliary capacitor 108 is used to store energy generated by the first and second transducers 106, 110 in order to power the processing unit 104 temporarily even after the tamper events have occurred. The auxiliary capacitor 108 can be further used to supply power to the processing unit 104 to facilitate generation of the tamper detection signal in absence of the supply power from the power supply unit 114. In another embodiment, the processing unit 104 can be powered by a battery independent of the transducers 106, 110.
In an embodiment, the tamper tag 102 includes at least one of NFC and RFID antenna to transmit the tamper flag value to the reader. Thus, the device 100 does not need expensive or high-power consuming communication methods like Bluetooth/BLE, Wi-Fi and like that.
In another exemplary embodiment, the default condition of the logical gate 112 is open. A first user/an exporter is attaching the device 100 to the container door 206. At this stage, the logical gate closes due to the pressure experienced by the pressure transducer. The closed state of the logical gate corresponds to a “not-tampered” or “locked” tamper status. The container may be transported to an end user in this condition. Thus, if the end user reads the tamper flag of the tag 102 using the reader, it will show a “not-tampered” or “locked” status. However, if the container is tampered with or opened during transport, without damaging or breaking the device 100, the tamper flag value will change, either due to (i) a change in pressure on the pressure transducer or (ii) detection of light by the photoelectric transducer or (iii) any attempt to remove the power supply from the system to deactivate the device 100. This change in tamper flag value will be reflected as “tampered” or “unlocked” on the reader, when the tag 102 is scanned by the end user. The device 100 is thus able to detect a tamper event in real time. Once the tamper event is detected, it cannot be undone.
In one embodiment, if a counterfeiter tries to remove the battery from the system, in that way counterfeiter deactivates the tamper detection process, the device 100 records this event also as a tamper event. In this case, the auxiliary capacitor 108 provides power supply to the processing unit 104 till event is recorded.
In another embodiment, the processing unit (Microcontroller) 104 keeps tracks of all tamper event from the activation of the tamper tag 102. This is beneficial in the sense that it would allow approximately locating the place of the event. For that, the device 100 includes a real-time clock to keep track of a current date and time and a data logger configured to cooperate with the real-time clock to record a detected tampering event, date and time corresponding to the event, and additional information associated with the tampering event. The additional information may include location of the tamper event. All tampered event data as well as the current time can be recorded in the EEPROM of the central processing unit.
In one exemplary embodiment, the flexible connection between the two parts of the e-Seal may attract possible tampering of the connecting lines. To care of such possibilities, a modification has been incorporated so that any such attempt would indicate the tampered state correctly. In the modified circuit, the placement of detection transistor has been so placed that if the state of the seal is untampered, then attempts to short the lines would report tampered state, and if the state is already tampered then it would continue to remain so. The logic of the implementation has been detailed below. Hence the present disclosure is a significant modification making the seal even more robust.
Consider a scenario where the device (100) is affixed to a shipping container. The pressure transducer (106) monitors the internal pressure, while the photoelectric transducer (110) detects light intrusion. If the container is tampered with, such as by drilling a hole or cutting a section, these transducers detect the changes and send trigger signals to the processing unit (104).
The processing unit (104) processes these signals and sends a tamper detection signal to the logical gate (112). This, in turn, alters the tamper flag value in the tamper tag (102), indicating a tampered state. The LED indicator (118) then blinks to signal this change. If an RFID reader scans the tamper tag (102), the antenna transmits the tampered status, alerting the relevant authorities.
The tamper detection device (100) thus offers a robust, multi-faceted solution for securing containers against unauthorized access, ensuring that any tamper attempts are promptly detected and communicated.
Figure 9A through Figure 9F illustrates flow charts depicting indication of various states of the tamper detection device of Figure 5.
Case 1: Assuming tag is in not tampered state: Shorting of LED signal with Control signal
As shown in Figure 9A, when the tag is in not tampered state, LED signal kept LOW. Therefore, there are two grounded wire and one control signal kept high for biasing of transistor. Shorting of LED signal with Control signal causes the control signal to become low, thereby changing the transistor biasing to cutoff which opens the tamper loop. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered.
Case 2: Assuming tag is in not tampered state: Shorting of Control signal with Ground
As shown in Figure 9B, shorting of Control signal with Ground will cause control signal to become low, thereby changing the transistor biasing to cutoff which opens the tamper loop. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered.
Case 3: Assuming tag is in not tampered state: Shorting of LED signal with Ground
As shown in Figure 9C, shorting of LED signal with Ground has no effect on control signal, which makes the transistor bias as conducting, and closes the tamper loop. The tamper tag will generate a not-tampered notification when read by the RFID reader. In case of an attempt of any unauthorized access of the container such as opening the doors/ taking the door off the hinge or cutting through the container, the light and or the pressure sensor will detect the same and the microcontroller will change the control signal to low state. This will change the transistor biasing to cutoff, and open the tamper loop. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered. Thus, the tag will function as expected.
Case 4: Assuming tag is in not tampered state: Shorting of LED signal and Control signal with Ground
As shown in Figure 9D, control signal becomes low which causes the transistor biasing to change to cutoff, and open the tamper loop. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered.
Case 5: Assuming tag is in tampered state
As shown in Figure 9E, LED signal is kept high for a very short duration in a minute say 0.5 Second, while rest of the time LED signal is kept LOW. If tamper has already been detected (by the microcontroller) then the control signal would change to LOW. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered.
Case 6: Assuming tag is in tampered state: Shorting of LED signal and Control signal
As shown in Figure 9F, Control signal is kept high for very small time say 0.5 second in a minute. This is a configurable setting and the LED can be switched off altogether in the tampered state. This may be done to ensure the tag will go into a tamper state permanently when read by the RFID reader). The transistor will be in conducting state for 0.5 seconds, and kept in open condition for almost 1 minute. If the tag is read while the transistor is in open condition, the tamper tag will generate a tampered notification when read by the RFID reader. The probability of the tag being read while the transistor is in conducting state (0.5 sec) is very low. This is a permanent change and any further notifications of the tag will always show tampered. The LED blinking may be affected.
Case 7: Assuming tag is in tampered state: Shorting of Control signal with Ground
As shown in Figure 9G, the control signal is low therefore the transistor will be in cutoff condition, and will open tamper loop. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered.
Case 8: Assuming tag is in tampered state: Shorting of LED signal with Ground
As shown in Figure 9H, control signal is low therefore the transistor will be in cutoff condition, and will open tamper loop. The tamper tag will generate a tampered notification when read by the RFID reader, and will permanently set the status as tampered. LED blinking may affect.
Case 9: Assuming tag is in tampered state: Shorting of LED signal and Control signal with Ground:
As shown in Figure 9I, control signal is kept high for very small time say 0.5 second in a minute (this is a configurable setting and the LED off altogether in the tampered state). The transistor will be in conducting state for 0.5 seconds, and in open condition for almost 1 minute. The tamper tag will generate a tampered notification when read by the RFID reader. This is a permanent change and any further readouts of the tag will always show tampered. The LED blinking may be affected.
In an embodiment the tamper tag 102 gives information about tampering when scanned with the NFC/UHF reader 120. But if the users are interested in knowing the cause of the tampered event, then there are three ways to do so, first one is destructive access to the processing unit 104, second one is communication using serial port from the processing unit 104, and third one is using i2c/spi supported NFC/UHF RFID IC. In the destructive access the processing unit 104 is removed from the device 100 and EEPROM data is read through a dedicated EEPROM reading device for microcontroller. The processing unit 104 also supports the serial communication, so the tampered data can be sent serially to the serial monitor. In a case where user is interesting in knowing tampered data over NFC only/UHF only, in such situation i2c/spi supported NFC/UHF IC can be used. The added benefit to the user is that the user doesn’t require any other hardware except RFID reader.
In one embodiment, the power supply unit 114 includes a rechargeable or a non-rechargeable battery. In another embodiment, the power supply unit 114 includes an energy harvesting device like piezoelectric transducer, solar panel etc. In this case, power supply like coin cell battery will not be required in the device 100. To store harvested energy, the auxiliary capacitor 108 can be used. The auxiliary capacitor 108 may hold charge for the operation of the tamper status detecting device 100.The reader may be a user device such as a mobile phone, a laptop, a tablet, or a portable or wearable electronic device with scanning and processing capabilities. The user device may be associated with a user having a unique account ID. The account IDs may be pre-assigned to authorized users.
The processing unit 104 may be implemented using one or more microprocessors, microcomputers, micro-controllers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions.
Advantageously, the device 100 is made by using either flexible/printed electronics or hybrid electronics (printed with bonded components) or Printed Circuit Board (PCB). Alternatively, the device 100 may be a hybrid of flexible electronics and PCB to achieve both durability and strength.
The foregoing description of the embodiments has been provided for purposes of illustration and not intended to limit the scope of the present disclosure. Individual components of a particular embodiment are generally not limited to that particular embodiment, but, are interchangeable. Such variations are not to be regarded as a departure from the present disclosure, and all such modifications are considered to be within the scope of the present disclosure.
TECHNICAL ADVANCES AND ECONOMICAL SIGNIFICANCE
The present disclosure described herein above has several technical advantages including, but not limited to, the realization of a tamper detection device that:
· detects a tamper event and in real time;
· indicates the state of the device in real time;
· detects a tamper event even if the device is not damaged/broken during tampering; and
· uses a combination of RFID+NFC communication technology to obviate the need for more expensive technology or elaborate solutions involving high power consumption communication technologies like Bluetooth/BLE, Wi-Fi.
The foregoing description of the specific embodiments so fully reveals the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.
Throughout this specification the word “comprise”, or variations such as “comprises” or “comprising”, will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.
The use of the expression “at least” or “at least one” suggests the use of one or more elements or ingredients or quantities, as the use may be in the embodiment of the disclosure to achieve one or more of the desired objects or results.
Any discussion of documents, acts, materials, devices, articles or the like that has been included in this specification is solely for the purpose of providing a context for the disclosure. It is not to be taken as an admission that any or all of these matters form a part of the prior art base or were common general knowledge in the field relevant to the disclosure as it existed anywhere before the priority date of this application.
While considerable emphasis has been placed herein on the components and component parts of the preferred embodiments, it will be appreciated that many embodiments can be made and that many changes can be made in the preferred embodiments without departing from the principles of the disclosure. These and other changes in the preferred embodiment as well as other embodiments of the disclosure will be apparent to those skilled in the art from the disclosure herein, whereby it is to be distinctly understood that the foregoing descriptive matter is to be interpreted merely as illustrative of the disclosure and not as a limitation. ,CLAIMS:WE CLAIM:
1. A tamper detection device (100), said device (100) configured to be affixed to an operative surface of a container to detect unauthorized intrusion (if any), said device (100) comprising:
• at least one transducer (106, 110) configured to detect a tamper event, and generate a corresponding trigger signal upon detection of said tamper event;
• a power supply unit (114) configured to provide power to at least one component of said device (100);
• a processing unit (104) in communication with said power supply unit (114) and said transducer (106, 110), said processing unit (104) configured to receive said trigger signal from said transducer (106, 110) and process said trigger signal to generate a corresponding tamper detection signal;
• a logical gate (112) configured be in communication with said processing unit to receive said tamper detection signal, said logical gate (112) configured to be operable in an open state and a close state and further configured to change the state relative to said tamper detection signal upon occurrence of unauthorized intrusion event(s) (if any);
• a tamper tag (102) in communication with said logical gate (112), said tamper tag (102) configured to store a tamper flag value and further configured to receive said tamper detection signal from said logical gate (112) to change said tamper flag value, wherein said tamper flag value indicates a tamper status of said device (100);
• a plurality of conductive tracks (122a, 122b, 122c) configured to separately connect said logical gate (112), said tamper tag (102) and at least one of said transducer (106, 110) with said processing unit (104);
• a capacitor (108) configured to be in communication with said processing unit (104) to facilitate power supply in the absence of said power supply unit (114),
wherein said device (100) is characterized such that said logical gate (112) is mounted on the operative terminals of said tamper tag (102), thereby facilitating the generation of said tamper detection signal when at least one of said conductive tracks (122a, 122b, 122c) is short-circuited, thus causing the tamper state of said device (100) to change from “non-tampered” to “tampered” in response to unauthorized intrusion.
2. The device (100) as claimed in claim 1, wherein the unauthorized intrusion event(s) includes:
• receiving said trigger signal from at least one of said transducer (106, 110); and
• detecting a cut-off of power supply from said power supply unit (114).
3. The device (100) as claimed in claim 1, wherein said transducer (106, 110), said power supply unit (114), said capacitor (108) and said processing unit (104) are collectively mounted as a circuit module on an operative inner surface of the container.
4. The device (100) as claimed in claim 3, wherein said tamper tag (102), said logical gate (112) are collectively mounted as an antenna module on an operative outer surface of the container.
5. The device (100) as claimed in claim 4, includes an antenna, configured to be mounted on said antenna module in communication with said tamper tag (102), said antenna is configured to transmit the state of said device (100) to a reader when said tag is scanned by the reader, said antenna is selected from a group consisting of a Radio Frequency Identification (RFID) antenna, a Near Field Communication (NFC) antenna, and an NFC+RFID antenna.
6. The device (100) as claimed in claim 4, wherein said circuit module is in communication with said antenna module by means of said plurality of conductive tracks (122a, 122b, 122c).
7. The device (100) as claimed in claim 1, wherein said plurality of conductive tracks (122a, 122b, 122c) includes a first conductive track (122a), a second conductive track (122b), and a third conductive track (122c), said first conductive track (122a) connects said logical gate (112) with said processing unit (104), said second conductive track (122b) connects said tamper tag (102) with said processing unit (104), and said third conductive track (122c) connects said tamper tag (102) with said processing unit (104).
8. The device (100) as claimed in claim 4, wherein short circuiting of any one of said first conductive track (122a) with said second conductive track (122b), or said first conductive track (122a) with third conductive track (122c) or said second conductive track (122b) with said third conductive track (122c) results in generation of said tamper detection signal to thereby change in the state of device (100) from “non-tampered” to a “Tampered” state.
9. The device (100) as claimed in claim 1, wherein said transducer includes a first transducer (106) and a second transducer (110), said first transducer (106) is configured to sense the change in pressure of the container and typically selected from group of a pressure transducer, said second transducer (110) is configured to sense the presence of light in the container in an operative configuration of said device and typically selected from a group of a photoelectric transducer.
10. The device (100) as claimed in claim 1, includes a LED indicator (118), in communication with said tamper tag, said LED indicator configured to blink at different predetermined interval to indicate the state of said device, selected from the group consisting of arming state, armed state, non-tampered state, and tampered state.
11. The device (100) as claimed in claim 10, wherein said tamper tag (102) includes a set of sensors (116), configured to detect at least one critical parameter corresponding to a change in the state of said logical gate (112) and generate a corresponding sensed signal.
12. The device (100) as claimed in claim 11, wherein said LED indicator (118) is configured to be in communication with said set of sensors, said LED signal is configured to receive said sensed signal from said set of sensors (116) and is further configured to indicate the state of said device (100).

Dated this 26th day of July, 2024

_______________________________
MOHAN RAJKUMAR DEWAN, IN/PA – 25
OF R. K. DEWAN & CO.
AUTHORIZED AGENT OF APPLICANT

TO,
THE CONTROLLER OF PATENTS
THE PATENT OFFICE, AT MUMBAI