Description:TECHNICAL FIELD
The present disclosure relates to angular position measurement. More particularly, the present disclosure relates to a direct-digital interfacing circuit for angle measurement and a method thereof.
BACKGROUND
Among different available angle sensors, angle sensors with sine-cosine characteristics are more efficient and are thus favored for both the static and dynamic angular position sensing as it offers continuous angle measurement from 0 degree to 360 degree, unlike a basic resistive potentiometer-based angle sensor. The Hall-effect based encoders, resolvers, Giant Magnetoresistance (GMR) and Tunnel Magnetoresistance (TMR) based angle sensors showcase sine-cosine natured response. Such a non-linear natured response demands efficient interfacing circuit for linearization as well as accurate angle estimation.
The simplest approach to the design and development of linearizing circuits for sine-cosine natured angle sensor requires Analog-to-Digital Converter(s) (ADC), Digital-to-Analog Converter (DAC), a digital processor or a Look-Up Table (LUT) where the angle can be easily estimated by inverse tangent operation on digital equivalents of sensor outputs.
However, this approach has several constraints such as the ADCs must be bipolar, resolution of ADC must be sufficiently high, processor must be accurate and faster, and so on. An alternate approach to realize a linear angle measurement system based on TMR angle sensor may require non-standard weighted resistors or supplementary circuits for obtaining full-circle linear output. Furthermore, presently, the existing interfacing circuits have large component-count, use costly analog multipliers or instrumentation amplifiers for linearization and/or for operation, or require saw-tooth natured or quadrature shifted sinusoids for linearization. Moreover, in some cases, the angle measurement is observed to be dependent on the variations in the amplitude of sensor-excitation voltage or phase-imbalance of the quadrature oscillator employed. For circuits based on direct-digital measurement techniques, quadrature-shifted AC excitation is used, providing excellent immunity towards the phase imbalance of quadrature-oscillator outputs and sensor parasitic capacitances, but its performance has not been evaluated for dynamic inputs. Moreover, the available dual-slope based digitizer possesses large conversion time. Few available angle sensors and associated linearizing circuits incorporate multiple sensors to improve the inherent sensitivity of the system. Furthermore, some circuits are quite complex in its architecture and render piecewise linear analog output for full-circle range.
Therefore, there is a need for a simple, easy-to-implement system and a method, providing a technical solution towards the challenges mentioned hereinabove for rotation angle measurement from 0 degree to 360 degree with enhanced accuracy, reduced measurement time, suitable for slow speed dynamic input tracking and harsh environmental conditions for industrial applications.
SUMMARY
In an aspect of the present disclosure, a direct-digital interfacing circuit is disclosed. The direct-digital interfacing circuit includes a first switch configured to enable selection of one of, sine and cosine voltages received from a half bridge Tunnel Magnetoresistance (TMR) angle sensor that is magnetically coupled to a rotating shaft. Further, the direct-digital interfacing circuit includes a non-inverting amplifier that is coupled to the first switch. The non-inverting amplifier is configured to generate a first output signal. The first output signal is one of, first and second amplified voltages corresponding to the sine and cosine voltages based on the selection of the first switch. Furthermore, the direct-digital interfacing circuit includes a third switch configured to enable selection of, one of, first and second Direct Current (DC) voltages (+VDC and -VDC). Furthermore, the direct-digital interfacing circuit includes a second switch that is coupled to the third switch, and configured to enable selection of one of, a second output of the third switch and the first output signal. The second output is dependent on the selection of the third switch. Furthermore, the direct-digital interfacing circuit includes an integrator (INT) circuit that is coupled to the second switch. The INT circuit is configured to (i) execute a dual slope operation based on the selection of the second switch and the third switch and (ii) generate an input voltage. Furthermore, the direct-digital interfacing circuit includes a comparator that is coupled to the INT circuit. The comparator is configured to generate a comparator output based on the input voltage. Furthermore, the direct-digital interfacing circuit includes a control and timing unit (CTU) that is coupled to the comparator and the first through third switches such that the CTU controls the first through third switches to determine (i) first and second de-integration times and (ii) an output angle based on the first and second de-integration times.
In some aspects, the non-inverting amplifier includes a first operational amplifier, a first resistance, and a second resistance. The first operational amplifier is configured to generate the first and second amplified voltages using the first and second voltages, respectively.
In some aspects, the integrator circuit includes a second operational amplifier, a first capacitance, a third resistance, and a fourth resistance such that the third resistance is significantly smaller than the fourth resistance. The second operational amplifier is configured to execute the dual-slope operation, based on the selection of the second switch and the third switch to generate the input voltage for the comparator circuit.
In some aspects, the comparator includes a third operational amplifier configured to generate the comparator output based on the input voltage. The comparator output is a one-bit binary equivalent pulse to the input voltage.
In some aspects, the direct-digital interfacing circuit further includes third and fourth resistances coupled to the INT circuit such that (i) an integration phase of the dual-slope operation is executed for a predefined time duration and (ii) a de-integration phase of the dual-slope operation is executed on an expiration of the integration phase. A time duration of de-integration phase is decided by the voltage applied during the integration phase, which in turn depends on the shaft angle, ?.
In some aspects, the third resistance is smaller than the fourth resistance.
In another aspect of the present disclosure, a method is disclosed. The method includes enabling, by way of a first switch, a selection of one of, sine and cosine voltages received from a half bridge Tunnel Magnetoresistance angle sensor that is magnetically coupled to a rotating shaft. The method further includes generating, by way of a non-inverting amplifier, a first output signal. The first output signal is one of, first and second amplified voltages based on the selection of the first switch (S1); enabling, by way of a third switch (S3), a selection of, one of, first and second Direct Current (DC) voltages (+VDC and -VDC). The method further includes enabling, by way of a second switch, a selection of one of, a second output of the third switch and the first output signal. The second output is dependent on the selection of the third switch. The method further includes executing, by way of an integrator (INT) circuit, a dual slope operation based on the selection of the second switch and the third switch and generate an input voltage. The method further includes generating, by way of a comparator that is coupled to the INT circuit, a comparator output based on the input voltage. The method further includes controlling, by way of a control and timing unit (CTU) that is coupled to the comparator and the first through third switches, the first through third switches such that the CTU determines (i) first and second de-integration times and (ii) an output angle based on the first and second de-integration times.
BRIEF DESCRIPTION OF DRAWINGS:
The above and still further features and advantages of aspects of the present disclosure becomes apparent upon consideration of the following detailed description of aspects thereof, especially when taken in conjunction with the accompanying drawings, and wherein:
FIG. 1 illustrates a schematic block diagram of a system to measure an angle of a rotating shaft using a half-bridge based Tunneling Magneto Resistance (TMR) angle sensor, in accordance with an exemplary aspect of the present disclosure;
FIG. 2 illustrates a schematic block diagram of a direct-digital interfacing circuit of the system of FIG. 1, in accordance with an exemplary aspect of the present disclosure; and
FIG. 3 illustrates a flow chart of a method for measuring an angle of a rotating shaft using a Half-Bridge based TMR angle sensor, in accordance with an exemplary aspect of the present disclosure.
To facilitate understanding, reference numerals have been used, where possible, to designate elements common to the figures.
DETAILED DESCRIPTION OF DRAWINGS:
Various aspects of the present disclosure provide a system, an apparatus, and a method for rotational shaft angle measurement using half-bridge based Tunnel Magneto Resistance (TMR) angle sensor. The following description provides specific details of certain aspects of the disclosure illustrated in the drawings to provide a thorough understanding of those aspects. It should be recognized, however, that the present disclosure can be reflected in additional aspects and the disclosure may be practiced without some of the details in the following description.
The various aspects including the example aspects are now described more fully with reference to the accompanying drawings, in which the various aspects of the disclosure are shown. The disclosure may, however, be embodied in different forms and should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure is thorough and complete, and fully conveys the scope of the disclosure to those skilled in the art. In the drawings, the sizes of components may be exaggerated for clarity.
It is understood that when an element is referred to as being “on,” “connected to,” or “coupled to” another element, it can be directly on, connected to, or coupled to the other element or intervening elements that may be present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The subject matter of example aspects, as disclosed herein, is described with specificity to meet statutory requirements. However, the description itself is not intended to limit the scope of this patent. Rather, the inventor/inventors have contemplated that the claimed subject matter might also be embodied in other ways, to include different features or combinations of features like the ones described in this document, in conjunction with other technologies. Generally, the various aspects including the example aspects relate to the system, and the method for rotating shaft angle measurement using half-bridge based TMR angle sensor.
As mentioned, there is a need for a system, an apparatus, and a method for accurate and precise measurement of angle of a rotating shaft using TMR sensor that efficiently utilize the available resources and results in least amount of irrelevant data captured by the system to cover the desired area. The present aspects, therefore: provides a system, a direct-digital interfacing circuit, and a method that provides an improvised technical solution that overcomes the aforementioned problems.
The aspects herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting aspects that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted to not unnecessarily obscure the aspects herein. The examples used herein are intended merely to facilitate an understanding of ways in which the aspects herein may be practiced and to further enable those of skill in the art to practice the aspects herein. Accordingly, the examples should not be construed as limiting the scope of the aspects herein.
FIG. 1 illustrates a schematic block diagram of a system 100 to measure an angle of a rotating shaft 108 using a half-bridge based TMR angle sensor 110, in accordance with an exemplary aspect of the present disclosure. The system 100 may include a magnetic unit 102, the Half-Bridge based TMR angle sensor 110, and a direct-digital interfacing circuit 112.
In some aspects of the present disclosure, the magnetic unit 102 may be configured to generate one of, a Direct Current (DC) signal (i.e., for a static input), an Alternate Current (AC) signal (i.e., for a dynamic input) based on a rotation of the rotating shaft 108. In some aspects of the present disclosure, the magnetic unit 102 may include a permanent magnet 106 and the rotating shaft 108.
Examples of the permanent magnet 106 may include but not limited to, rare earth magnets, Alnico magnets, Samarium Cobalt based magnets, ceramic magnets, magnets based on custom magnetic engineering and the like. Aspects of the present disclosure are intended to include or otherwise cover any type of the permanent magnet 106 including known without deviating from the scope of the present disclosure. The rotational shaft 108 may enable a rotation of the permanent magnet 106 to enable a generation (or variation) of a magnetic field that may lead to a generation of sine and cosine natured voltage signals based on the change in the direction of magnetic field due to a rotational movement of the permanent magnet 106 attached with the rotational shaft 108 of the magnetic unit 102.
The rotating shaft 108 may include one or more elongated, rod-shaped members that may facilitate the rotation of the permanent magnet 106 about a longitudinal axis to transmit a generated torque to the coupled permanent magnet 106. In some aspects of the present disclosure, the rotating shaft 108 may be configured to be rotated by a rotational angle ‘?’ with respect to a vertical axis (not shown) of the rotating shaft 108 which may further generate and transmit a torque to the adjacent permanent magnet 106 such that the transmission of torque may result in the rotation of the permanent magnet 106. In some aspects of the present disclosure, the rotating shaft 108 may be one of, straight shafts, cranked shafts, flexible shafts, and articulated shafts of circular cross-section and can be either solid or hollow, and the like. Examples of the rotating shaft 108 may include, but is not limited to, transmission shafts, machine shafts, axle shafts, spindle type of shafts, and the like. Aspects of the present disclosure are intended to include or otherwise cover any type of the rotating shaft 108 including known without deviating from the scope of the present disclosure. In some aspects of the present disclosure, the magnetic unit 102 may be configured to generate a magnetic signal that may depict a variation in magnetic field based on a rotation of the permanent magnet 106 dependent on the torque provided by the rotating shaft 108.
The Half-Bridge based TMR angle sensor 110 (hereinafter interchangeably referred to and designated as “angle sensor 110”) may be magnetically coupled to the magnetic unit 102 and may be configured to receive the magnetic signal from the magnetic unit 102. The angle sensor 110 may include suitable circuitry that can be configured to perform one or more operations related to transformation of the received magnetic signal into another form. For example, the angle sensor 110 may be configured to transform the magnetic signal received from the magnetic unit 102 into either of, one or more voltage signals, one or more current signals, or a combination thereof. In some aspects of the present disclosure, the angle sensor 110 may be powered from a differential excitation. The angle sensor 110 may further be configured to generate sine and cosine voltages (V1 and V2) based on the magnetic signal that may depict an absolute angular position of the rotating shaft 108. The sine and cosine voltages (V1 and V2) (hereinafter interchangeably referred to and designated as “first and second voltages”) may follow sine and cosine relationship with a shaft angle ‘?’ of the rotating shaft 108, respectively, and therefore can be said to have a phase difference of 90 degrees with each other. In some aspects of the present disclosure, the angle sensor 110 may include first through fourth variable resistances (shown later in FIG. 2 as RV1-RV4) in a Wheatstone Bridge arrangement. The first variable resistance (shown later in FIG. 2 as RV1) may be connected between first and second half bridge (HB) nodes (shown later in FIG. 2 as 202 and 204, respectively), the second variable resistance (shown later in FIG. 2 as RV2) may be connected between the second HB node 204 and a third HB node (shown later in FIG. 2 as 206), the third variable resistance (shown later in FIG. 2 as RV3) may be connected between fifth and sixth HB nodes (shown later in FIG. 2 as 210 and 212, respectively), and the fourth variable resistance (shown later in FIG. 2 as RV4) may be connected between a fourth HB nodes (shown later in FIG. 2 as 208) and the fifth HB node (shown later in FIG. 2 as 210).
The First and sixth HB nodes (202 and 212) may be applied with a first Direct Current (DC) voltage (+VDC). The third and fourth HB nodes (206 and 208) may be applied with a third DC voltage (-VP). In some aspects of the present disclosure, the angle sensor 110 may be configured to provide a suitable differential DC excitation such that the generated first and second voltages (V1 and V2) may be offset free voltages. In some aspects of the present disclosure, the angle sensor 110 may generate the first and second voltages (V1 and V2) based on the first and third DC voltages (+VDC and -VP) by applying one or more principles of Wheatstone Bridge. The first and second voltages may be obtained from the second and the fifth HB nodes 204 and 210, respectively.
The direct digital interfacing circuit 112 (hereinafter interchangeably referred to and designated as ‘interface circuit 112’) may be configured to determine an output angle (DOUT) based on the first and second voltages (V1 and V2), that may be equal to the shaft angle ‘?’ of the rotating shaft 108.
The interface circuit 112 may include a first switch (S1), a non-inverting amplifier circuit 114 (hereinafter interchangeably referred to and designated as ‘the NIA circuit 114’), a third switch (S3), and an enhanced dual-slope based digitizer 121. Specifically, the enhanced dual-slope based digitizer 121 may include third and fourth resistances (R3 and R4), a second switch (S2), an integrator circuit 116 (hereinafter interchangeably referred to and designated as ‘the INT circuit 116’), a comparator circuit 118 (hereinafter interchangeably referred to and designated as ‘the CMP circuit 118’), and a Control and Timing Unit 120 (hereinafter interchangeably referred to and designated as ‘the CTU 120’).
As illustrated, the NIA circuit 114 may be coupled to the first switch (S1), the third switch (S3) may be coupled to the second switch (S2), the INT circuit 116 may be coupled to the second switch (S2), the CMP circuit 118 may be coupled to the INT circuit 116, and the CTU 120 may be coupled to the CMP circuit 118 and the first through third switches S1-S3.
The first switch (S1) may be configured to enable selection of one of, the sine and cosine voltages (V1 and V2) received from the angle sensor 110 that may be magnetically coupled to the rotating shaft 108 of the magnetic unit 102. The non-inverting amplifier 114 may be configured to generate a first output signal. In one aspect of the present disclosure, the first output signal may be a first amplified voltage when the sine voltage (V1) is selected by way of the first switch (S1). In another aspect of the present disclosure, the first output signal may be a second amplified voltage when the cosine voltage (V2) is selected by way of the first switch (S1). Specifically, the non-inverting amplifier 114 may be configured to generate the first output signal (i.e., the first and second amplified voltages) depending on the selection of the sine and cosine voltages, respectively, by way of the first switch (S1).
The INT circuit 116 may be coupled to the second switch (S2). The INT circuit 116 may be configured to generate an integrated signal (hereinafter interchangeably referred to and designated as “the input voltage (Vin)”) associated with one of, the first output signal and a second output signal (i.e., one of, a first DC voltage (+VDC) and a second DC voltage (-VDC)) received through the third switch (S3). In an aspect of the present disclosure, the INT circuit 116 may be configured to generate the integrated signal (i.e., a first integrated signal) with respect to time of the first output signal when the first output signal is selected by way of the second switch (S2). In another aspect of the present disclosure, the INT circuit 116 may be configured to generate the integrated signal (i.e., a second integrated signal) with respect to time when one of, the first DC voltage (+VDC) and the second DC voltage (-VDC) coming through the third switch (S3) is selected by way of the second switch (S2).
The third switch (S3) may be configured to select one of, the first DC voltage (+VDC) and the second DC voltage (-VDC). The third switch (S3) may be configured to enable selection of one of, the second output signal of the third switch (S3) and the first output signal at a second INT node. The second output signal may be dependent on the selection of the third switch (S3).
The comparator 118 may be coupled to the INT circuit 116. The comparator 118 may be configured to generate a pulse signal based on the input voltage (Vin) received from the INT circuit 116. Specifically, the input voltage (Vin) may be a ramp signal such that when the input voltage (Vin) is less than or equal to 0 V, the comparator 118 generates a comparator output i.e., a logic “0” output (shown later in FIG. 2 as ‘DP’) and when the input voltage (Vin) is greater than 0 V, the comparator 118 generates the comparator output i.e., a logic “1” output (shown later in FIG. 2 as ‘DP’). Specifically, the comparator output (DP) is a one-bit binary equivalent pulse to the input voltage (Vin).
The CTU 120 may be coupled to the comparator 118 and the first through third switches (S1-S3). The CTU 120 may include suitable circuitry that may enable the CTU 120 to perform one or more operations. For example, the CTU 120 may be configured to control the first through third switches (S1-S3) to determine first and second de-integration times (T1 and T2) based on the comparator output (DP). The CTU 120 may further be configured to determine an output angle (shown later in FIG. 2 as ‘DOUT’) based on the first and second de-integration times (T1 and T2).
FIG. 2 illustrates a schematic block diagram of the direct-digital interfacing circuit 112 of the system 100 of FIG. 1, in accordance with an exemplary aspect of the present disclosure. The direct-digital interfacing circuit 112 may be coupled with the angle sensor 110 and may be configured to receive the first and second voltages (V1 and V2) from the angle sensor 110. The direct-digital interfacing circuit 112 may further be configured to determine the output angle (DOUT) (that may be equal to the rotational angle ‘?’ of the rotating shaft 108) based on the first and second voltages (V1 and V2) received from the angle sensor 110. The interface circuit 112 may include the first through the NIA circuit 114, and the enhanced dual-slope based digitizer 121. Further, the enhanced dual-slope based digitizer 121 may include the first through third switches (S2-S3), the third and fourth resistances (R3 and R4), the INT circuit 116, the CMP circuit 118, and the CTU 120.
The non-inverting amplifier circuit 114 may include a first operational amplifier (OP1), a first resistance (R1), and a second resistance (R2). The first operational amplifier (OP1) may include suitable circuitry that may enable the first operational amplifier (OP1) to perform one or more operations. For example, the first operational amplifier (OP1) may be configured to generate the first and second amplified voltage signals based on the first and second voltages (V1 and V2), respectively. In some aspects of the present disclosure, the non-inverting amplifier circuit 114, by way of the first operational amplifier (OP1) may be configured to generate the first and second amplified voltage signals with a voltage gain of 1+R_2/R_1 with respect to the first and second voltages (V1 and V2), respectively. A positive input terminal of the first operational amplifier (OP1) may be coupled to a first non-inverting amplifier (NIA) node 214 of the first operational amplifier (OP1). The first operational amplifier (OP1) may be configured to receive one of, the first and second voltages (V1 and V2) through the first switch (S1) that may be connected to the first NIA node 214. A negative input terminal of the first operational amplifier (OP1) may be connected to a second NIA node 216 such that the second NIA node 216 may connect a first resistance (R1) and a second resistance (R2). The first resistance (R1) may be connected between a ground node (GND) and the second NIA node 216. The second resistance (R2) may be connected between the second NIA node 216 and a third NIA node 218.
In some aspects of the present disclosure, the NIA circuit 114 may be configured to receive the first and second voltages (V1 and V2) from the angle sensor 110 through the positive input terminal of the first operational amplifier (OP1) connected with the first NIA node 214 and may generate the first and second amplified voltage signals respectively with a voltage gain of 1+R_2/R_1 through the third NIA node 218.
Upon generation of the first and second amplified voltage signals, the INT circuit 116 may receive one of the first and second amplified voltage signals from the NIA circuit 114. The INT circuit 116 may include a second operational amplifier (OP2), a first capacitance (C1). The second switch (S2) may be coupled with the NIA circuit 114 and the third switch (S3) by way of the third and fourth resistances (R3 and R4), respectively. In some aspects of the present disclosure, the third resistance (R3) may be significantly smaller than the fourth resistance (R4). A positive input terminal of the second operational amplifier (OP2) may be coupled to a ground node (GND). A negative input terminal of the second operational amplifier (OP2) may be coupled to a fourth integrator (INT) node 226 of the second operational amplifier (OP2). An output terminal of the second operational amplifier (OP2) may be connected to a fifth INT node 228. The fourth INT node 226 may be configured to receive one of the signals from a second INT node 222 or the signals from a third INT node 224. The second INT node 222 may be configured to receive the first and the second amplified voltage signals from the third NIA node 218 of NIA circuit 114. The third resistance (R3) may be configured to connect the third NIA node 218 and the second INT node 222. The third INT node 224 may be configured to receive one of, the first and second DC voltages (+VDC and -VDC) from a first INT node 220 through the third switch (S3), reduced by a factor of the fourth resistance (R4). The fourth resistance (R4) may be configured to connect the first INT node 220 and the third INT node 224. The first capacitor (C1) may be connected to the fourth INT node 226 and the fifth INT node 228. The INT circuit 116 may be configured to receive the first and second amplified voltage signals from the NIA circuit 114.
In some aspects of the present disclosure, the INT circuit 116, by way of the second amplifier (OP2) may be configured to execute an integration phase, based on the selection of the third switch (S3) and/or a third output of the second switch (S2) to generate the first and second integrated versions of the first output signal and the third output of the second switch (S2), respectively. Specifically, the INT circuit 116 may be configured to generate the integrated signal (denoted as an input voltage (Vin) for the comparator circuit 118) associated with one of, the first output signal and an output (i.e., one of, the first DC voltage (+VDC) and the second DC voltage (-VDC)) of the second switch (S2).
The comparator circuit 118 may include a third operational amplifier (OP3). The comparator circuit 118, by way of the third operational amplifier (OP3), may be configured to convert the input voltage (Vin) into the comparator output (DP). In some aspects of the present disclosure, comparator output (DP) is a one-bit binary equivalent pulse to the input voltage (Vin) for the comparator circuit 118. The comparator circuit 118, by way of the third operational amplifier (OP3), may be configured to generate the comparator output (DP) from the input voltage (Vin) that is dependent on the integrated signal received from the INT circuit 116. Specifically, the integrated signal may be a ramp signal such that when the integrated signal ramps in a negative direction and when it goes below 0 V, the comparator 118 generates the comparator output (DP) i.e., a logic “0” output and when the integrated signal ramps in a positive direction and when it goes above 0 V, the comparator 118 generates the comparator output (DP) i.e., a logic “1” output. The CMP circuit 118 may further be configured to determine the comparator output (DP) where a positive input terminal of the third operational amplifier (OP3) may be connected to the ground (GND) node. A negative input terminal of the third operational amplifier (OP3) may be connected to the fifth INT node 228. An output terminal of the third operational amplifier (OP3) may be connected to a first comparator (CMP) node 230 to receive the information about the comparator output (DP).
The CTU 120 may be configured to control the first through third switches (S1-S3) to determine the first and second de-integration times (T1 and T2) based on the comparator output (DP). Specifically, the CTU 120 may be configured to generate first through third control signals (DC1- DC3), to control the first through third switches, respectively. Examples of the CTU 120 may include, but are not limited to, an Application-Specific Integrated Circuit (ASIC) processor, a Reduced Instruction Set Computing (RISC) processor, a Complex Instruction Set Computing (CISC) processor, a Field-Programmable Gate Array (FPGA), a Programmable Logic Control unit (PLC), and the like. Aspects of the present disclosure are intended to include or otherwise cover any type of the CTU 120 including known, related art, and/or later developed technologies.
In some aspects of the present disclosure, the CTU 120 may be configured to facilitate the INT circuit 116 to execute an integration phase and a de-integration phase (i.e., a dual-slope operation with a faster integration phase and relatively slower de-integration phase). In an exemplary scenario, the CTU 120 may be configured to generate a first control signal (DC1) such that the first control signal (DC1) enables the first switch (S1) to select the cosine voltage (Vcos). Further, the CTU 120 may be configured to generate a second control signal (DC2) such that the second control signal (DC2) enables the second switch (S2) to select the input voltage (Vin). As the INT circuit 116 receives the input voltage (Vin) through the third resistance (R3), the INT circuit 116 executes the integration phase for a predefined time duration. Further, the CTU 120 may be configured to generate a third control signal (DC3) at an expiration of the predefined time duration. In some aspects of the present disclosure, the CTU 120 may start an internal timer (T) to determine the expiration of the predefined time duration. The third control signal (DC3) may enable the third switch (S3) to select one of, the first and second DC voltages (-VDC and +VDC) to enable the INT circuit 116 to execute the de-integration phase. A time duration of de-integration phase is decided by the voltage applied during the integration phase, which in turn depends on the shaft angle, ?. Specifically, the selection of the first and second DC voltages (-VDC and +VDC) by way of the third switch (S3) may depend on the comparator output (DP). For example, when the comparator output (DP) is at a logic “0”, the third control signal (DC3) enables the third switch (S3) to select the first DC voltage (-VDC). On the other hand, when the comparator output (DP) is at a logic “1”, the third control signal (DC3) enables the third switch (S3) to select the second DC voltage (+VDC). In some aspects of the present disclosure, the de-integration phase may continue till an output of the INT circuit 116 crosses 0V (or changes the status of the comparator output (DP) from 1 to 0, or vice versa). The CTU 120 may further be configured to monitor the status of the comparator output (DP) continuously.
The CTU 120 may be further configured to determine the first and second de-integration times (T1 and T2) and the output angle (DOUT) based on the first and second de-integration times (T1 and T2).
In some aspects of the present disclosure, the CTU 120 may be configured to determine the first and second de-integration times (T1 and T2) based on the expressions presented hereinbelow:
T_1=((R_4+R_ON2+R_ON3 ))/((R_1+R_ON2 ) )×V_M G2k|cos?? |.T_I, for ??(0^o,360^o ) and
T_2= ((R_4+R_ON2+R_ON3 ))/((R_1+R_ON2 ) )×V_M G×2k|sin?? |.T_I for ??(0^o,360^o ) where, R_ON2 and R_ON3 represent ON-resistances of the second and third switches (S2 and S3), respectively, k represents sensor constant, G represents a gain of the NIA circuit 114, TI represents the integration time, VM represents the peak value of first and second voltage signals, and ? represents the rotation angle of the shaft.
In some aspects of the present disclosure, based on the first and second de-integration time periods (T1 and T2), the CTU 120 may be configured to compute a variable x using the mathematical expression presented hereinbelow:
x=(T_1-T_2)/(T_2+T_1 )=(|cos?? |-|sin?? |)/(|cos?? |+|sin?? |) for ??(0^o,360^o ).
The CTU 120 may further perform a linearization transformation on the x (which is independent of switch ON resistances) to generate the output angle (DOUT). Thus, the output angle (DOUT) is also independent of all the variables related to the circuit components.
The CTU 120 may be configured to determine the output angle (DOUT) using the equation:
D_OUT=[x×45^o-x(|x|-1)(14.02+3.8×|x|)]×a+K˜? for ??(0^o,360^o ), where, a represents a constant that depends on the quadrant of the input shaft angle, ? and K represents intercept.
FIG. 3 illustrates a flow chart of a method 300 for measuring the angle ‘?' of a rotating shaft 108 using the Half-Bridge based TMR angle sensor 110, in accordance with an exemplary aspect of the present disclosure.
At step 302, the direct-digital interfacing circuit 112, by way of a first switch (S1), may enable the selection of one of, the first and second voltages (V1 and V2) from the half bridge Tunnel Magnetoresistance angle sensor 110. The half bridge Tunnel Magnetoresistance angle sensor 110 magnetically may be coupled to the rotating shaft (108).
At step 304, the direct-digital interfacing circuit 112, by way of the NIA circuit 114, may generate the first output signal, that may be one of, first and second amplified voltages based on the selection of the first switch (S1), respectively. In some aspects of the present disclosure, the NIA circuit 114 may amplify the first and second voltages (V1 and V2) to generate the first and second amplified voltage signals, respectively.
At step 306, the direct-digital interfacing circuit 104, by way of the control and timing unit 120 may control the second and third switches (S2 and S3) to enable the INT circuit 116 to execute the dual slope operation (i.e., the integration and de-integration phase).
In some aspects of the present disclosure, the direct-digital interfacing circuit 104, by way of the CTU 120, may enable the INT circuit 116 to execute the integration phase and the de-integration phase (i.e., the dual-slope operation with faster integration phase and relatively slower de-integration phase).
At step 308, the CTU 120 may determine the first and second de-integration times (T1 and T2) of the dual slope operation and further the output angle (DOUT) based on the first and second de-integration times (T1 and T2).
At step 310, the CTU 120, may compute a switch independent variable (x) based on the first and second de-integration times (T1 and T2) using the mathematical expression x=(T_1-T_2)/(T_2+T_1 )=(|cos?? |-|sin?? |)/(|cos?? |+|sin?? |) for ??(0^o,360^o ).
At step 312, the CTU 120 may perform linearization transformation on the switch independent variable (x) to determine the output angle (DOUT) which is independent of all the variable related to the circuit components using the following mathematical expression:
D_OUT=[x×45^o-x(|x|-1)(14.02+3.8×|x|)]×a+K˜? for ??(0^o,360^o ), where, a represents a constant that depends on the quadrant of the input shaft angle, ? and K represents intercept.
As discussed earlier, there is a need for a system that is simple and easy to implement, and a method that provides a technical solution for accurate and precise measurement of angular movement of a rotating shaft with reduced low latency. The system 100, without using any explicit analog to digital converter (ADC), by way of the direct-digital interfacing circuit 112, utilizes differential excitation scheme to eliminate offset voltage in the sensor outputs. Moreover, the system 100 provides precise and accurate measurements of rotating shaft angle movement from 0 to 360 degree applying a simple direct current (DC) excitation for the angle sensor 110 with reduced measurement time. Furthermore, the system 100 is suitable for slow speed dynamic input tracking and harsh environmental conditions for industrial, automobile, military, and aerospace applications where sensor outputs are not influenced by sensor parasitic capacitances. The direct-digital interfacing circuit 112 provides smaller integration time, and thus results in reduction in an overall time for measurement of the rotation angle ‘?'. The direct-digital interfacing circuit 112 further provides a simple calibration method to minimize the measurement error due to a mismatch in a nominal resistance of the angle sensor 110 and a maximal change in the resistance.
The foregoing discussion of the present disclosure has been presented for purposes of illustration and description. It is not intended to limit the present disclosure to the form or forms disclosed herein. In the foregoing Detailed Description, for example, various features of the present disclosure are grouped together in one or more aspects, configurations, or aspects for the purpose of streamlining the disclosure. The features of the aspects, configurations, or aspects may be combined in alternate aspects, configurations, or aspects other than those discussed above. This method of disclosure is not to be interpreted as reflecting an intention the present disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed aspect, configuration, or aspect. Thus, the following claims are hereby incorporated into this Detailed Description, with each claim standing on its own as a separate aspect of the present disclosure.
Moreover, though the description of the present disclosure has included description of one or more aspects, configurations, or aspects and certain variations and modifications, other variations, combinations, and modifications are within the scope of the present disclosure, e.g., as may be within the skill and knowledge of those in the art, after understanding the present disclosure. It is intended to obtain rights which include alternative aspects, configurations, or aspects to the extent permitted, including alternate, interchangeable and/or equivalent structures, functions, ranges, or steps to those claimed, whether or not such alternate, interchangeable and/or equivalent structures, functions, ranges or steps are disclosed herein, and without intending to publicly dedicate any patentable subject matter.
As one skilled in the art will appreciate, the system 100 includes a number of functional blocks in the form of a number of units and/or engines. The functionality of each unit and/or engine goes beyond merely finding one or more computer algorithms to carry out one or more procedures and/or methods in the form of a predefined sequential manner, rather each engine explores adding up and/or obtaining one or more objectives contributing to an overall functionality of the system 100. Each unit and/or engine may not be limited to an algorithmic and/or coded form, rather may be implemented, by way of one or more hardware elements operating together to achieve one or more objectives contributing to the overall functionality of the system 100. Further, as it will be readily apparent to those skilled in the art, all the steps, methods and/or procedures of the system 100 are generic and procedural in nature and are not specific and sequential.
Certain terms are used throughout the following description and claims to refer to features or components. As one skilled in the art will appreciate, different people may refer to the same feature or component by different names. This document does not intend to distinguish between components or features that differ in name but not structure or function. While various aspects of the present disclosure have been illustrated and described, it will be clear that the present disclosure is not limited to these aspects only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present disclosure, as described in the claims. , Claims:1. A direct-digital interfacing circuit (112) comprising:
a first switch (S1) configured to enable selection of one of, sine and cosine voltages (V1 and V2) received from a half bridge Tunnel Magnetoresistance (TMR) angle sensor (110) that is magnetically coupled to a rotating shaft (108);
a non-inverting amplifier (114) that is coupled to the first switch (S1), and configured to generate a first output signal, wherein the first output signal is one of, first and second amplified voltages corresponding to the sine and cosine voltages (V1 and V2) based on the selection of the first switch (S1);
a third switch (S3) configured to enable selection of, one of, first and second Direct Current (DC) voltages (+VDC and -VDC);
a second switch (S2) that is coupled to the third switch (S3), and configured to enable selection of one of, a second output of the third switch (S3) and the first output signal, wherein the second output is dependent on the selection of the third switch (S3);
an integrator (INT) circuit (116) that is coupled to the second switch (S2), and configured to (i) execute a dual slope operation based on the selection of the second switch (S2) and the third switch (S3), and generate an input voltage (Vin);
a comparator (118) that is coupled to the INT circuit (116), and configured to generate a comparator output (DP) based on the input voltage (Vin); and
a control and timing unit (CTU) (120) that is coupled to the comparator (118) and the first through third switches (S1-S3) such that the CTU (120) controls the first through third switches (S1-S3) to determine (i) first and second de-integration times (T1 and T2) and (ii) an output angle (DOUT) based on the first and second de-integration times (T1 and T2).
2. The direct-digital interfacing circuit (112) as claimed in claim 1, wherein the non-inverting amplifier (114) comprising a first operational amplifier (OP1), a first resistance (R1), and a second resistance (R2), wherein the first operational amplifier (OP1) is configured to generate the first and second amplified voltages using the first and second voltages (V1 and V2), respectively.
3. The direct-digital interfacing circuit (112) as claimed in claim 1, wherein the integrator circuit (116) comprising a second operational amplifier (OP2), a first capacitance (C1), a third resistance (R3), and a fourth resistance (R4) such that the third resistance (R3) is significantly smaller than the fourth resistance (R4), wherein the second operational amplifier (OP2) is configured to execute the dual-slope operation, based on the selection of the second switch (S2) and the third switch (S3) to generate the input voltage (Vin) for the comparator circuit (118).
4. The direct-digital interfacing circuit (112) as claimed in claim 1, wherein the comparator (118) comprising a third operational amplifier (OP3) configured to generate the comparator output (DP) based on the input voltage (Vin), wherein the comparator output (DP) is a one-bit binary equivalent pulse to the input voltage (Vin).
5. The direct-digital interfacing circuit (112) as claimed in claim 1, further comprising third and fourth resistances (R3, R4) coupled to the INT circuit (116) such that (i) an integration phase of the dual-slope operation is executed for a predefined time duration and (ii) a de-integration phase of the dual-slope operation is executed on an expiration of the predefined time duration.
6. The direct-digital interfacing circuit (112) as claimed in claim 5, wherein the third resistance (R3) is smaller than the fourth resistance (R4).
7. A method (300) comprising:
enabling, by way of a first switch (S1), a selection of one of, sine and cosine voltages (V1 and V2) received from a half bridge Tunnel Magnetoresistance angle sensor (110) that is magnetically coupled to a rotating shaft (108);
generating, by way of a non-inverting amplifier (114), a first output signal, wherein the first output signal is one of, first and second amplified voltages based on the selection of the first switch (S1);
enabling, by way of a third switch (S3), a selection of, one of, first and second Direct Current (DC) voltages (+VDC and -VDC);
enabling, by way of a second switch (S2), a selection of one of, a second output of the third switch (S3) and the first output signal, wherein the second output is dependent on the selection of the third switch (S3);
executing, by way of an integrator (INT) circuit (116), a dual slope operation based on the selection of the second switch (S2) and the third switch (S3), and generate an input voltage (Vin);
generating, by way of a comparator (118) that is coupled to the INT circuit (116), a comparator output (DP) based on the input voltage (Vin); and
controlling, by way of a control and timing unit (CTU) (120) that is coupled to the comparator (118) and the first through third switches (S1-S3), the first through third switches (S1-S3) such that the CTU (120) determines (i) first and second de-integration times (T1 and T2) and (ii) an output angle (DOUT) based on the first and second de-integration times (T1 and T2).
8. The method (300) as claimed in claim 7, further comprising executing, by way of the INT circuit (116), an integration phase of the dual-slope operation for a predefined time duration, wherein the integration phase is controlled by the CTU (120).
9. The method (300) as claimed in claim 8, further comprising executing, by way of the INT circuit (116), a de-integration phase of the dual-slope operation on an expiration of the predefined time duration, wherein the de-integration phase is controlled by the CTU (120) by way of the third switch (S3).
10. The method (300) as claimed in claim 8, wherein the third resistance (R3) is smaller than the fourth resistance (R4).