DESC:TECHNICAL FIELD OF INVENTION

The present invention is related to the field of electrical engineering. More specifically, it relates to a constant transconductance bias device to reduce PVT variation in ring oscillators.

BACKGROUND OF THE INVENTION

The background information herein below relates to the present disclosure but is not necessarily prior art.

A high-speed cleaner clock is required from frequency synthesizers and clock-data recovery circuits for wireline as well as wireless communication applications. This high-speed clock is generated by putting high operating frequency VCO in negative feedback systems such as PLL. Being most critical block of PLL, most stringent requirements like low power, low jitter and low phase noise becomes benchmarking of VCOs. Ring Oscillators have become preferred choice as compared to LC VCO because of superior performance in tuning range, power, area, and ease of implementation. With the advancement of CMOS technology, performance variation due to Process Voltage Temperature (PVT) has become one of the biggest concerns in designing as VCO gain (Kvco) can very 2-3 times due to PVT variation.

There have been several attempts with various techniques to minimize effects of PVT variation in Ring Oscillators but there is various drawbacks in the existing prior art hence there is need of a constant transconductance bias device. Most prior arts have either used off-chip solutions to compensate for PVT variations or have derived techniques based on square law which in advanced technologies can’t be relied on.

WO2009123708A1 the present invention provides a constant gm circuit that generates a bias current for an emitter/source-coupled multivibrator oscillator. The stable gm bias limits the temperature dependence of the oscillator. Trimming a resistor in the constant gm circuit compensates for process variations, and current sources may be provided that are mirrors of the bias current that are also substantially independent of the supply voltage. The present invention provides an oscillator with less that 1% frequency changes due to PVT variations.

US10840926B2 related to an example oscillator device comprises an oscillation circuit arranged for generating and outputting an oscillation signal and comprising an active circuit to ensure oscillation is maintained, a voltage-to-current conversion replica circuit of the active circuit arranged for receiving the oscillation signal and for outputting a current proportional to the oscillation signal, biasing means arranged to generate a constant bias current to activate the oscillation circuit, and subtraction means for subtracting the current proportional to the oscillation signal from the bias current, thereby obtaining a resulting current which can be used for adapting the oscillation signal's amplitude.

There are various drawbacks to prior art and existing technology. Hence, there was a long-felt need in the art.

OBJECTIVE OF THE INVENTION

The primary objective of the present invention is to provide a constant transconductance bias device to reduce PVT variation in ring oscillators.

Yet another objective of the invention is to mitigate Process Voltage Temperature (PVT) variations in ring oscillators.

Yet another objective of the invention is to provide an on-chip solution for controlling the frequency of the Voltage Controlled Oscillator (VCO) over PVT variations.

Yet another objective of the invention is to ensures stability and performance consistency, particularly in advanced CMOS technology nodes.

SUMMARY OF THE INVENTION

Accordingly, the following invention provides a constant transconductance bias device designed to tackle Process Voltage Temperature (PVT) variations in ring oscillators, crucial for high-speed clock generation in communication circuits. Through meticulous circuit design illustrated in Figure 1(a) and (b), the device integrates a reference biasing generator and a negative feedback system utilizing an operational amplifier to adjust the supply voltage of the ring oscillator's inverter. This ensures stable oscillation frequency across different process, voltage, and temperature conditions. Furthermore, the architecture of the Voltage Controlled Oscillator (VCO), as depicted in Figure 2, is engineered to be resilient to PVT variations, offering an on-chip solution for controlling frequency without relying on the square-law characteristics of MOS transistors.

A negative feedback system to mitigate the PVT variations in Ring Oscillator (RO). The proposed device is to adjust the supply voltage of the inverter such that the negative feedback will compensate for the changes at the supply node of the RO. a constant transconductance (gm) technique has been adopted to control the supply node of the RO across PVT.

By providing an on-chip solution, this invention offers a reliable and robust method for clock generation in communication circuits. The proposed constant transconductance bias device eliminates the need for off-chip solutions, simplifying design complexities and improving overall system reliability. This innovation not only addresses the challenges posed by PVT variations but also holds promise for low-power, robust PVT compensation applications, enhancing the performance and longevity of communication systems in various environmental conditions.

BRIEF DESCRIPTION OF DRAWING

This invention is described by way of example with reference to the following drawings where,

Figure 1(a) of sheet 1 illustrated the reference biasing generator circuit.

Figure 1(b) of sheet 1 illustrated the negative feedback system,
Where.
1 denotes n-type MOS transistor (nMOS),
2 denotes p-type MOS transistor (pMOS),
3 denotes Resistor,
4 denotes Resistor,
5 denotes n-type MOS transistor (nMOS),
6 denotes p-type MOS transistor (pMOS),
7 denotes Operational Amplifier (opamp),
8,9,10,11,12 denotes node voltages.

Figure 2 of sheet 2 illustrated the architecture of the used voltage-controlled oscillator (VCO),
Where.
21,22,23,24 denotes differential inverter,
25,26,27,28,29,30 denotes node voltages,
31,33 denotes p-type MOS transistor (pMOS),
32,34,37 denotes n-type MOS transistor (nMOS).

DETAILED DESCRIPTION OF THE INVENTION

As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

The present discloser relates, in general to a constant transconductance bias device to reduce PVT variation in ring oscillators

The proposed constant gm device provides an on-ship solution to control VCO frequency over PVT variations. The proposed invention consists of three major parts, one reference voltage generator, one negative feedback using Op-Amp, and a VCO. A negative feedback loop consisting of Op-Amp tracks transconductance of replica circuit and generates biasing for ring oscillator. This supply independent biasing of the ring oscillator tries to keep the oscillation frequency in contact across PVT.

It is submitted that most prior arts have either used off-chip solutions to compensate for PVT variations or have derived techniques based on square law which in advanced technologies can’t be relied on. The proposed constant gm technique does not depend on the square-law characteristic of MOS and therefore much more reliable and robust for advanced CMOS technology nodes. It has great potential for low-power robust PVT compensation applications

This invention presents a negative feedback system to mitigate thePVT variations in Ring Oscillator (RO). The proposed invention is to adjust the supply voltage of the inverter such that the negative feedback will compensate for the changes at the supply node of the RO. a constant transconductance (gm) device has been has been developed to control the supply node of the RO across PVT.

Figure 1(a) shows the reference biasing generator circuit consisting of a self-biased inverter forming servo loop with transistor M1-M2. This configuration generates node voltage VX which is equal to trip point of the inverter. This node voltage is provided to a resistive divider consisting of two resistances named R1 and R2. Ratio of R1/R2 is chosen to be very small such that potential of node Y is slightly less than the potential of node X.

Figure 1(b) shows negative feedback system consisting of an operational amplifier (OP1) and a replica biasing circuit. Output node W of the OP1 is connected to replica bias of the RO. Hence, OP1 adjusts the supply of the inverter consisting of M2-M3 across PVT and tries to mitigate any variationat Node W with the help of negative feedback system.

Figure 2 shows the shows the architecture of the used Voltage Controlled Oscillator (VCO) used in constant gm device. Unit delay stage consists of the differential inverter with cross coupled inverters load to guarantee the differential operation. Frequency of the VCO is adjusted by the current starving transistor using VCTL control voltage.

While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.
,CLAIMS:1. A constant transconductance bias device, comprising of;

a reference biasing generator circuit, comprising n-type MOS transistor (1) p-type MOS transistor (2) resistors (3, 4) and an operational amplifier (7) interconnected to generate a reference voltage (VX) for biasing;

a negative feedback system comprising an operational amplifier (7) and MOS transistors (1, 2, 5, 6) connected to adjust the supply voltage of the ring oscillator's inverter,
wherein the operational amplifier (7) adjusts the supply voltage based on feedback signals to counteract PVT variations, and;

a voltage-controlled oscillator (VCO) architecture differential inverters (21, 22, 23, 24) p-type MOS transistors (31, 33) and n-type MOS transistors (32, 34, 37) interconnected.

2. The constant transconductance bias device as claimed in claim 1, wherein the reference biasing generator circuit generates a reference voltage (VX) to establish biasing parameters for the subsequent negative feedback system.

3. The constant transconductance bias device as claimed in claim 1 wherein the negative feedback system utilizes an operational amplifier (7) to adjust the supply voltage of the ring oscillator's inverter based on the transconductance of a replica circuit, thereby stabilizing the oscillation frequency across PVT variations.

4. The constant transconductance bias device as claimed in claim 1, wherein the Voltage Controlled Oscillator (VCO) architecture incorporates differential inverters (21, 22, 23, 24) and MOS transistors (31, 32, 33, 34, 37) to provide a resilient on-chip solution for controlling frequency without relying on the square-law characteristics of MOS transistors.