FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
GATE DRIVE CIRCUIT;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION
ORGANISED AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS
IS 7-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED
2
DESCRIPTION
TECHNICAL FIELD
[0001] The present disclosure relates to a gate drive
circuit.
5
BACKGROUND ART
[0002] As switching devices used for a power conversion
device or the like, for example, semiconductor elements such
as insulated-gate bipolar transistors (IGBTs) or metal-oxide10 semiconductor field-effect transistors (MOSFETs) are used.
These switching devices receive output voltages from drive
circuits and perform switching operations. When each of
these switching devices is turned on or turned off, the
switching device experiences switching loss.
15 [0003] If the switching loss is decreased, power
consumption of the power conversion device can be decreased,
whereby the efficiency at the time of power conversion is
improved. Therefore, in order to realize downsizing and
efficiency improvement of the power conversion device, it is
20 desirable to decrease the switching loss in the switching
device.
The switching loss can be decreased by increasing
the switching speed. The switching speed can be increased by
hastening a voltage change at around a gate threshold voltage
25 of the switching device.
3
[0004] As a method for decreasing the switching loss, a
method has been disclosed in which a first voltage higher
than an ordinarily-applied voltage is applied at first to
realize high-speed switching, and, at a predetermined timing
5 after a switching element is turned on, change is performed
such that the voltage at a gate terminal of the switching
element becomes a second voltage lower than the voltage of a
first voltage source, thereby increasing the switching speed
at the time of turn-on (see, for example, Patent Document 1).
10 [0005] Meanwhile, at the timing of turn-on, short-circuit
fault sometimes occurs owing to abnormality of a control
circuit and failure of a switching element that forms a pair.
Consequently, the switching element might be broken. If the
gate voltage of the switching element is high, large current
15 flows through the switching element at the time of the shortcircuit fault. In view of this, a method has been disclosed
in which a first voltage lower than an ordinarily-applied
voltage is applied at first to limit current that flows at
the time of short-circuit fault and ensure short-circuit
20 withstand capability, and, at a predetermined timing after a
switching element is normally turned on, change is performed
such that the voltage at a gate terminal of the switching
element becomes a second voltage higher than the voltage of a
first voltage source in order to decrease steady conduction
25 loss (see, for example, Patent Document 2).
4
CITATION LIST
PATENT DOCUMENT
[0006] Patent Document 1: Japanese Laid-Open Patent
5 Publication No. 2007-174134
Patent Document 2: Japanese Laid-Open Patent
Publication No. 2009-071956
SUMMARY OF THE INVENTION
10 PROBLEM TO BE SOLVED BY THE INVENTION
[0007] In the method disclosed in Patent Document 1, since
the gate voltage of the switching element is high, the
switching loss is decreased, but the switching element might
be broken owing to short-circuit fault that might occur at
15 the timing of turn-on.
In the method disclosed in Patent Document 2, since
the initial gate voltage at the time of turn-on is low,
current that flows at the time of short-circuit fault can be
limited, but a problem arises in that the switching loss
20 increases.
Thus, decrease of switching loss and ensuring of
short-circuit withstand capability are in a trade-off
relationship.
[0008] The present disclosure has been made to solve the
25 above problems, and an object of the present disclosure is to
5
provide a gate drive circuit, for a switching element, that
can achieve both decrease of switching loss and ensuring of
short-circuit withstand capability.
5 MEANS TO SOLVE THE PROBLEM
[0009] A gate drive circuit according to the present
disclosure is a gate drive circuit including a control unit
which applies, between a gate and a source of a switching
element to be driven, a gate voltage and drives the switching
10 element. The control unit applies, between the gate and the
source of the switching element, a first voltage so as to
turn on the switching element. After transference of drain
current of the switching element, the control unit interrupts
the first voltage and applies, between the gate and the
15 source of the switching element, a second voltage that is
lower than the first voltage and that is higher than a mirror
voltage of the switching element. When no short-circuit
current is flowing to the switching element to be driven, the
control unit interrupts the second voltage and applies,
20 between the gate and the source of the switching element, a
third voltage higher than the second voltage.
EFFECT OF THE INVENTION
[0010] In the gate drive circuit according to the present
25 disclosure, at the time of turn-on, switching is performed at
6
a high voltage so that switching loss is decreased.
Furthermore, even if short-circuit current occurs as a result
of the turn-on, the gate voltage is immediately decreased to
be low so that the short-circuit current can also be
5 decreased, whereby short-circuit withstand capability can
also be ensured. Moreover, the gate voltage is increased
thereafter, whereby steady conduction loss can also be
decreased to be low.
10 BRIEF DESCRIPTION OF THE DRAWINGS
[0011] [FIG. 1] FIG. 1 is a circuit configuration diagram
schematically showing a gate drive circuit according to
embodiment 1.
[FIG. 2] FIG. 2 shows an example of a power
15 conversion system to which the gate drive circuits according
to embodiment 1 and switching elements to be driven have been
applied.
[FIG. 3] FIG. 3 is a timing chart showing
operation of the gate drive circuit according to embodiment 1.
20 [FIG. 4] FIG. 4 is another timing chart showing
operation of the gate drive circuit according to embodiment 1.
[FIG. 5] FIG. 5 is a circuit configuration diagram
schematically showing a gate drive circuit according to
embodiment 2.
25 [FIG. 6] FIG. 6 is a timing chart showing
7
operation of the gate drive circuit according to embodiment 2.
[FIG. 7] FIG. 7 is a circuit configuration diagram
schematically showing a gate drive circuit according to
embodiment 3.
5 [FIG. 8] FIG. 8 is a timing chart showing
operation of the gate drive circuit according to embodiment 3.
[FIG. 9] FIG. 9 is a hardware configuration
diagram of a control unit provided to any of the gate drive
circuits according to embodiments 1 to 3.
10
DESCRIPTION OF EMBODIMENTS
[0012] Hereinafter, the present embodiments will be
described with reference to the drawings. In the drawings,
the same or corresponding parts are denoted by the same
15 reference characters. Also, FIG. 1 to FIG. 9 are related to
embodiments, and the present disclosure is not limited by
these drawings.
[0013] Embodiment 1
Hereinafter, a gate drive circuit according to
20 embodiment 1 will be described with reference to FIG. 1.
FIG. 1 is a circuit configuration diagram
schematically showing the gate drive circuit according to
embodiment 1. FIG. 2 shows an example of a power conversion
system to which the gate drive circuits and switching
25 elements to be driven have been applied.
8
Regarding a gate drive circuit 100 shown in FIG. 1,
without limitation to the present embodiment 1, any of gate
drive circuits according to other embodiments can be used for
various power converters. For example, the gate drive
5 circuit can be used as each of the gate drive circuits of the
power conversion system shown in FIG. 2. An example of the
power conversion system shown in FIG. 2 is a three-phase
inverter system in which AC power from a grid power supply is
rectified to DC power by a rectification circuit, and then
10 the DC power is converted into AC power to be outputted to a
motor as a load, or the like. Here, each of gate drive
circuits 100a, 100b, 100c, 100d, 100e, and 100f and each of
switching elements 99a, 99b, 99c, 99d, 99e, and 99f in FIG. 2
correspond to a gate drive circuit 100 and a switching
15 element 99 in any of FIG. 1, and FIG. 5 and FIG. 7 described
later.
[0014] In the drawings, an insulated-gate bipolar
transistor (IGBT) which is a representative power
semiconductor element is used as the switching element 99 to
20 be driven by the gate drive circuit 100. However, the
switching element 99 to be driven is not limited to an IGBT
and may be another voltage-driven switching element such as a
metal-oxide-semiconductor field-effect transistor (MOSFET).
It is noted that a diode is connected in antiparallel to the
25 IGBT. Meanwhile, if the switching element 99 is an MOSFET,
9
it is also possible to use a body diode of the MOSFET instead.
[0015] Next, a detailed configuration of the gate drive
circuit 100 for the switching element 99 to be driven will be
described. In FIG. 1, a first power supply 61 for applying a
5 positive voltage to a gate terminal of the switching element
99 is connected to the gate terminal of the switching element
99 via a switching element 1 and a gate resistor 6 for
adjusting a switching speed. In addition, in order to apply
a second power supply voltage V2 to the gate terminal of the
10 switching element 99, a diode 8, a switching element 15, and
a second power supply 62 are connected in series to the gate
terminal. Furthermore, a fourth power supply 64 for applying
a negative voltage to the gate terminal of the switching
element 99 is connected to the gate terminal of the switching
15 element 99 via a switching element 4 and a gate resistor 7
for adjusting the switching speed. Here, an example in which
each of the switching elements 1, 4, and 15 is an MOSFET is
shown.
[0016] It is noted that each of the power supplies is a DC
20 power supply, and voltages V1, V2, and V4 applied to the gate
terminal from the respective power supplies 61, 62, and 64
satisfy the following relationship.
V1 > V2 > mirror voltage of switching element 99 >
V4
25 Here, the voltage V1 is defined as a voltage that
10
should be applied in an ON state and that is set for each
switching element 99. The voltage V4 is a negative voltage
and is a voltage of about, for example, -5 to -15 V.
[0017] In FIG. 1, the gate drive circuit 100 further has a
5 control unit 5 which controls each of the switching elements
1, 4, and 15 in order to control the voltage to be applied to
the gate terminal of the switching element 99. The control
unit 5 includes a short-circuit current detection unit 51
which performs, on the basis of an output from a current
10 detector 20 for current flowing to the switching element 99,
detection as to whether short-circuit current is flowing to
the switching element 99.
[0018] Next, operation of the gate drive circuit 100 will
be described with reference to a timing chart in FIG. 3. The
15 drawing is a timing chart showing, in order from the top, a
gate voltage Vgs which is the voltage between a gate and a
source, a drive signal Vg1 for turning on the switching
element 1, a drive signal Vg4 for turning on/off the
switching element 4, a drive signal Vg3 for turning on/off
20 the switching element 15, drain current Id of the switching
element 99, and a drain-source voltage Vds of the switching
element 99.
[0019] At a time point t0, the drive signal Vg1 becomes
high (H) so as to turn on the switching element 1.
25 Consequently, the first voltage V1 is applied for the gate
11
voltage Vgs via the gate resistor 6, and the switching
element 99 is turned on at an ordinary switching speed. Here,
the ordinary switching speed refers to a switching speed when
turn-on is performed at the voltage V1 that should be applied
5 in an ON state.
[0020] At a time point t1, the gate voltage Vgs reaches a
mirror voltage, and consequently, the drain current Id of the
switching element 99 gradually increases and, at a time point
t2, reaches a current that should originally be caused to
10 flow. Here, the current that should originally be caused to
flow refers to a current determined according to input
voltage, the state of the motor, or the like, and the drain
current Id increases to a current that has been flowing
through a pair-forming arm having been in an ON state until
15 just before. At this point, transference of the drain
current Id is completed.
[0021] Thereafter, the drain-source voltage Vds decreases
and, at a time point t3, reaches 0 V, and turn-on of the
switching element 99 is normally ended. In addition, the
20 gate voltage Vgs increases to the first voltage V1 between
the time point t2 and the time point t3. Although an example
in which the gate voltage Vgs becomes the first voltage V1
between the time point t2 and the time point t3 has been
described here, the present disclosure is not limited to this
25 example. That is, the gate voltage Vgs only has to become a
12
voltage equal to or higher than the second voltage V2 between
the time point t2 and the time point t3.
[0022] At the timing of completion of switching (time
point t3), the drive signal Vg1 is set to be low (L) so as to
5 turn off the switching element 1. At the same time, the
drive signal Vg3 is set to be high (H) so as to turn on a
gate of the switching element 15. Consequently, the gate
voltage Vgs decreases to the second voltage V2 (at a time
point t4).
10 [0023] The state where the gate voltage Vgs is the second
voltage V2 is maintained until a time point t5. This time
period is provided in consideration of a delay time period,
of the circuit, for performing detection as to whether shortcircuit current is flowing to the switching element 99. That
15 is, the state of being the second voltage V2 is maintained
for the delay time period for the short-circuit current
detection unit 51.
[0024] Since the gate voltage Vgs decreases to the second
voltage V2 lower than the first voltage V1, this decrease
20 causes increase of the conduction loss in the switching
element 99. However, the period from the time point t4 to
the time point t5 is about several microseconds, and there is
little influence on the loss. Furthermore, since the gate
voltage Vgs is decreased after switching is completed,
25 deterioration regarding switching loss does not occur, either.
13
[0025] If the short-circuit current detection unit 51
determines that no short-circuit current is flowing to the
switching element 99, i.e., no short-circuit has occurred,
the drive signal Vg3 is set to be low (L) at the time point
5 t5 so as to turn off the switching element 15. At the same
time, the drive signal Vg1 is set to be high (H) again so as
to turn on a gate of the switching element 1. Consequently,
the first voltage V1 is applied for the gate voltage Vgs
again via the gate resistor 6, and thus the switching element
10 99 continues to be operated at an ordinary conduction loss.
[0026] Although not shown in the drawing, the drive signal
Vg1 is set to be low (L) so as to turn off the switching
element 1 at the time of turning off the switching element 99.
At the same time, the drive signal Vg4 is set to be high (H)
15 so as to turn on a gate of the switching element 4.
Consequently, the fourth voltage V4 which is a negative
voltage is applied for the gate voltage Vgs via the gate
resistor 7, and also, the drain current Id becomes 0. This
state corresponds to a state taken before the time point t0.
20 [0027] The timing chart in FIG. 3 shows an example in
which no short-circuit current has been detected. Next,
operation in the case where short-circuit current has been
detected will be described with reference to FIG. 4.
In FIG. 4, events from the time point t0 to a time
25 point t12 are the same as those from the time point t0 to the
14
time point t2 in FIG. 3. That is, at the time point t0, the
drive signal Vg1 becomes high (H) so as to turn on the
switching element 1. Consequently, the first voltage V1 is
applied for the gate voltage Vgs via the gate resistor 6, and
5 the switching element 99 is turned on at the ordinary
switching speed.
At a time point t11, the gate voltage Vgs reaches
the mirror voltage, and consequently, the drain current Id of
the switching element 99 gradually increases and, at the time
10 point t12, reaches the current that has been flowing through
the pair-forming arm, and transference of the drain current
Id is completed.
[0028] Here, if there is abnormality in a switching
element 99 forming a pair with this switching element 99 and
15 a state where short-circuit has occurred is maintained, the
drain current Id further increases as in a period subsequent
to the time point t12 in FIG. 4, and this leads to a state
where short-circuit fault has occurred. Here, if, for
example, the power conversion system is configured as in FIG.
20 2, the switching element 99b is a switching element that
forms a pair with the switching element 99a. It is noted
that a short-circuit withstand capability is set for each
switching element 99, and thus the switching element 99 is
not immediately broken even when the drain current Id starts
25 to increase. When loss becomes excessive as a result of
15
continuation of this state for a long time, the switching
element ends up being broken.
[0029] Upon completion of transference of the drain
current Id, the drive signal Vg1 is set to be low (L) so as
5 to turn off the switching element 1. At the same time, the
drive signal Vg3 is set to be high (H) so as to turn on the
gate of the switching element 15. Consequently, the gate
voltage Vgs decreases to the second voltage V2 (at a time
point t14). Decrease in the gate voltage Vgs makes it
10 possible to limit the drain current Id, and likewise,
suppress loss generated owing to short-circuit fault.
Therefore, decrease in the gate voltage Vgs leads to
elongation of the time period in which short-circuit current
can be kept flowing, whereby a time period for determination
15 as to short-circuit fault can be ensured. Since the gate
voltage Vgs is decreased after switching is completed, there
is no influence on switching loss.
[0030] The state where the gate voltage Vgs is the second
voltage V2 is maintained until a time point t15. As
20 described above, detection as to whether short-circuit
current is flowing to the switching element 99 is performed
during this time period.
If the short-circuit current detection unit 51
determines that short-circuit has occurred, the drive signal
25 Vg3 is set to be low (L) at the time point t15 so as to turn
16
off the switching element 15. At the same time, the drive
signal Vg4 is set to be high (H) so as to turn on the gate of
the switching element 4. Consequently, the fourth voltage V4
which is a negative voltage is applied for the gate voltage
5 Vgs via the gate resistor 7, and the switching element 99 is
turned off. Thus, the switching element 99 can be normally
caused to stop operating, before the switching element 99 is
broken.
[0031] As described above, the gate drive circuit
10 according to embodiment 1 includes the control unit 5 which
controls the gate voltage Vgs of the switching element 99 to
be driven and which drives the switching element 99. The
control unit 5 is configured to control the gate voltage Vgs
by applying, to the gate of the switching element 99, any one
15 of at least three types of voltages, i.e., the first voltage
V1, the second voltage V2, and the fourth voltage V4 which is
a negative voltage. Further, at the time of turning on the
switching element 99, switching is performed at the high
first voltage V1 so that the switching loss is decreased.
20 Furthermore, even if short-circuit current occurs as a result
of the turn-on, the gate voltage Vgs is immediately decreased
to be low (second voltage V2) so that the short-circuit
current can be decreased, whereby the short-circuit withstand
capability can be ensured. Here, if no short-circuit current
25 has occurred, the gate voltage Vgs is set to be the first
17
voltage V1 thereafter, whereby the steady conduction loss can
also be decreased to be low. Meanwhile, if short-circuit
current has occurred, the gate voltage Vgs is changed from
the second voltage V2 to the fourth voltage V4 which is a
5 negative output voltage, whereby the switching element 99 is
turned off, and operation can be ended before the switching
element 99 is broken.
[0032] Embodiment 2
Hereinafter, a gate drive circuit according to
10 embodiment 2 will be described with reference to the drawings.
Embodiment 2 is an example in which the switching element 99
is turned on at a voltage that is even higher than the first
voltage V1 used in embodiment 1.
FIG. 5 is a circuit configuration diagram
15 schematically showing the gate drive circuit according to
embodiment 2. FIG. 6 is a timing chart showing operation of
the gate drive circuit.
[0033] In FIG. 5, a power supply 63 which supplies a third
voltage V3 higher than the first voltage V1 is connected to
20 one end of the switching element 1. In addition, the power
supply 61 which supplies the first voltage V1 is connected in
series to a diode 14 and a switching element 13 and connected
to the gate terminal of the switching element 99. The other
components are the same as those in FIG. 1 regarding
25 embodiment 1, and thus will not be described.
18
[0034] It is noted that each of the power supplies is a DC
power supply, and voltages V1, V2, V3, and V4 applied to the
gate terminal from the respective power supplies 61, 62, 63,
and 64 satisfy the following relationship.
5 V3 > V1 > V2 > mirror voltage of switching element
99 > V4
Here, the voltage V1 is defined as a voltage that
should be applied in an ON state and that is set for each
switching element 99, and the voltage V3 is a voltage higher
10 than the voltage V1, i.e., higher than the voltage that
should ordinarily be applied. The voltage V4 is a negative
voltage.
[0035] Next, operation of the gate drive circuit 100 will
be described with reference to the timing chart in FIG. 6.
15 The drawing is a timing chart showing, in order from the top,
the gate voltage Vgs which is the voltage between the gate
and the source, the drive signal Vg1 for turning on the
switching element 1, the drive signal Vg4 for turning on/off
the switching element 4, the drive signal Vg3 for turning
20 on/off the switching element 15, a drive signal Vg5 for
turning on/off the switching element 13, the drain current Id
of the switching element 99, and the drain-source voltage Vds
of the switching element 99.
[0036] At the time point t0, the drive signal Vg1 becomes
25 high (H) so as to turn on the switching element 1.
19
Consequently, the third voltage V3 is applied for the gate
voltage Vgs via the gate resistor 6, and the switching
element 99 is turned on at a switching speed that is higher
than that in an ordinary case, i.e., higher than that in a
5 case where the voltage at the time of switching is the first
voltage V1.
At a time point t21, the gate voltage Vgs reaches
the mirror voltage, and consequently, the drain current Id of
the switching element 99 gradually increases and, at a time
10 point t22, reaches the current that has been flowing to the
pair-forming arm. At this point, transference of the drain
current Id is completed.
[0037] Thereafter, the drain-source voltage Vds decreases
and, at a time point t23, reaches 0 V, and turn-on of the
15 switching element 99 is normally ended. In addition, the
gate voltage Vgs increases to the third voltage V3 between
the time point t22 and the time point t23. It is noted that
the gate voltage Vgs does not necessarily have to reach the
third voltage V3 by the time point t23 at which the drain20 source voltage Vds completely decreases.
Since the gate voltage Vgs is set to be high, the
period from the time point t0 to the time point t23 is
shorter than the period from the time point t0 to the time
point t3 in embodiment 1, and the switching loss can be made
25 lower than that in embodiment 1.
20
[0038] At the timing of completion of switching (time
point t23), the drive signal Vg1 is set to be low (L) so as
to turn off the switching element 1. At the same time, the
drive signal Vg3 is set to be high (H) so as to turn on the
5 gate of the switching element 15. Consequently, the gate
voltage Vgs decreases to the second voltage V2 (at a time
point t24).
[0039] The state where the gate voltage Vgs is the second
voltage V2 is maintained until a time point t25. Similar to
10 embodiment 1, detection as to whether short-circuit current
is flowing to the switching element 99 is performed during
this time period. That is, the state of being the second
voltage V2 is maintained for the delay time period for the
short-circuit current detection unit 51.
15 [0040] Since the gate voltage Vgs decreases to the second
voltage V2 lower than the first voltage V1 that should
ordinarily be applied, this decrease causes increase of the
conduction loss in the switching element 99. However, the
period from the time point t24 to the time point t25 is about
20 several microseconds, and there is little influence on the
loss. Furthermore, since the gate voltage Vgs is decreased
after switching is completed, deterioration regarding
switching loss does not occur, either.
[0041] If the short-circuit current detection unit 51
25 determines that no short-circuit current is flowing to the
21
switching element 99, i.e., no short-circuit has occurred,
the drive signal Vg3 is set to be low (L) at the time point
t25 so as to turn off the switching element 15. At the same
time, the drive signal Vg5 is set to be high (H) so as to
5 turn on a gate of the switching element 13. Consequently,
the gate voltage Vgs becomes the first voltage V1, whereby
the switching element 99 continues to be operated at the
ordinary conduction loss.
[0042] Although not shown in the drawing, the drive signal
10 Vg1 is set to be low (L) so as to turn off the switching
element 13 at the time of turning off the switching element
99. At the same time, the drive signal Vg4 is set to be high
(H) so as to turn on the gate of the switching element 4.
Consequently, the fourth voltage V4 which is a negative
15 voltage is applied for the gate voltage Vgs via the gate
resistor 7, and also, the drain current Id becomes 0. This
state corresponds to the state taken before the time point t0.
[0043] The timing chart in FIG. 6 shows an example in
which no short-circuit current has been detected. Meanwhile,
20 operation in the case where short-circuit current has been
detected is the same as that in FIG. 4 regarding embodiment 1.
That is, at the time point t25 in FIG. 6, the drive signal
Vg3 is set to be low (L) so as to turn off the switching
element 15. At the same time, the drive signal Vg4 is set to
25 be high (H) so as to turn on the gate of the switching
22
element 4.
[0044] As described above, the gate drive circuit
according to embodiment 2 exhibits the same advantageous
effects as those in embodiment 1. Furthermore, the control
5 unit 5 is configured to control the gate voltage Vgs by
applying, to the gate of the switching element 99, any one of
at least four types of voltages, i.e., the first voltage V1,
the second voltage V2, the third voltage V3, and the fourth
voltage V4 which is a negative voltage. Further, at the time
10 of turning on the switching element 99, switching is
performed at the third voltage V3 higher than that applied at
the time of ordinary operation so that the switching loss is
decreased. Furthermore, even if short-circuit current occurs
as a result of the turn-on, the gate voltage Vgs is
15 immediately decreased to be low (second voltage V2) so that
the short-circuit current can be decreased, whereby the
short-circuit withstand capability can be ensured. Here, if
no short-circuit current has occurred, the gate voltage Vgs
is set to be the first voltage V1 thereafter, whereby the
20 steady conduction loss can also be decreased to be low.
Meanwhile, if short-circuit current has occurred, the gate
voltage Vgs is changed from the second voltage V2 to the
fourth voltage V4 which is a negative output voltage, whereby
the switching element 99 is turned off, and operation can be
25 ended before the switching element 99 is broken.
23
[0045] In particular, if the switching element 99 to be
driven is formed of a wide-bandgap semiconductor that is a
compound semiconductor such as silicon carbide (SiC) or
gallium nitride (GaN), the internal gate resistor is high,
5 and, even if the external gate resistor 6 is set to 0 Ω, the
switching loss might be high. Although a certain
advantageous effect is exhibited with the configuration in
embodiment 1 as well, the advantageous effect of decreasing
the switching loss becomes more significant by causing, at
10 the time of switching, the gate voltage Vgs to be a voltage
higher than that applied at the time of ordinary operation as
in the present embodiment 2.
[0046] Embodiment 3
Hereinafter, a gate drive circuit according to
15 embodiment 3 will be described with reference to the drawings.
The present embodiment 3 is an example of a circuit
in which the voltage is decreased from the first voltage V1
to a second voltage V2a without using the second power supply
in embodiment 1.
20 FIG. 7 is a circuit configuration diagram
schematically showing the gate drive circuit according to
embodiment 3. FIG. 8 is a timing chart showing operation of
the gate drive circuit.
[0047] In FIG. 7, the diode 8, a transistor 2, and a
25 resistor 12 for generating the second voltage V2a are
24
connected in series to the gate terminal of the switching
element 99, a Zener diode 10 for determining a voltage is
connected via the power supply 61 to a base side of the
transistor 2, a transistor 3 for turn-on/off thereof is
5 connected via a resistor 11, and an emitter of the transistor
3 is connected to the power supply 64 (the voltage V4 thereof
being a negative voltage).
[0048] In the timing chart in FIG. 8, events from the time
point t0 to a time point t32 are the same as those from the
10 time point t0 to the time point t2 in FIG. 3 regarding
embodiment 1, and thus will not be described.
After transference of the drain current Id is
completed at the time point t32, the drain-source voltage Vds
decreases and, at a time point t33, reaches 0 V, and turn-on
15 of the switching element 99 is normally ended.
[0049] At the timing of completion of switching (time
point t33), the drive signal Vg1 is set to be low (L) so as
to turn off the switching element 1. A drive signal Vg13 is
set to be high (H) so as to turn on the transistor 3.
20 Consequently, the emitter voltage of the transistor 2
decreases to a voltage lower than the first voltage V1, e.g.,
V2, the transistor 2 of a PNP type is turned on, and the
second voltage V2a obtained through addition of a voltage Vbe
between the base and the emitter of the transistor 2 is
25 applied for the gate voltage Vgs of the switching element 99.
25
Here, V2a=V2+Vbe is satisfied, and the voltage Vbe is about 1
V. That is, after turn-on is ended, the gate voltage Vgs can
be decreased to the second voltage V2a lower than the first
voltage V1 (at a time point t34) without using the power
5 supply 62 described in each of embodiments 1 and 2.
Subsequent operations and the operation in the case where
short-circuit has been detected, are the same as those in
embodiment 1, and will not be described.
[0050] As described above, the gate drive circuit
10 according to embodiment 3 also exhibits the same advantageous
effects as those in embodiment 1. In addition, the number of
power supplies is smaller than that in embodiment 1, and thus
the gate drive circuit can be configured at low cost.
[0051] It is noted that the control unit 5 in each of
15 embodiments 1 to 3 is composed of a processor 1001 and a
storage device 1002, an example of hardware of the control
unit 5 being shown in FIG. 9. Although not shown, the
storage device includes a volatile storage device such as a
random access memory and a nonvolatile auxiliary storage
20 device such as a flash memory. Alternatively, the storage
device may include, as the auxiliary storage device, a hard
disk instead of a flash memory. The processor 1001 executes
a program inputted from the storage device 1002. In this
case, the program is inputted from the auxiliary storage
25 device via the volatile storage device to the processor 1001.
26
Further, the processor 1001 may output data such as a
computation result to the volatile storage device of the
storage device 1002 or may save the data via the volatile
storage device into the auxiliary storage device.
5 [0052]
In embodiments 1 to 3, the short-circuit current
detection unit 51 which detects occurrence of abnormality
such as short-circuit fault that involves flow of shortcircuit current is provided in the control unit 5. However,
10 the short-circuit current detection unit 51 may be provided
outside of the control unit 5. If the short-circuit current
detection unit 51 is provided outside of the control unit 5,
configuring only has to be performed such that: a signal
regarding presence/absence of short-circuit fault is inputted
15 to the control unit 5; and the gate voltage Vgs is controlled
on the basis of the signal.
[0053] In embodiments 1 to 3, the switching elements 1, 4,
13, and 15 in the gate drive circuits 100 have been described
as being exemplified by MOSFETs. However, the switching
20 elements may be other switching elements such as IGBTs.
[0054] The circuit configurations of the gate drive
circuits described in embodiments 1 to 3 are not limited to
those in the drawings presented as examples, and a circuit
with, for example, any number of power supplies may be used
25 as long as the circuit allows a plurality of different
27
voltages to be applied, as the gate voltage Vgs, between the
gate and the source of the switching element 99 to be driven.
[0055] Although the disclosure is described above in terms
of various exemplary embodiments and implementations, it
5 should be understood that the various features, aspects, and
functionality described in one or more of the individual
embodiments are not limited in their applicability to the
particular embodiment with which they are described, but
instead can be applied, alone or in various combinations to
10 one or more of the embodiments of the disclosure.
It is therefore understood that numerous
modifications which have not been exemplified can be devised
without departing from the scope of the specification of the
present disclosure. For example, at least one of the
15 constituent components may be modified, added, or eliminated.
At least one of the constituent components mentioned in at
least one of the preferred embodiments may be selected and
combined with the constituent components mentioned in another
preferred embodiment.
20
DESCRIPTION OF THE REFERENCE CHARACTERS
[0056] 1, 4, 13, 15 switching element
2, 3 transistor
5 control unit
25 6, 7 gate resistor
28
8, 14 diode
9, 11, 12 resistor
10 Zener diode
20 current detector
5 51 short-circuit current detection unit
61, 62, 63, 64 power supply
99 switching element
100 gate drive circuit
1001 processor
10 1002 storage device
V1, V2, V3, V4 voltage

We Claim:
[Claim 1] A gate drive circuit comprising
a control unit which applies, between a gate and a
5 source of a switching element to be driven, a gate voltage
and drives the switching element, wherein
the control unit
applies, between the gate and the source of the
switching element, a first voltage so as to turn on the
10 switching element,
after transference of drain current of the
switching element, interrupts the first voltage and applies,
between the gate and the source of the switching element, a
second voltage that is lower than the first voltage and that
15 is higher than a mirror voltage of the switching element, and
when no short-circuit current is flowing to the
switching element to be driven, interrupts the second voltage
and applies, between the gate and the source of the switching
element, a third voltage higher than the second voltage.
20
[Claim 2] The gate drive circuit according to claim 1,
wherein
the third voltage is a voltage equal to the first
voltage.
25
30
[Claim 3] The gate drive circuit according to claim 2,
further comprising:
a first gate resistor, a first switching element,
and a first power supply which are connected in series to the
5 gate of the switching element to be driven; and
a second switching element and a second power
supply which are connected in series to the gate of the
switching element to be driven, wherein
the control unit
10 turns on the first switching element so as to
apply, between the gate and the source of the switching
element to be driven, the first voltage from the first power
supply, and
turns on the second switching element so as to
15 apply, between the gate and the source of the switching
element to be driven, the second voltage from the second
power supply.
[Claim 4] The gate drive circuit according to claim 2 or 3,
20 wherein
when short-circuit current is flowing to the
switching element to be driven, the control unit interrupts
the second voltage and applies, between the gate and the
source of the switching element, a fourth voltage which is a
25 negative voltage.
31
[Claim 5] The gate drive circuit according to claim 4,
further comprising:
a first gate resistor, a first switching element,
5 and a first power supply which are connected in series to the
gate of the switching element to be driven;
a second switching element and a second power
supply which are connected in series to the gate of the
switching element to be driven; and
10 a second gate resistor, a fourth switching element,
and a fourth power supply which are connected in series to
the gate of the switching element to be driven, wherein
the control unit
turns on the first switching element so as to
15 apply, between the gate and the source of the switching
element to be driven, the first voltage from the first power
supply,
turns on the second switching element so as to
apply, between the gate and the source of the switching
20 element to be driven, the second voltage from the second
power supply, and
turns on the fourth switching element so as to
apply, between the gate and the source of the switching
element to be driven, the fourth voltage from the fourth
25 power supply.
32
[Claim 6] The gate drive circuit according to claim 2,
further comprising:
a first gate resistor, a first switching element,
5 and a first power supply which are connected in series to the
gate of the switching element to be driven;
a second gate resistor, a fourth switching element,
and a fourth power supply which are connected in series to
the gate of the switching element to be driven;
10 a first diode, a first transistor, and a first
resistor which are connected in series between the gate of
the switching element to be driven and the fourth power
supply; and
a second transistor having an emitter connected to
15 the fourth power supply, the second transistor having a
collector connected to the first power supply, wherein
an intermediate point between the second transistor
and the first power supply is connected to a base of the
first transistor, and
20 the control unit
turns on the first switching element so as to
apply, between the gate and the source of the switching
element to be driven, the first voltage from the first power
supply, and
25
33
turns on the second transistor so as to apply,
between the gate and the source of the switching element to
be driven, the second voltage lower than the first voltage.
5 [Claim 7] The gate drive circuit according to claim 6,
wherein
when short-circuit current is flowing to the
switching element to be driven, the control unit interrupts
the second voltage and turns on the fourth switching element
10 so as to apply, between the gate and the source of the
switching element to be driven, a fourth voltage which is a
negative voltage from the fourth power supply.
[Claim 8] The gate drive circuit according to claim 1,
15 wherein
the third voltage is a voltage that is lower than
the first voltage and that is higher than the second voltage.
[Claim 9] The gate drive circuit according to claim 8,
20 further comprising:
a first gate resistor, a first switching element,
and a first power supply which are connected in series to the
gate of the switching element to be driven;
25
34
a second switching element and a second power
supply which are connected in series to the gate of the
switching element to be driven; and
a third switching element and a third power supply
5 which are connected in series to the gate of the switching
element to be driven, wherein
the control unit
turns on the first switching element so as to
apply, between the gate and the source of the switching
10 element to be driven, the first voltage from the first power
supply,
turns on the second switching element so as to
apply, between the gate and the source of the switching
element to be driven, the second voltage from the second
15 power supply, and
turns on the third switching element so as to
apply, between the gate and the source of the switching
element to be driven, the third voltage from the third power
supply.
20
[Claim 10] The gate drive circuit according to claim 8 or
9, wherein
when short-circuit current is flowing to the
switching element to be driven, the control unit interrupts
25 the second voltage and applies, between the gate and the
35
source of the switching element to be driven, a fourth
voltage which is a negative voltage.
[Claim 11] The gate drive circuit according to claim 10,
5 further comprising:
a first gate resistor, a first switching element,
and a first power supply which are connected in series to the
gate of the switching element to be driven;
a second switching element and a second power
10 supply which are connected in series to the gate of the
switching element to be driven;
a third switching element and a third power supply
which are connected in series to the gate of the switching
element to be driven; and
15 a second gate resistor, a fourth switching element,
and a fourth power supply which are connected in series to
the gate of the switching element to be driven, wherein
the control unit
turns on the first switching element so as to
20 apply, between the gate and the source of the switching
element to be driven, the first voltage from the first power
supply,
turns on the second switching element so as to
apply, between the gate and the source of the switching
25 element to be driven, the second voltage from the second
36
power supply,
turns on the third switching element so as to
apply, between the gate and the source of the switching
element to be driven, the third voltage from the third power
5 supply, and
turns on the fourth switching element so as to
apply, between the gate and the source of the switching
element to be driven, the third voltage from the third power
supply.
10
[Claim 12] The gate drive circuit according to any one of
claims 1 to 11, wherein
a timing of applying the second voltage is
subsequent to completion of turn-on as a result of decrease
15 in a voltage between a drain and the source of the switching
element to be driven.
[Claim 13] The gate drive circuit according to any one of
claims 1 to 12, wherein
20 the control unit includes a short-circuit current
detection circuit which performs detection as to whether
short-circuit current is flowing to the switching element.
[Claim 14] The gate drive circuit according to any one of
25 claims 1 to 13, wherein
37
the switching element to be driven is formed of a
semiconductor having a wide bandgap.