Field of Invention:
The invention relates to the field of mechatronics in secure
systems, which incorporates the securitization of encryption
modules from un authorized access.
Background of Invention:
Resistance to tampering the device by either normal users or
systems or others with physical access to it. It ranges from
simple features like screws with special heads to complex
devices which can zeroize the content in it or encrypt the
information.
Attacker Categories:
1. Class I (clever outsiders) -. Clever but have
insufficient knowledge of the system and
equipment.
2. Class II (knowledgeable insiders) —. Generally have
access sophisticated equipment and tools
3. Class III (funded organizations) —. They are funded
by big organizations and have access all kind of
resources.
Protection Levels:
1. LEVEL ZERO 6 No special security features. All of
the parts of the device are free to access.
2. LEVEL LOW 0 Some security features are used.
3. LEVEL MODL 0 Secure against most of the low cost
attacks. Attackers need to have more expensive
tools and special knowledge.
4. LEVEL MOD 0 Special tools and equipment are
required as well as special skills and knowledge.
5. LEVEL MODH 0 Special design is considered for
secure device.
6. LEVEL HIGH 0 It is resilient against all known
attacks.
Semi-Invasive Attacks:
Attacks that involve physical intrusion at a system or chip
level. - At the system level, this would mean physical intrusion
into the product enclosure or the tamper protected enclosure
(trusted boundary) in the system (for example, the PCB tamper
mesh). — At the chip level, this would mean physical intrusion
into the device package. Chip-level physical intrusion is not in
the scope of this document and is, therefore, not discussed in
further detail here.
1. Relatively new type of attack, it fills the gap between
non-invasive and invasive attacks
2. Similar to the invasive attacks, they requires
depackaging of the device
3. But, the attacker do not need to have expensive tools
such as FIB‘
4. Actually, these attacks are not entirely new since UV
light is used to disable security fuses, in EPROM for
many years.
Tamper refers to intentional alteration or manipulation to the
system such that it compromises the secrets in the system or
enables unauthorized operation of the system. Designing
systems that are absolutely tamper proof is often not possible
due to the increased cost involved to implement countermeasures
against various known and potentially unknown
attacks (for example, due to constantly improving technology
that increases adversaries' capabilities to carry out an attack,
either in terms of time taken or reduced cost. to perform a
successful attack).
3.1 Prior Art
PATENT US7947911 B1:
"ANTI TAMPER MESH"
The patent describes the concept of reconfigurable Radio
Frequency front end and Antenna arrays for RADAR mode
switching. This feature is achieved through the redundant
Antenna Array built on the PCB. The scope for reconfiguration
limits to the circuit/ antenna array available on the PCB.
4. Brief summary of Invention
The processor or Electronic chip also has interface to a
tamper detection circuitry which shall erase algorithm and
secure codes upon any activity to tamper with
encryption/decryption unit. The crypto processor card is
securely encapsulated with tamper proof mesh PCB’s, upon any physical intrusion or un-authorized opening would trigger
tamper mechanism. Low battery is also treated as tamper event.
5. Brief description of drawings
The foregoing and other features, objects and advancement
of the present invention are apparent over the prior art in the
following more particular description of preferred embodiment of
the invention as illustrated in the form of drawings wherein each
embodiment is represented by a Alphabet.
Figure: 1 shows the EXPLODED VIEW of mesh encapsulated
FRAME,
Figure: 2 shows the Assembled View of FR4 Substrate with their
corresponding frames,
Figure: 3 shows A, B and G are Top, Bottom and Front Battery
Enclosures with their FR4 substrate
Figure: 4 shows C, D, E and F are Left, Right, Rear and Front
Enclosures with their FR4 substrate.
Figure: 5 shows completely assembled and secured Enclosures
with their FR4 substrate mess except battery enclosure with its
mess.
Figure: 6 shows completely assembled and secured Enclosures
with their FR4 substrate mess.
Figure: 7 shows Block diagram of types of Tamper Attacks.
Figure: 8 shows Block diagram for techniques of Tamper.
6. Detailed Description of Invention
Tamper detection: refers to monitoring tamper sensors or
inputs in the system and identifying/qualifying any
abnormalities to indicate a possible tamper event in the
system. Examples include: an ambient light sensor or pressure
sensor within the product enclosure monitored to check if
product enclosure is open or closed, or a vibration sensor to
detect any drilling actions in the system.
Tamper response: refers to the action taken by the system
upon indication of a tamper event. Tamper response typically
takes actions such that the security assets in the system are
not compromised (for example, disable read out or
manipulation of critical information in the system) and the
system is not misused/ modified. Examples include: making the
product non operational, entering a safe mode by disabling
critical operations within the product. It can also involve
indication of tamper event to external systems; for example,
displaying a message on the product screen asking user to take
product to nearest authorized party for further evaluation.
Tamper resistance: refers to the ability of the system to detect
and defend against a threat that has the objective to
compromise the system or the data processed by the system. It
is a measure of time, skill, tools and the knowledge of the
threat (attacker) needed to perform a successful tamper attack.
Semi-Invasive Attacks Counter measures:
1. Additional metallization layers that
0 form a sensor mesh above the actual circuit.
0 do not carry any critical signals
2. All the paths in a sensor mesh are continuously
monitored for interruptions and short-circuits while
power is available
3. It prevents laser cutter or selective etching access to the
bus lines.
4. Also, mesh layer hides the lower layer which makes
navigation on the chip surface for probing and FIB
editing more tedious.
Frames A, B, C, D shown in Fig.3 8:. Fig.4 encloses the FR4 substrate with metal frame, assembled internally mutually
perpendicular with each other to form a rectangular enclosure
Rf which has provision to connect E and F with rear and front side'
of the enclosure respectively.
A battery (I) which is assembled on the (F) Frame coupled
with FR4 substrate provides required power to maintain RTC
(Real Time Cock) and supply to the controller/chip to record the
tamper event during no primary supply. A battery cap which is
made up aluminium alloy with FR4 substrate is also surrounds
the battery (I) to prevent tampering of battery
a A connector which is assembled on the rear end of the frame
used for external communication/ signalling. A provision is made for connecting between H and F, F and I, I and F, F and A,
A and C, C and B, B and D, D and F, F and H succession for
establishing continuity circuit, where in un authorized access
lead to opening of circuit, which in turn results in self—
destruction/erase of data/algorithm. Connectors/copper leads
are used for connecting between two FR4 substrate termination
ends.
The FR4 substrate has provided with two parallel conductive
mesh laid on the nonconductive FR4 substrate with minimal
separation, in a dedicated pattern to avoid the tampering
without de-engaging of the encloser walls. The conductive
tamper mesh laid in between layers surrounded by conductive
dummy layers of ZIG - ZAG pattern to avoid RAY Detection. In
the same fashion tamper proof of battery(1) also attained
meshing all around the battery using FR4 substrate and guided
with battery cap.
We claim:
1. A method of anti tamper encapsulation for secure systems
comprises of layer mesh, metal frame, Printed circuit
Board and Battery.
. A method of anti tamper encapsulation is achieved through
the conductive mesh terminated one end of electronic
device, layer mesh on substrate attached with metal frame,
connecting between H and F, F and I, I and F, F and A, A
and C, C and B, B and D, D and F, F and H succession for
establishing continuity circuit, where in un authorized
access lead to opening of circuit, which in turn results in
self destruction / erase of data/ algorithm.
. The material used for Printed Circuit Board is FR4 and
metal frames are made up of Aluminium alloy.
. ’I‘wo parallel conductive mesh laid on the non conductive
FR4 substrate with minimal separation in a dedicated
pattern to avoid the tampering without de-engaging the
encloser walls.
. Frames A, B, C, D encloses the FR4 substrate with metal
frame are designed to mate directly with working
channels/passages on front and rear side, which is
restricting access in between physically.
. The conductive tamper mesh laid in between layers where
surrounded by conductive dummy layers of ZIG — ZAG
pattern to avoid RAY Detection.
. Tamper proof of battery also attained meshing all around
the battery and guided with battery cap.