Abstract: New emerging areas of large data handling and fast computation have fueled the research and innovation towards quantum computing. By leveraging the principles of quantum mechanics to perform calculations that would be practically impossible for classical computers to solve in a reasonable amount of time. This work presents design of an n-bit Quantum Binary Adder-Subtractor (QBAS) using quantum logic gates using IBM Qiskit. As the fundamental module of abinary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) are designed. Subsequently, these QFAs are analyzed on various aspects to choose the best quantum full adder suitable for QBAS application. Next, a QBAS circuit is designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results show the potential of QBAS in the possible design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The design of the circuits and its results presented here are expected to pave the way for potential design of compact and state of the art quantum adders with optimized number of qubits, quantum cost. 5 Claims & 5 Figures
Description:Field of Invention
The invention presents an efficient methodology for efficient and fast computation intended for complex and big data analysis. Here, quantum full adders (QFAs) are designed using IBM quantum computing tool Qiskit, and the same is extended to implement an n-bit Quantum Binary Adder Subtractor (QBAS). The present innovation demonstrates the power of parallel computing using quantum computing’ superposition efficiency and entanglement property of qubits which facilitates more efficient calculations in wider range of applications like space-physics, novel molecule discovery in medical science, and other computations related to large and complex data sets.
Objectives of the Invention
The objective of the present invention is to demonstrate improved computational efficiency of quantum full adders (QFAs) used in digital circuits over conventional classical binary full adders. The said design is implemented using IBM quantum computing tool Qiskit—an open source powerful and versatile framework for quantum computing developed by IBM. The design and results show here are expected to pave the way for potential design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.
Background of the Invention
Present day digital computers employ digital circuits which work on conventional binary logic for computations. Modern day supercomputers are capable of handling large data, can implement complex algorithm for potential solution of real-time problems, and offer ultrafast computing, also. However, these all still work on classical digital Boolean logic, and looks not suitable for real-world problems having unsorted multivariable dependent / independent variables and more importantly all other problems having exponential time complexity. These classical digital computers also suffer from lack of sufficient parallelism, vast combinational optimization, energy inefficient, and more resource demanding in terms of power and memory. These motivations combined with emergence of new areas have pushed the research and innovation more towards new-age digital devices capable of working on quantum computing over classical computing. Very first study was done by physicist Feynman [1982],International Journal of Theoretical Physics, volume 21, pp. 467–488. The author demonstrated an efficient way to simulate quantum systems using the concept of quantum computing. Subsequently, D. Deutsch [1985], International Journal of Theoretical Physics, volume 24, pp. 1–41, proposed theoretical groundwork for quantum algorithms using the concept of a universal quantum computer.Other significant work on quantum computing includes Shor's algorithm by Peter Shor [1995], SIAM Rev., volume 41, pp. 303-332, and demonstrated the potential of quantum computers to factor large numbers exponentially faster than classical computers. During the last decade of 20th century, researchers made progress in building experimental quantum computing devices, such as ion trap and superconducting qubit-based quantum computers. This was also echoed by significant investing in the development of quantum hardware by worldwide tech-giants like IBM, Google, and Rigetti.
Description of the Prior Art
Conventional computations techniques based on two-valued binary logic, which are the foundation of classical computing, face several limitations and problems when it comes to certain types of calculations and problem-solving tasks. Earlier works exploring the potential of quantum computing were done including fundamental research, research paper publications, patents, and experimental work that laid the groundwork for the current state of quantum computing.Theoretical foundations concepts in quantum mechanics, such as superposition and entanglement, were established in the early 20th century by physicists like Max Planck, Niels Bohr, and Erwin Schrödinger. These first principles concepts were widely used by researchers for potential quantum computing. This was followed by notable research publications byFeynman ‘Simulating Physics with Computers’ [1982], David Deutsch's authored ‘Universal Quantum Computer’[1985], ‘Shor's Algorithm’by Peter Shor[1994], Grover's Algorithm published by Lov Grover [1996], and experimental quantum computing hardware which notably includes ion trap and superconducting qubit-based quantum computers. Leveraging the quantum mechanics principles, during the years 1900 – 2000, Charles Bennett and Gilles Brassard developed quantum key distribution (QKD) protocols, such as BB84, which ensure secure communication. Other significant development in the journey of quantum computing includes development of open-source quantum software frameworks like IBM Qiskit and Google Cirq. These resources have offered a crucial help in making quantum computing accessible and fostering collaboration in the field.Other notable milestones in field of quantum computing include IBM’s patent for a quantum computer [2001], US Patent 6,536,440. Early quantum patents were awarded to D-Wave Systems, founded in 1999, have multiple patents in the field. In year 2019, Google secured patent for its 53-qubit quantum processor, Sycamore. Rigetti Computing [2013], has developed its quantum processors and holds various patents in quantum computing technologies.
Summary of the Invention
The present invention offers novel design of a quantum full adder (QFA) and its application in designing of n-bit Quantum Binary Adder Subtractor (QBAS).
In one aspect, this work presents a novel design of an efficient QFA using IBM Qiskit, intended for quantum computing. QFA designs are analyzed based on parameters such as the quantum cost (QC) and number of ancillae or garbage, and execution time.
In another aspect, this work presents a novel design of an efficient n-bit QBAS, intended for quantum computing.
In another aspect, the present work presents circuit analysis of 2, 4, 8-bit QBAS, and n-bit QBAS.
In another aspect, an efficient n-bit quantum binary adder-subtractor with reduced quantum cost is designed.
Detailed description of the Invention
A qubitis the fundamental unit of quantum computing and is analogous to the bit in classical computing. The constraints of a qubit are similar to those of a bit, they can store only one binary state, either 0 or 1. However, qubits obey the laws of quantum mechanics which allow them to exhibit a behavior indifferent to that of classical bits. The state of a qubit can be represented in various ways, however, the widely used are the Dirac or the Bra-Ket notation.
|0?= [¦(1@0)] and |1?= [¦(0@1)] (1)
Quantum logic gates are the building blocks of quantum circuits. Various quantum logic gates, each of which has its unique set of operations and its own state transition matrix,are used to compute the state of the qubits at the output. Quantum logic gates are broadly classified into Clifford and Non-Clifford gates. Clifford gates are the ones which can be derived by using only the Hadamard, Phase and CNOT gates.
Thequantum full adder (QFA) circuit design employs two cascaded Peres gates. This architecture is collectively termed as the Peres Full Adder Gate (PFAG).A total of 4 qubits are required to realize this design, of which two are for the desired outputs (sum and carry) and the rest are garbage outputs. This design incorporates only one constant input. The carry and sum are generated at the third and the fourth qubit respectively. It is worth noting that thesecond qubit generates the half adder sum which can be useful in the design of circuits like parity generators. The quantum cost of a Peres gate is 4 in its most optimum realization. Hence, the total quantum cost of the designed PFAG is 8.
Using the design of the classical n-bit binary adder-subtractor, quantum binary adder-subtractor is designed. Theclassical n-bit binary adder-subtractor contains a cascade of nfull adders. Each full adder (FA) module has three inputs which Ai, CTRLBi and Ci.Aiand Bi are the ithbits of the input binary numbers.The input Ci is the carry generated in the pervious full addermodule but C0 is taken from the CTRL (control) input. Eachof FA module gives two outputs Si and Ci+1. Si is the ith bitof the resultant sum and Ci+1 is fed to the next FA moduleuntil the last FA module in the cascade giving Cout which isthe resultant carry.A binary adder-subtractor circuit is capable of both additionand subtraction of binary numbers. The desired operation iscontrolled with the help of a control input. The two different cases are given by following equations.
Case 1: CTRL=0
B_0?CTRL=B_0?0=B_0
C_0=CTRL=0
S_0=A_0?(B_0?CTRL)?C_0= A_0?B_0
C_1= A_0 B_0+ B_0 C_0+C_0 A_0=A_0 B_0
S0 and C1 are the required sum and carry outputs of the first FA module which acts as an adder in this setup.
Case 2: CTRL=1
B_0?CTRL=B_0?1=(B_0 ) ¯
C_0=CTRL=1
S_0=A_0?(B_0?CTRL)?C_0= A_0?(B_0 ) ¯?1
C_1= A_0 B_0+ B_0 C_0+C_0 A_0=A_0 B_0+B_0+A_0
S0 and C1 are the required difference and borrow outputs ofthe first FA module which acts as a subtractor in the present design.The difference results from the addition of A0and 2’scomplement of B0.The quantumversion of the n-bit binary adder-subtractor circuit isconstructed using QFAs. A circuit is only as fast as itsmodules; therefore, it makes sense to employ the fastestmodules, QFAs in case of quantum n-bit binary adder-subtractor. The PFAG is preferred for this applicationprimarily due to factors such as low quantum cost, fasterexecution time and lesser number of qubits and ancillae.
The inputs to a n-bit QBAS circuit are two n-bit binary stringor numbers and the control. The control input is standalonequbit whereas the two n-bit binary inputs will be treated asquantum registers with n qubits each. The output of thedesigned circuit is an n-bit binary number which is equal tothe sum or the difference of the inputs which will regarded asn-bit classical register and a bit denoting the carry-out orborrow-out depending upon the control input. In addition, thedesigned circuit requires constant input qubits, considered asan n-bit binary zero quantum register. The circuit is builtaround the quantum and classical registers.This is implemented in Qiskit as follows:
a = QuantumRegister(n,'A')
b = QuantumRegister(n,'B')
z = QuantumRegister(n,'Z')
c = QuantumRegister(n,'C')
ctrl = QuantumRegister(1,'CTRL')
s = ClassicalRegister(n,'S')
carry = ClassicalRegister(1,'Carry')
qc = QuantumCircuit(a,ctrl,b,z,c,s,carry)
Brief description of Drawing
The figures accompanied here areincluded to provide further understanding of the present invention. The drawings illustrate exemplary embodiments of the invention.
Figure 1 Design of quantum full adder (QFA) using Peres Gates.
Figure 2 Qiskit Implementation of QFA using Peres Gates.
Figure 3Design of QFA based on Qubit State Reuse.
Figure 4Qiskit Implementation of QFA based on Qubit State Reuse.
Figure 5Design of n-bit Quantum Binary Adder-Subtractor Circuit Design.
Detailed description of the drawing
As described above the present invention relates to copyright fetching.
Figure 1 shows the Design of quantum full adder (QFA) using Peres Gates.This QFA circuit employs two cascaded Peres gates. This architecture is collectively termed as the Peres Full Adder Gate (PFAG).
Figure 2 illustrates the Qiskit Implementation of QFA using Peres Gates.Full implementation of he PFAG using IBM Qiskit is shown in this figure.
Figure 3.shows the Design of QFA based on Qubit State Reuse.The circuit diagram employs five CNOT gates and two CCNOT gates.
Figure 4.illustrates the Qiskit Implementation of QFA based on Qubit State Reuse.Five qubits are used to realize this QFA with three garbage outputs and two desired outputs. Two constant inputs are used in this circuit which serve as the output lines for sum and carry.
Figure 5. displays the Design of n-bit Quantum Binary Adder-Subtractor Circuit Design. The 2-CNOT version is implemented is IBM Qiskit shown, the MAJ gate and UMA gate are clearly distinguished with help of barriers.
5 Claims & 5 Figures , Claims:The scope of the invention is defined by the following claims:
Claims:
1. A novel methodology of n-bit Quantum Binary Adder Subtractor (QBAS), comprising
a) Implementation of quantum full adder (QFA) using IBM Qiskit;
b) QFA is analyzed for quantum cost and execution time;
c) Quantum Binary Adder Subtractor (QBAS) is designed using QFA designed earlier;
d) Quantum Binary Adder Subtractor (QBAS) is analyzed for quantum cost and execution time.
2. As per claim 1 (b), execution time of 3.443 ms is estimated for quantum full adder (QFA) using Peres gates.
3. As mentioned in claim 1, the combined quantum cost of fiveFeynman gates and two Toffoli gates is 15.
4. As per the claim 1, the quantum cost of a Peres gate is 4 in its most optimum realization.
5. As mentioned in claim 1,the total quantum cost of the designed PFAG is 8.
| # | Name | Date |
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| 1 | 202341066781-REQUEST FOR EARLY PUBLICATION(FORM-9) [05-10-2023(online)].pdf | 2023-10-05 |
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| 8 | 202341066781-EDUCATIONAL INSTITUTION(S) [05-10-2023(online)].pdf | 2023-10-05 |
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