Description:FIELD OF THE INVENTION
[001] The present invention generally relates to integrated circuits. More particularly, the present invention relates to provision of an inverter circuit.

BACKGROUND OF THE INVENTION
[002] Generally, a transistor is an electronic component that is used in several electronic devices. The transistor is configured to be used in circuits and it helps in controlling the flow of the current and the voltage in the circuits. The transistor is usually used as a switch, to achieve amplification, and the like. One of the most commonly used transistors is a Field Effect Transistor (FET). The FET controls the voltage across the circuits. A Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is a type of FET and is configured to be provided with an insulated gate terminal.
[003] As is commonly known, MOSFETs are used in high power inverter, converter, motor-drive applications, and the like. Due to high power levels and faster switching, there can be fast transients as the circuit and the electronic devices contain parasitic capacitances (Cgd) and inductances. Mainly, the sudden change in the voltage (dV) in a short span of time (dt) causes a short-circuit by falsely turning on the lower device in a half bridge when already the upper device is in ON state. The sudden increase in the voltage across the drain-source terminal (Vds) results in the current through the parasitic capacitance (Cgd) or a miller capacitance (Cge) located inside the MOSFET, taking the path through the gate resistor and driver. This current is known as a miller current. The miller current induces a voltage at the gate terminal of the MOSFET. If the voltage drop is larger than the gate terminal threshold voltage, then the electronic device could turn ON causing a short-circuit.
[004] Therefore, it is important to avoid the false turn ON of the bottom MOSFET in a complimentary switching MOSFET topology. Conventionally, a miller clamp driver circuit is used in the circuit that redirects the current due to the sudden change in dv/dt. However, the driver circuit involves a lot of components which increases the overall cost and occupies a lot of space as well and therefore, is undesirable. Hence, there is a need to provide a circuit that solves the problems related to ease of serviceability, performance, safety, cost reduction, and the like.
[005] Thus, there is a need in the art for an inverter circuit, which addresses at least the aforementioned problems.

SUMMARY OF THE INVENTION
[006] In one aspect, the present invention is directed towards an inverter circuit. The inverter circuit comprises a battery source configured to provide a voltage and a current to the inverter circuit. The inverter circuit further has one or more phases configured to be provided in parallel to each other and connected to the battery source and a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The plurality of MOSFETs comprises a first MOSFET and a second MOSFET. The plurality of MOSFETs being configured to be provided in each of the one or more phases. Further, the inverter circuit includes a protection circuit configured to be connected to one of the first MOSFET and the second MOSFET, thereby avoiding a short circuit.
[007] In an embodiment of the invention, the protection circuit has a first protection MOSFET, a second protection MOSFET, a first resistor, a second resistor, a R gate resistor and a voltage source.
[008] In a further embodiment of the invention, the voltage source is 5V.
[009] In a further embodiment of the invention, a drain terminal of the first protection MOSFET being configured to be connected to a gate terminal of the second protection MOSFET.
[010] In a further embodiment of the invention, a gate terminal of the first protection MOSFET is configured to be connected to a gate terminal of the second MOSFET, and the first protection MOSFET is regulated by the gate terminal of the second MOSFET.
[011] In a further embodiment of the invention, a drain terminal of the second protection MOSFET is configured to be connected to the gate terminal of the second MOSFET.
[012] In a further embodiment of the invention, the R gate resistor is configured to be connected between the gate terminal of the second MOSFET and the second protection MOSFET.
[013] In a further embodiment of the invention, the first resistor is configured to be connected in series with the first protection MOSFET.
[014] In a further embodiment of the invention, the first resistor is configured to be connected across the gate terminal of the second MOSFET and the gate terminal of the first protection MOSFET.
[015] In a further embodiment of the invention, the second resistor is configured to be connected in series with the voltage source.
[016] In a further embodiment of the invention, the gate terminal of the second protection MOSFET is configured to be connected with the voltage source.

BRIEF DESCRIPTION OF THE DRAWINGS
[017] Reference will be made to embodiments of the invention, examples of which may be illustrated in accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.
Figure 1 illustrates a schematic diagram of an inverter circuit, in accordance with an embodiment of the present invention.
Figure 2 illustrates a schematic diagram of a protection circuit, in accordance with an embodiment of the present invention.
Figure 3 illustrates a schematic diagram of the protection circuit, in accordance with an embodiment of the present invention.
Figure 4 illustrates a graphical representation of the voltage for the second MOSFET, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION
[018] The present invention generally relates to integrated circuits. More particularly, the present invention relates to provision of an inverter circuit. The present invention provides for an active gate clamp in complementary switching Metal Oxide Semiconductor Field Effect Transistor (MOSFET) topology.
[019] Figure 1 illustrates a schematic diagram of an inverter circuit 100, in accordance with an embodiment of the present invention. The inverter circuit 100 is responsible for converting the direct current (DC) voltage to an alternating current (AC) voltage in the electronic devices. In an embodiment of the present invention, the inverter circuit 100 is provided with a battery source V. The battery source V is configured to provide the voltage and the current to the inverter circuit 100. As depicted in Figure 1, the inverter circuit 100 comprises one or more phases P1, P2, P3. The one or more phases P1, P2, P3 includes a first phase P1, a second phase P2 and a third phase P3. In an embodiment of the present invention, the first phase P1 corresponds to a red phase. The second phase P2 corresponds to a yellow phase and the third phase corresponds to a blue phase. The phases P1, P2, P3 are separated by an angle of 120 degrees.
[020] In an embodiment, the one or more phases P1, P2, P3 are configured to be provided in parallel to each other. Also, the one or more phases P1, P2, P3 are configured to be connected to the battery source V. The inverter circuit 100 further includes a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The plurality of MOSFETs has a first MOSFET M’ and a second MOSFET M’’. The plurality of MOSFETs M’, M’’ are configured to be provided in each of the one or more phases P1, P2, P3. In an embodiment, the first MOSFET M’ and the second MOSFET M’’ are provided in the first phase P1. Similarly, the first MOSFET M’ and the second MOSFET M’’ are provided in the second phase P2 and the third phase P3 as well. Therefore, the first MOSFET M’ and the second MOSFET M’’ are responsible for each of the phases P1, P2, P3 in which they are connected.
[021] In an aspect and as depicted in Figure 2, the inverter circuit 100 is further provided with a protection circuit 200. The protection circuit 200 is configured to protect the electronic devices from short circuit conditions. The protection circuit 200 is configured to be connected to one of the first MOSFET M’ and the second MOSFET M’’, thereby avoiding a short circuit condition. In an embodiment, the protection circuit 200 is configured to be connected to the second MOSFET M’’. Particularly, the protection circuit 200 is meant to be connected across the gate terminal Vgate of the second MOSFET M’’ in each of the phases P1, P2, P3. The inverter circuit 100 has three phases P1, P2, P3, and the protection circuit 200 is in place for each of the three phases P1, P2, P3 for the second MOSFET M’’.
[022] In a further embodiment of the present invention, the protection circuit 200 has a first protection MOSFET M1, a second protection MOSFET M2, a first resistor R1, a second resistor R2, a R gate resistor Rgate and a voltage source Vcc. In an embodiment, the voltage source Vcc is 5V.
[023] Further, as depicted in Figure 3, the first protection MOSFET M1 has a drain terminal D1, a gate terminal G1 and a source terminal S1. Similarly, the second protection MOSFET M2 has a drain terminal D2, a gate terminal G2 and a source terminal S2. The drain terminal D1 of the first protection MOSFET M1 is configured to be connected to a gate terminal G2 of the second protection MOSFET M2. Further, the gate terminal G1 of the first protection MOSFET M1 is configured to be connected to a gate terminal Vgate of the second MOSFET M’’. In an embodiment, the first protection MOSFET M1 is regulated by the gate terminal Vgate of the second MOSFET M’’. Further, the drain terminal D2 of the second protection MOSFET M2 is configured to be connected to the gate terminal Vgate of the second MOSFET M’’.
[024] In an embodiment, the R gate resistor Rgate is configured to be connected between the gate terminal Vgate of the second MOSFET M’’ and the second protection MOSFET M2. The first resistor R1 is configured to be connected in series with the first protection MOSFET M1. The first resistor R1 is configured to be connected across the gate terminal Vgate of the second MOSFET M’’ and the gate terminal G1 of the first protection MOSFET M1. The second resistor R2 is configured to be connected in series with the voltage source Vcc. In yet another embodiment of the present disclosure, the gate terminal G2 of the second protection MOSFET M2 is configured to be connected with the voltage source Vcc.
[025] In an embodiment, the protection circuit 200 is responsible for protecting the inverter circuit 100 from false turn ON of the second MOSFET M’’ in cases, wherein the first MOSFET M’ is already in ON state. In the present invention, when the second MOSFET M’’ gate signal is OFF, the first protection MOSFET M1 remains in the OFF state and the second protection MOSFET M2 turns ON, thereby shorting the gate terminal Vgate to the source terminal i.e., ground. This avoids any chance of the false turn ON of the second MOSFET M’’. The protection circuit 200 is used in inverters, DC-DC converters in electric vehicles, and the like. The present invention is advantageous as it involves lesser number of components, and the gate terminal Vgate is already grounded during OFF state and deadtime of the second MOSFET M’’.
[026] In an embodiment of the present invention, since the gate terminal Vgate of the second MOSFET M’’ is shorted to ground during the deadtime with lesser number of components, thereby it avoids any voltage or current stress in the inverter circuit 100.
[027] As depicted in Figure 2 and Figure 3, when the gate terminal signal Vgate of the second MOSFET M’’ is HIGH = 1, i.e., in normal condition, the first protection MOSFET M1 turns ON, thereby shorting the gate terminal G2 of the second protection MOSFET M2 to ground, thereby turning the second protection MOSFET M2 in an OFF state. Therefore, when Vgate = 1, the second MOSFET M’’ is turned ON.
[028] In yet another embodiment of the present disclosure, when the gate terminal signal Vgate of the second MOSFET M’’ is LOW = 0, i.e., the case when the first MOSFET M’ is already in ON state and when the false turn ON of the second MOSFET M’’ may happen, thereby creating a short circuit situation. In this condition, the first protection MOSFET M1 is turned OFF and the second protection MOSFET M2 is turned ON, thereby shorting the gate terminal Vgate of the second MOSFET M’’ to the source terminal i.e., ground. This avoids any chance of the false turn ON of the second MOSFET M’’.
[029] In an exemplary embodiment of the present invention, whenever the first MOSFET M’ is in ON state, the second MOSFET M’’ is supposed to be in the OFF state to prevent the short circuit problems. However, when the first MOSFET M’ is in the ON state, there is 52 V across the inverter circuit 100. This voltage generates miller capacitance, which induces voltage at the gate terminal Vgate of the second MOSFET M’’. If the voltage drop is larger than the gate terminal threshold voltage, then the electronic device is turned ON causing a short circuit. If both the first MOSFET M’ and the second MOSFET M’’ are ON, the 52V is directly grounded. This leads to an unsafe condition due to the high voltage and current being directly grounded. Therefore, the protection circuit 200 is introduced at the second MOSFET M’’ of the inverter circuit 100.
[030] The input to the protection circuit 200 is the Vgate voltage given to the second MOSFET M’’. When Vgate = 1 (which is around 12V), the first protection MOSFET M1 is turned ON. This shorts the 5V to ground and lets the 12V directly go to the second MOSFET M’’ as desired. When Vgate = 0 (which is when the miller current is generated), the second protection MOSFET M2 is turned ON and the first protection MOSFET M1 is turned OFF. Therefore, since the second protection MOSFET M2 is turned ON, the current flowing towards the second MOSFET M’’ (which is undesirable if Vgate = 0) is directly grounded. Therefore, the second MOSFET M’’ is safeguarded from the false miller current being induced and will only turn ON and OFF depending on the gate terminal Vgate value.
[031] Following is a detailed example of the present disclosure. The components utilized include a second MOSFET M’’, Gate clamp MOSFETs i.e., a first protection MOSFET M1 and a second protection MOSFET M2, a Gate Terminal of second MOSFET Vgate, a Gate resistor Rgate, and a first Resistor R1 and a second Resistor R2. In an example, consider that R gate resistor Rgate is 10 ohms, the first Resistor R1 and the second Resistor R2 is 100 ohms each, and Voltage threshold for false turn ON prevention is 2V.
[032] Then, in a normal condition, when Vgate is HIGH:
• The First Protection MOSFET M1 turns ON, shorting the gate terminal of M2 to ground.
• The Second Protection MOSFET M2 turns OFF, allowing the gate signal to pass through the second MOSFET M’’.
• The second MOSFET M’’ receives a HIGH gate signal (e.g., 10V), turning it ON as intended.
[033] In an abnormal condition, when Vgate is LOW i.e., during False Turn-On Prevention:
• The gate terminal Vgate of the second MOSFET M’’ is LOW (e.g., 0V).
• The first protection MOSFET M1 turns OFF, preventing the gate signal from reaching the second MOSFET M’’.
• The second protection MOSFET M2 turns ON, shorting the gate terminal of the second MOSFET M’’ to ground.
• The voltage drop across the first resistor R1 and the second resistor R2 (considering 200 ohms in total) due to the current flow during the abnormal condition is limited to 2V (threshold).
• For the first resistor R1 and the second resistor R2 in series: Vdrop=IMiller X (R1 + R2)
• If Vdrop>2V, then the false turn ON prevention mechanism is activated.
[034] In this example, the proposed gate clamp circuit with specific component values ensures that during normal operation, the second MOSFET M’’ receives the intended gate signal. In abnormal conditions, the gate is effectively shorted to ground, preventing false turn ON by limiting the voltage drop across the first resistor R1 and the second resistor R2.
[035] Figure 4 illustrates a graphical representation 300 of the voltage for the second MOSFET, in accordance with an embodiment of the present invention. As shown in Figure 4, the voltage across the gate terminal and the source terminal of the second MOSFET M’’ corresponds to the value and the condition of the Vgate as described above. Hence, the protection circuit 200 helps in avoiding the situations related to the short circuit of the electronic devices.
[036] Advantageously, the present invention provides for an inverter circuit in which a protection circuit is provided with the second MOSFET. The protection circuit helps in avoiding the short circuit conditions and therefore, is safe and reliable. Furthermore, the present invention improves the overall performance of the inverter circuit. The present invention provides for ease of serviceability as the overall components have been reduced in the present invention. Due to the lesser number of the components used in the circuit, the overall cost has been reduced as well. Therefore, the present invention provides safety and is efficient as compared to the conventional integrated circuits.
[037] The location of the protection circuit allows for better performance and durability of the inverter circuit, which lowers servicing and replacement costs of the associated parts of the electronic devices. Further, conventionally since a lot of components occupied more space, the present invention makes more packaging space available for other more suitable components of the electronic devices. Further, the integration of the protection circuit with the inverter circuit as described in the present invention makes the assembly easier and less sophisticated.
[038] The present disclosure and the claimed invention involve a specific circuit design and configuration to address a practical problem in complementary switching MOSFET topologies, particularly in high-power inverter, converter, and motor-drive applications. The present disclosure introduces concrete tangible components (MOSFETs, resistors) and describes their specific interactions and behaviours under normal and abnormal conditions. The present disclosure and the claimed invention provide a technical solution to prevent false turn ON of the bottom MOSFET during certain conditions, which is a practical problem in high-power electronics.
[039] The claimed invention introduces a specific gate clamp circuit involving two MOSFETs (M1 and M2) and resistors (R1 and R2) to prevent false turn ON. The use of a dual MOSFET arrangement for gate clamping during specific conditions adds a layer of complexity that goes beyond conventional solutions. The claimed invention addresses the specific challenges associated with fast transients, dv/dt-induced short circuits, and the limitations of prior art solutions.
[040] In view of the above, the present disclosure and the claimed invention is non-abstract as it involves a specific and tangible circuit design to address practical challenges in complementary switching MOSFET topologies. The non-obviousness is supported by the introduction of a specific configuration and the detailed working examples illustrated above.
[041] While the present invention has been described with respect to certain embodiments, it will be apparent to those skilled in the art that various changes and modification may be made without departing from the scope of the invention as defined in the following claims.

List of Reference Numerals
100: Inverter Circuit
200: Protection Circuit
V: Battery Source
P1, P2, P3: One or More Phases
P1: First Phase
P2: Second Phase
P3: Third Phase
M’: First MOSFET
M’’: Second MOSFET
M1: First Protection MOSFET
M2: Second Protection MOSFET
R1: First Resistor
R2: Second Resistor
Rgate: R gate resistor
Vgate: Gate Terminal of M’’
Vcc: Voltage Source
D1: Drain Terminal of M1
G1: Gate Terminal of M1
S1: Source Terminal of M1
D2: Drain Terminal of M2
G2: Gate Terminal of M2
S2: Source Terminal of M2
, Claims:WE CLAIM:
1. An inverter circuit (100), comprising:
a battery source (V), the battery source (V) being configured to provide a voltage and a current to the inverter circuit (100);
one or more phases (P1, P2, P3), the one or more phases (P1, P2, P3) being configured to be provided in parallel to each other and connected to the battery source (V);
a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), the plurality of MOSFETs comprising a first MOSFET (M’) and a second MOSFET (M’’), and the plurality of MOSFETs being configured to be provided in each of the one or more phases (P1, P2, P3); and
a protection circuit (200), the protection circuit (200) being configured to be connected to one of the first MOSFET (M’) and the second MOSFET (M’’), thereby avoiding a short circuit.

2. The inverter circuit (100) as claimed in claim 1, wherein the protection circuit (200) comprises a first protection MOSFET (M1), a second protection MOSFET (M2), a first resistor (R1), a second resistor (R2), a R gate resistor (Rgate) and a voltage source (Vcc).

3. The inverter circuit (100) as claimed in claim 2, wherein the voltage source (Vcc) is 5V.

4. The inverter circuit (100) as claimed in claim 2, wherein a drain terminal (D1) of the first protection MOSFET (M1) being configured to be connected to a gate terminal (G2) of the second protection MOSFET (M2).

5. The inverter circuit (100) as claimed in claim 2, wherein a gate terminal (G1) of the first protection MOSFET (M1) being configured to be connected to a gate terminal (Vgate) of the second MOSFET (M’’), and the first protection MOSFET (M1) being regulated by the gate terminal (Vgate) of the second MOSFET (M’’).

6. The inverter circuit (100) as claimed in claim 5, wherein a drain terminal (D2) of the second protection MOSFET (M2) being configured to be connected to the gate terminal (Vgate) of the second MOSFET (M’’).

7. The inverter circuit (100) as claimed in claim 5, wherein the R gate resistor (Rgate) being configured to be connected between the gate terminal (Vgate) of the second MOSFET (M’’) and the second protection MOSFET (M2).

8. The inverter circuit (100) as claimed in claim 2, wherein the first resistor (R1) being configured to be connected in series with the first protection MOSFET (M1).

9. The inverter circuit (100) as claimed in claim 5, wherein the first resistor (R1) being configured to be connected across the gate terminal (Vgate) of the second MOSFET (M’’) and the gate terminal (G1) of the first protection MOSFET (M1).

10. The inverter circuit (100) as claimed in claim 2, wherein the second resistor (R2) being configured to be connected in series with the voltage source (Vcc).

11. The inverter circuit (100) as claimed in claim 4, wherein the gate terminal (G2) of the second protection MOSFET (M2) being configured to be connected with the voltage source (Vcc).

Dated this 29th day of November 2023
TVS MOTOR COMPANY LIMITED
By their Agent & Attorney

(Nikhil Ranjan)
of Khaitan & Co
Reg No IN/PA-1471