1. A processor, comprising:
decode circuitry to decode an instruction to perform a direct memory access
(DMA) operation, wherein the instruction comprises an opcode and one or more
fields, wherein the opcode indicates a type of DMA operation to be performed, and
wherein the one or more fields indicate:
a destination memory region; and
one or more data operands; and
memory offload circuitry to offload the instruction from an execution
pipeline, wherein the memory offload circuitry is to perform the DMA operation
based on the opcode and the one or more fields.
2. The processor of Claim 1, wherein the one or more fields further indicate:
a compute operation to be performed on the one or more data operands,
wherein one or more resulting data operands are to be written to the destination
memory region.
3. The processor of Claim 2, wherein the compute operation comprises:
a complement operation;
a bitwise operation;
an add operation; or
a multiply operation.
4. The processor of any of Claims 2-3, wherein the compute operation is to be
performed on at least one data operand from a source memory region and at least
one data operand from the destination memory region.
5. The processor of any of Claims 2-4, wherein the one or more fields comprise
a DMA type field, wherein the DMA type field indicates the compute operation to
be performed.
79 INTL-8091-IN
6. The processor of any of Claims 1-5, wherein:
the DMA operation is to read from or write to a non-contiguous memory
region, wherein the non-contiguous memory region is a source memory region or
the destination memory region.
7. The processor of any of Claims 1-5, wherein the instruction is a DMA
initialize instruction, wherein the DMA initialize instruction is to initialize the
destination memory region with data.
8. The processor of any of Claims 1-5, wherein the instruction is a DMA
initialize stride instruction, wherein the DMA initialize stride instruction is to
initialize the destination memory region with data, wherein the destination memory
region is a strided memory region.
9. The processor of any of Claims 1-5, wherein the instruction is a DMA copy
stride instruction, wherein the DMA copy stride instruction is to copy data from a
source memory region to the destination memory region, wherein at least one of the
source memory region or the destination memory region is a strided memory region.
10. The processor of any of Claims 1-5, wherein the instruction is a DMA
scatter instruction, wherein the DMA scatter instruction is to scatter data across the
destination memory region, wherein the destination memory region is a noncontiguous memory region.