Power Conversion Device

Abstract: A first controller (40) comprises a first processor and a first memory. A second controller (50) comprises a second processor and a second memory. When transmitting data from the first controller (40) to the second controller (50), the first controller (40) repeatedly executes an operation of writing the transmission data to the first memory according to a clock signal, and reads out the transmission data from the first memory for output to a communication line. The second controller (50) writes received data, which is received from the communication line, into the second memory according to the clock signal, and reads out the received data from the second memory according to the clock signal. The second controller (50) transfers a data value in a current clock cycle to the second processor if a plurality of data values in a plurality of consecutive clock cycles, including the current clock cycle, match in the read received data.

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