Description:FORM 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENT RULES, 2003
(See Section 10 and Rule 13)

Title of invention:
METHOD AND SYSTEM FOR DEPTH REDUCTION OF QUANTUM CIRCUITS

Applicant:
Tata Consultancy Services Limited
A company Incorporated in India under the Companies Act, 1956
Having address:
Nirmal Building, 9th Floor,
Nariman Point, Mumbai 400021,
Maharashtra, India

The following specification particularly describes the invention and the manner in which it is to be performed.
TECHNICAL FIELD
The disclosure herein generally relates to quantum computing, and, more particularly, to a method and system for depth reduction of quantum circuits.

BACKGROUND
Quantum computing has the potential for solving problems that are complex in nature, and are difficult for classical computers to solve. For example, quantum computing can be used for applications such as but not limited to option pricing calculations. Quantum computing uses laws of quantum mechanics for solving the problems. Depending on complexity of task to be executed, a quantum circuit being used may have different combinations of quantum gates. Depth of a quantum circuit is the longest path in the directed acyclic graph representation of the quantum circuit. As complexity of the task increases, depth of the quantum circuit could proportionately increase.
Quantum computing is currently in the Noisy Intermediate-Scale Quantum(NISQ) era wherein quantum executions suffer from the impact of noise. The noise introduced in a quantum execution scales with the depth of a quantum circuit. Which means, the impact of noise could be pronounced with increase in complexity of tasks being executed, thus adversely affecting quality of results.

SUMMARY
Embodiments of the present disclosure present technological improvements as solutions to one or more of the above-mentioned technical problems recognized by the inventors in conventional systems. For example, in one embodiment, a processor implemented method is provided. The method includes: receiving, via one or more hardware processors, a quantum circuit with n qubits as input; extracting, via the one or more hardware processors, a plurality of circuit data associated with the quantum circuit; and iteratively processing each of the n qubits, via the one or more hardware processors, comprising: selecting a qubit from among the n qubits, in each iteration; extracting a plurality of gates applied on the selected qubit; determining by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates, wherein the at least one D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z}; extracting a preceding gate and a succeeding gate of the at least one D gate; and removing the succeeding gate and including effect of the succeeding gate in the preceding gate by doubling the rotation angle of the preceding gate, if a set of conditions comprising a) the preceding gate and the succeeding gate are R_c gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z, is satisfied, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate, wherein by removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits causes depth reduction of the quantum circuit.
In an embodiment of the method, the iteration through remaining preceding gate – succeeding gate pairs in the plurality of preceding gate – succeeding gate pairs is terminated if the set of conditions is not satisfied for any of the preceding gate – succeeding gate pairs.
In another embodiment of the method, the depth reduction is caused for the quantum circuit received as input, if a pre-defined circuit pattern is present in the extracted plurality of circuit data of the quantum circuit.
In another embodiment, a system is provided. The system includes one or more hardware processors, a communication interface, and a memory storing a plurality of instructions. The plurality of instructions cause the one or more hardware processors to: receive a quantum circuit with n qubits as input; extract a plurality of circuit data associated with the quantum circuit; and iteratively process each of the n qubits, comprising: selecting a qubit from among the n qubits, in each iteration; extracting a plurality of gates applied on the selected qubit; determining by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates, wherein the at least one D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z}; extracting a preceding gate and a succeeding gate of the at least one D gate; and removing the succeeding gate and including effect of the succeeding gate in the preceding gate by doubling the rotation angle of the preceding gate, if a set of conditions comprising a) the preceding gate and the succeeding gate are R_c gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z, is satisfied, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate, wherein by removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits causes depth reduction of the quantum circuit.
In an embodiment of the system, the one or more hardware processors are configured to terminate the iteration through remaining preceding gate – succeeding gate pairs in the plurality of preceding gate – succeeding gate pairs, if the set of conditions is not satisfied for any of the preceding gate – succeeding gate pairs.
In another embodiment of the system, the one or more hardware processors are configured to cause the depth reduction for the quantum circuit received as input, if a pre-defined circuit pattern is present in the extracted plurality of circuit data of the quantum circuit.
In yet another aspect, a non-transitory computer readable medium is provided. The non-transitory computer readable medium includes a plurality of instructions which when executed, cause the one or more hardware processors to: receive a quantum circuit with n qubits as input; extract a plurality of circuit data associated with the quantum circuit; and iteratively process each of the n qubits, by: selecting a qubit from among the n qubits, in each iteration; extracting a plurality of gates applied on the selected qubit; determining by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates, wherein the at least one D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z}; extracting a preceding gate and a succeeding gate of the at least one D gate; and removing the succeeding gate and including effect of the succeeding gate in the preceding gate by doubling the rotation angle of the preceding gate, if a set of conditions comprising a) the preceding gate and the succeeding gate are R_c gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z, is satisfied, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate, wherein by removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits causes depth reduction of the quantum circuit.
In an embodiment of the non-transitory computer readable medium, the iteration through remaining preceding gate – succeeding gate pairs in the plurality of preceding gate – succeeding gate pairs is terminated if the set of conditions is not satisfied for any of the preceding gate – succeeding gate pairs.
In another embodiment of the non-transitory computer readable medium, the depth reduction is caused for the quantum circuit received as input, if a pre-defined circuit pattern is present in the extracted plurality of circuit data of the quantum circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles:
FIG. 1 illustrates an exemplary system for depth reduction of quantum circuit, according to some embodiments of the present disclosure.
FIGS. 2A and 2B (collectively referred to as FIG. 2), is a flow diagram depicting steps involved in the process of depth reduction of quantum circuit, using the system of FIG. 1, according to some embodiments of the present disclosure.
FIGS. 3A and 3B are example quantum circuit diagrams used to illustrate the quantum circuit depth reduction being performed by the system of FIG. 1, in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS
Exemplary embodiments are described with reference to the accompanying drawings. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. Wherever convenient, the same reference numbers are used throughout the drawings to refer to the same or like parts. While examples and features of disclosed principles are described herein, modifications, adaptations, and other implementations are possible without departing from the scope of the disclosed embodiments.
Quantum computing is currently in the Noisy Intermediate-Scale Quantum(NISQ) era wherein quantum executions suffer from the impact of noise. The noise introduced in a quantum execution scales with the depth of a quantum circuit. Which means, the impact of noise could be pronounced with increase in complexity of tasks being executed, thus adversely affecting quality of results.
In order to address this challenge, method and system disclosed herein provide a depth reduction approach, which involves the following steps. In this method, a quantum circuit with n qubits is received as input. Further, a plurality of circuit data associated with the quantum circuit are extracted. Further, each of the n qubits is iteratively processed. The iterative processing of each of the n qubits involves the following steps. Initially, a qubit from among the n qubits is selected in each iteration. Further, a plurality of gates applied on the selected qubit are extracted. Further, by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates is determined, wherein the at least one D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z}. Further, a preceding gate and a succeeding gate of the at least one D gate are extracted. Further, the succeeding gate is removed and the effect of the succeeding gate is included in the preceding gate by doubling the rotation angle of the preceding gate, if a set of conditions comprising a) the preceding gate and the succeeding gate are Rc gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z, is satisfied, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate, wherein by removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits causes depth reduction of the quantum circuit. By reducing the depth of the quantum circuit with this approach, the impact of noise on the quantum execution is potentially reduced, in turn improving quality of results generated.
Referring now to the drawings, and more particularly to FIG. 1 through FIG. 3B, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments and these embodiments are described in the context of the following exemplary system and/or method.
FIG. 1 illustrates an exemplary system for depth reduction of quantum circuit, according to some embodiments of the present disclosure. The system 100 includes or is otherwise in communication with hardware processors 102, at least one memory such as a memory 104, an I/O interface 112. The hardware processors 102, memory 104, and the Input /Output (I/O) interface 112 may be coupled by a system bus such as a system bus 108 or a similar mechanism. In an embodiment, the hardware processors 102 can be one or more hardware processors.
The I/O interface 112 may include a variety of software and hardware interfaces, for example, a web interface, a graphical user interface, and the like. The I/O interface 112 may include a variety of software and hardware interfaces, for example, interfaces for peripheral device(s), such as a keyboard, a mouse, an external memory, a printer and the like. Further, the I/O interface 112 may enable the system 100 to communicate with other devices, such as web servers, and external databases.
The I/O interface 112 can facilitate multiple communications within a wide variety of networks and protocol types, including wired networks, for example, local area network (LAN), cable, etc., and wireless networks, such as Wireless LAN (WLAN), cellular, or satellite. For the purpose, the I/O interface 112 may include one or more ports for connecting several computing systems with one another or to another server computer. The I/O interface 112 may include one or more ports for connecting several devices to one another or to another server.
The one or more hardware processors 102 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, node machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. Among other capabilities, the one or more hardware processors 102 is configured to fetch and execute computer-readable instructions stored in the memory 104.
The memory 104 may include any computer-readable medium known in the art including, for example, volatile memory, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), and/or non-volatile memory, such as read only memory (ROM), erasable programmable ROM, flash memories, hard disks, optical disks, and magnetic tapes. In an embodiment, the memory 104 includes a plurality of modules 106.
The plurality of modules 106 include programs or coded instructions that supplement applications or functions performed by the system 100 for executing different steps involved in the process of the depth reduction of quantum circuits. The plurality of modules 106, amongst other things, can include routines, programs, objects, components, and data structures, which performs particular tasks or implement particular abstract data types. The plurality of modules 106 may also be used as, signal processor(s), node machine(s), logic circuitries, and/or any other device or component that manipulates signals based on operational instructions. Further, the plurality of modules 106 can be used by hardware, by computer-readable instructions executed by the one or more hardware processors 102, or by a combination thereof. The plurality of modules 106 can include various sub-modules (not shown). The plurality of modules 106 may include computer-readable instructions that supplement applications or functions performed by the system 100 for the depth reduction of quantum circuits.
The data repository (or repository) 110 may include a plurality of abstracted piece of code for refinement and data that is processed, received, or generated as a result of the execution of the plurality of modules in the module(s) 106.
Although the data repository 110 is shown internal to the system 100, it will be noted that, in alternate embodiments, the data repository 110 can also be implemented external to the system 100, where the data repository 110 may be stored within a database (repository 110) communicatively coupled to the system 100. The data contained within such external database may be periodically updated. For example, new data may be added into the database (not shown in FIG. 1) and/or existing data may be modified and/or non-useful data may be deleted from the database. In one example, the data may be stored in an external system, such as a Lightweight Directory Access Protocol (LDAP) directory and a Relational Database Management System (RDBMS). Functions of the components of the system 100 are now explained with reference to the flow diagram in FIG. 2, and the example diagrams in FIGS. 3A and 3B.
FIGS. 2A and 2B (collectively referred to as FIG. 2), is a flow diagram depicting steps involved in the process of depth reduction of quantum circuit, using the system of FIG. 1, according to some embodiments of the present disclosure.
In an embodiment, the system 100 comprises one or more data storage devices or the memory 104 operatively coupled to the processor(s) 102 and is configured to store instructions for execution of steps of the method 200 by the processor(s) or one or more hardware processors 102. The steps of the method 200 of the present disclosure will now be explained with reference to the components or blocks of the system 100 as depicted in FIG. 1 and the steps of flow diagram as depicted in FIG. 2. Although process steps, method steps, techniques or the like may be described in a sequential order, such processes, methods, and techniques may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps to be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously.
In method 200 of the FIG. 2, at step 202, the system 100 receives, via the one or more hardware processors 102, a quantum circuit with n qubits as input. Further, at step 204 of the method 200, the system 100 extracts, via the one or more hardware processors 102, a plurality of circuit data associated with the quantum circuit. The plurality of circuit data may include data such as but not limited to one or more circuit patterns of pre-defined type. Following is a basic pre-defined circuit pattern that is compatible with the depth reduction approach in the method 200. For explanation purpose, it is considered that the circuit pattern being considered in the method 200 is compatible with a spin-echo effect, which enables optimization by adding effect of one gate on another, as being explained below, for the purpose of the depth reduction in the quantum circuit. R_(C )^¦( @ ) (?)DR_(C )^¦( @ ) (-?) where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z } and D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z}. The subsequent steps illustrate how the identified pattern is further checked in any input quantum circuit and how the quantum circuit is optimized, i.e., how the depth reduction is achieved. Upon detecting the pre-defined circuit pattern, the system 100 checks for presence of R_(C )^¦( @ )gates in subsequent preceding gate – succeeding gate pairs as illustrated in the following steps.
At step 206 of the method 200, the system 100 iteratively processes each of the n qubits, via the one or more hardware processors 102. Various steps involved in the iterative processing of each of the n qubits are depicted in steps 206a through 206e.
At step 206a, the system 100 selects a qubit from among the n qubits, in each iteration. The qubits maybe selected in the order in which they appear or in a random fashion. Further, at step 206b, the system 100 extracts a plurality of gates applied on the selected qubit. The extraction of the plurality of gates is dependent on a quantum Software Development Kit (SDK) that is being used by the system 100 at this stage. For example, if the system 100 uses Qiskit SDK, which is a known approach, then the circuit data is stored in a Directed Acyclic Graph (DAG) data structure and so the data extraction is based on this data structure. Further, at step 206c, the system 100 determines by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates. Each D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z}. Further, at step 206d, the system 100 extracts a preceding gate and a succeeding gate for the determined at least one D gate . In an embodiment, a gate preceding the determined at least one D gate is extracted as the preceding gate, and a gate succeeding the determined at least one D gate is extracted as the succeeding gate. Further, at step 206e, the system 100 initially determines whether a set of conditions, which are pre-defined, is satisfied. The set of conditions include: a) the preceding gate and the succeeding gate are R_c gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z. If the set of conditions is satisfied, the system 100 removes the succeeding gate and includes effect of the succeeding gate in the preceding gate by doubling the rotation angle of the preceding gate, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate. The iteration through remaining preceding gate – succeeding gate pairs in the plurality of preceding gate – succeeding gate pairs is terminated if the set of conditions is not satisfied for any of the preceding gate – succeeding gate pairs. Removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits, causes depth reduction of the quantum circuit.
For example, consider the example quantum circuit diagrams in FIGS. 3A and 3B. The quantum circuit in FIG. 3A has a depth 49. After applying the depth reduction approach as in method 200, the resultant quantum circuit as depicted in FIG. 3B has a depth of 41. In this example, the depth reduction is achieved by dropping controlled Y rotation gates in A operator and then including the effect in the immediately following A^† operator after the S_(?_0 )operator by doubling the rotation angles of the corresponding controlled Y rotation gates. The S_(?_0 )operator in this example is the Z gate which fills the criteria to be the representational D gate from the pre-defined circuit pattern. Once this D gate is identified, the preceding gate and the succeeding gate are identified to be the R_Y gates which fill the criteria to be the representational R_C gates from the pre-defined circuit pattern with equal and opposite rotation angles. Then subsequent preceding gate – succeeding gate pairs are iteratively searched through and a chain of R_Y gates are identified and optimized.

Experimental Data:
The experiment was conducted considering an option pricing scenario, in which the depth reduction approach was validated for single-asset European call and put options of ONGC asset for the entire month of February 2023 and for all the strike prices within two standard deviations around the mean of the past one year’s closing prices.
This technique on average resulted in reduction in depth of the circuits of 170 layers (MLAE m = 1) and 700 layers (MLAE m = 3) for both call and put options while not adversely impacting the quality of estimates obtained through the Maximum Likelihood Amplitude Estimation (MLAE) algorithm.
Option Type Shots MLAE m Queries Spin-Echo Circuit MAE
(Rs) Average Time
(sec)
Average Width Average Max Depth
Single-Asset
European Call 1,429 3 10,003 No 9 2102 1.25 3.16
Yes 1404 1.26 2.29
10,000 1 10,000 No 9 680 1.26 1.06
Yes 506 1.26 0.89
Single-Asset
European Put 1429 3 10,003 No 9 2149 1.03 3.26
Yes 1433 1.02 2.33
10,000 1 10,000 No 9 695 1.03 1.16
Yes 516 1.03 0.94

The following sequence is used for performing the depth reduction of quantum circuit in the option pricing context. the associated steps are explained in detail.

Step – 1: Construct a quantum circuit to estimate the payoff of single-asset vanilla European call/put option.
Step – 1.1: Fetch necessary financial data like the current price of an asset, risk-free rate of interest, etc., and construct an operator P for loading the log-normal distribution of spot prices of the asset at maturity.
Step – 1.2: Construct a payoff encoding operator for encoding the payoff of single-asset vanilla European call/put option. Construct the state preparation operator A using the PDF loading operator P, the comparator and the payoff encoding operator.
Step – 1.3: Construct the Grover operator Q=AS_0 A^† S_(?_0 ). Here, A^†is the inverse of the state preparation operator A. S_0 and S_(?_0 ) operators are for reflecting about the zero state and flipping the phase of the good state respectively.
Step – 1.4: Construct the complete option pricing circuit Q^k A|0?_n |0? that is compatible with the Maximum Likelihood Amplitude Estimation (MLAE) algorithm wherein the state preparation operator A is loaded first and the Grover operator Q is loaded after that for k number of times.
Step – 2: Pass the complete option pricing circuit Q^k A|0?_n |0? to method 200 which checks if the Spin-Echo compatible pre-defined circuit pattern is present in the circuit and then reduces the depth of the circuit accordingly.
Step – 2.1: Extract the circuit data associated with the quantum circuit. Iterate over each of the qubits and extract the quantum gates applied on each qubit.
Step – 2.2: Search for the presence of the D gate among the quantum gates applied on each qubit. In the option pricing circuit, the S_(?_0 )operator is a Z gate which fills the criteria to be the representational D gate from the pre-defined circuit pattern.
Step – 2.3: Once the D gate is identified, extract one gate present before and after the D gate as preceding and succeeding gates.
Step – 2.4: Check if the preceding and succeeding gates are of the same R_C type with angles equal and opposite to each other and that R_C^¦( @ ) is not R_X if D is X, R_C^¦( @ ) is not R_y if D is Y, and R_C^¦( @ ) is not R_z if D is Z.
Step – 2.5: If the conditions from step - 2.4 are satisfied, remove the succeeding gate and include the effect of succeeding gate in the preceding gate. In the option pricing circuit, the preceding gate and the succeeding gate are identified to be the controlled R_Y gates which fill the criteria to be the representational R_C gates from the pre-defined circuit pattern with equal and opposite rotation angles. The controlled R_Y gates in the circuit are present as part of the A and A^† operators.
Step – 2.6: Repeat steps 2.4 and 2.5 for the subsequent preceding gate – succeeding gate pairs to further reduce the depth of the circuit. In the option pricing circuit, depending on the payoff encoding operator, there could be more than one controlled R_Y gate. These are iteratively identified and optimized.
Step – 2.7: Iteratively keep searching for the pre-defined circuit pattern in the remaining part of the circuit and finally return the optimized circuit with reduced depth.
Step – 3: Estimate the expected payoff at maturity using Maximum Likelihood Amplitude Estimation (MLAE) algorithm and discount it back to obtain the current premium that a user has to pay to get into an option contract.
The written description describes the subject matter herein to enable any person skilled in the art to make and use the embodiments. The scope of the subject matter embodiments is defined by the claims and may include other modifications that occur to those skilled in the art. Such other modifications are intended to be within the scope of the claims if they have similar elements that do not differ from the literal language of the claims or if they include equivalent elements with insubstantial differences from the literal language of the claims.
The embodiments of present disclosure herein address unresolved problem of the impact of noise in quantum circuit executions. The embodiment, thus provides a mechanism for depth reduction of quantum circuits, and in turn the impact of noise potentially reduces.
It is to be understood that the scope of the protection is extended to such a program and in addition to a computer-readable means having a message therein; such computer-readable storage means contain program-code means for implementation of one or more steps of the method, when the program runs on a server or mobile device or any suitable programmable device. The hardware device can be any kind of device which can be programmed including e.g., any kind of computer like a server or a personal computer, or the like, or any combination thereof. The device may also include means which could be e.g., hardware means like e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination of hardware and software means, e.g., an ASIC and an FPGA, or at least one microprocessor and at least one memory with software processing components located therein. Thus, the means can include both hardware means and software means. The method embodiments described herein could be implemented in hardware and software. The device may also include software means. Alternatively, the embodiments may be implemented on different hardware devices, e.g., using a plurality of CPUs.
The embodiments herein can comprise hardware and software elements. The embodiments that are implemented in software include but are not limited to, firmware, resident software, microcode, etc. The functions performed by various components described herein may be implemented in other components or combinations of other components. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope of the disclosed embodiments. Also, the words “comprising,” “having,” “containing,” and “including,” and other similar forms are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise.
Furthermore, one or more computer-readable storage media may be utilized in implementing embodiments consistent with the present disclosure. A computer-readable storage medium refers to any type of physical memory on which information or data readable by a processor may be stored. Thus, a computer-readable storage medium may store instructions for execution by one or more processors, including instructions for causing the processor(s) to perform steps or stages consistent with the embodiments described herein. The term “computer-readable medium” should be understood to include tangible items and exclude carrier waves and transient signals, i.e., be non-transitory. Examples include random access memory (RAM), read-only memory (ROM), volatile memory, nonvolatile memory, hard drives, CD ROMs, DVDs, flash drives, disks, and any other known physical storage media.
It is intended that the disclosure and examples be considered as exemplary only, with a true scope of disclosed embodiments being indicated by the following claims.
, Claims:
A processor implemented method (200), comprising:
receiving (202), via one or more hardware processors, a quantum circuit with n qubits as input;
extracting (204), via the one or more hardware processors, a plurality of circuit data associated with the quantum circuit; and
iteratively processing (206) each of the n qubits, via the one or more hardware processors, comprising:
selecting (206a) a qubit from among the n qubits, in each iteration;
extracting (206b) a plurality of gates applied on the selected qubit;
determining (206c) by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates, wherein the at least one D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z};
extracting (206d) a preceding gate and a succeeding gate of the at least one D gate; and
removing (206e) the succeeding gate and including effect of the succeeding gate in the preceding gate by doubling the rotation angle of the preceding gate, if a set of conditions comprising a) the preceding gate and the succeeding gate are R_c gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z, is satisfied, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate,
wherein by removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits causes depth reduction of the quantum circuit.

The processor implemented method as claimed in claim 1, wherein the iteration through remaining preceding gate – succeeding gate pairs in the plurality of preceding gate – succeeding gate pairs is terminated if the set of conditions is not satisfied for any of the preceding gate – succeeding gate pairs.

The processor implemented method as claimed in claim 1, wherein the depth reduction of the quantum circuit received as input is caused if a pre-defined circuit pattern is present in the extracted plurality of circuit data of the quantum circuit.

A system (100), comprising:
one or more hardware processors (102);
a communication interface (112); and
a memory (104) storing a plurality of instructions, wherein the plurality of instructions cause the one or more hardware processors to:
receive a quantum circuit with n qubits as input;
extract a plurality of circuit data associated with the quantum circuit; and
iteratively process each of the n qubits, comprising:
selecting a qubit from among the n qubits, in each iteration;
extracting a plurality of gates applied on the selected qubit;
determining by iterating over the plurality of gates applied on the selected qubit, whether at least one D gate is present among the plurality of gates, wherein the at least one D gate is a single-qubit Pauli gate and belongs to a set of a plurality of single-qubit Pauli gates {X, Y, Z};
extracting a preceding gate and a succeeding gate of the at least one D gate; and
removing the succeeding gate and including effect of the succeeding gate in the preceding gate by doubling the rotation angle of the preceding gate, if a set of conditions comprising a) the preceding gate and the succeeding gate are R_c gates having angles equal and opposite to each other, where R_C^¦( @ ) belongs to a set of a plurality of single-qubit Pauli rotation gates {R_X,R_(y,) R_z }, and b) R_C^¦( @ ) is not equal to R_X if D is X, R_C^¦( @ ) is not equal to R_y if D is Y, and R_C^¦( @ ) is not equal to R_z if D is Z, is satisfied, for each of a plurality of preceding gate – succeeding gate pairs of each of the at least one D gate,
wherein by removing the succeeding gate and including effect of the succeeding gate in the preceding gate, for the n qubits causes depth reduction of the quantum circuit.

The system as claimed in claim 4, wherein the one or more hardware processors are configured to terminate the iteration through remaining preceding gate – succeeding gate pairs in the plurality of preceding gate – succeeding gate pairs, if the set of conditions is not satisfied for any of the preceding gate – succeeding gate pairs.

The system as claimed in claim 4, wherein the one or more hardware processors are configured to cause the depth reduction for the quantum circuit received as input, if a pre-defined circuit pattern is present in the extracted plurality of circuit data of the quantum circuit.