DESC:CONTROL STRATEGY FOR POWER FACTOR CORRECTION (PFC) CONVERTER
CROSS REFERENCE TO RELATED APPLICTIONS
The present application claims priority from Indian Provisional Patent Application No. 202421021044 filed on 19/03/2024, the entirety of which is incorporated herein by a reference.
TECHNICAL FIELD
The present disclosure generally relates to a power factor correction (PFC) converter. Particularly, the present disclosure relates to a control strategy for power factor correction (PFC) converter. Furthermore, the present disclosure relates to a method of controlling a power factor correction system. Furthermore, the present disclosure relates to a control system for an interleaved boost power factor correction converter.
BACKGROUND
In modern electric systems, the efficiency of the battery and power electronic components is crucial for achieving optimal performance and energy utilization. The use of high-efficiency power converters reduce energy losses during conversion processes, thereby enhancing the vehicle’s range and reducing overall energy consumption.
Generally, AC-DC converters are commonly used to convert alternating current (AC) into direct current (DC), which is essential for charging energy storage systems and powering various electronic systems. In applications requiring energy storage, the AC from external sources must be rectified into DC to charge high-capacity batteries and supply power to other subsystems or power electronic systems. The use of efficient AC-DC converters ensures minimal power loss, thereby improving vehicle energy efficiency, range, and overall performance. Also, there are multiple types of AC-DC converters, such as diode rectifiers, thyristor-based converters, switched-mode power supplies (SMPS), high-frequency converters and bridge rectifiers. However, the AC-DC converter exhibits a low power factor, leading to inefficient utilization of electrical power and increased reactive power. This may result in higher energy losses, excessive heat generation, and stress on grid infrastructure. To tackle this issue, the power factor correction (PFC) is incorporated with the AC-DC converters to improve the power factor of the electrical system i.e. unity power factor, ensuring efficient power usage and compliance with regulatory standards.
In addition to the PFC, there are several strategies that may be employed to achieve a unity power factor, ensuring optimal power usage and efficiency. One of the strategies is PI control which is widely used in power factor correction applications. The PI control dynamically adjusts the converter's operation to correct the phase difference between the voltage and current, reducing harmonics and ensuring the current waveform is in phase with the voltage waveform. This results in a unity power factor. However, the PI controllers may have a slower response to sudden changes in load or system dynamics, which may cause delays in correcting the power factor or maintaining stability during rapid transients. Furthermore, the performance of the PI control is heavily depending on the correct tuning of its proportional (P) and integral (I) gains. Improper tuning may lead to instability, oscillations, or poor dynamic performance. Also, the PI control may be sensitive to high-frequency noise, which causes fluctuations in the control signal and affect the overall stability and accuracy of the system.
Therefore, there is a need to use of more advance control technique to overcome one or more problems associated as set forth above.
SUMMARY
An object of the present disclosure is to provide a power factor correction system.
Another object of the present disclosure is to provide a method of controlling a power factor correction system.
Another object of the present disclosure is to provide a control system for an interleaved boost power factor correction converter
In accordance with first aspect of the present disclosure, there is provided a power factor correction system. The system comprises a boost converter circuit having at least one switching device, a voltage control loop configured to regulate a DC-link voltage, a current control loop configured to regulate an input power factor and a controller. The controller is configured to estimate a grid phase angle using a phase locked loop, generate a unit vector for a reference current based on the estimated phase angle, generate a reference current magnitude using a PI controller and a low-pass filter to maintain the DC-link voltage at a reference value, multiply the reference current magnitude by the unit vector to obtain a reference input current, predict a future value of the reference input current, calculate a cost function incorporating an inductor current ripple and select a switching state for the at least one switching device based on the calculated cost function.
The present disclosure discloses a power factor correction system. The power factor correction system as disclosed by present disclosure is advantageous in terms of providing an enhanced efficiency, stability, and performance in AC-DC power conversion applications. Beneficially, the power factor correction system provides the better dynamic response as compared to the other PI controllers. Beneficially, by reducing dependency on multiple PI controllers, the system simplifies control complexity and minimizes tuning efforts which makes the system more robust and easier to implement. Beneficially, as compared to other finite-control set model predictive control (FCS-MPC) strategies, the system achieves lower input current total harmonic distortion (THD) which enhances the power quality and compliance with grid standards. Furthermore, the inclusion of the power factor correction system beneficially allows for controlled and bounded operation, ensuring reliability under varying load conditions. Additionally, the system is computationally efficient, requiring fewer calculations while maintaining high performance. Beneficially, the design simplicity further facilitates practical implementation. Beneficially, the fixed switching frequency operation ensures consistent switching losses, making thermal management more predictable. Furthermore, the use of model predictive control (MPC) significantly enables the optimal operation by leveraging an optimization algorithm to determine the best switching states, enhancing overall efficiency and performance.
In accordance with second aspect of the present disclosure, there is provided a method of controlling a power factor correction system. The method comprises estimating a grid phase angle using a phase locked loop, generating a unit vector for a reference current based on the estimated phase angle, generating a reference current magnitude using a PI controller and a low-pass filter to maintain a DC-link voltage at a reference value, multiplying the reference current magnitude by the unit vector to obtain a reference input current, predicting a future value of the reference input current, calculating a cost function incorporating an inductor current ripple and selecting a switching state for at least one switching device based on the calculated cost function.
In accordance with third aspect of the present disclosure, there is provided a control system for an interleaved boost power factor correction converter, comprising a voltage control loop comprising a PI controller and a low-pass filter configured to generate a reference input current magnitude, a current control loop configured to implement finite-control set model predictive control. A controller configured to generate phase-shifted reference currents for parallel-connected boost converter cells, calculate individual cost functions for each boost converter cell incorporating inductor current ripple and select optimal switching states for each boost converter cell based on the calculated cost functions.
Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative embodiments constructed in conjunction with the appended claims that follow.
It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.
BRIEF DESCRIPTION OF DRAWINGS
The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.
Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:
FIG. 1 illustrates a block diagram of a power factor correction system, in accordance with an aspect of the present disclosure.
FIG. 2 illustrates a flow chart of a method of controlling a power factor correction system, in accordance with another aspect of the present disclosure.
FIG. 3 illustrates a block diagram of a control system for an interleaved boost power factor correction converter, in accordance with another aspect of the present disclosure.
FIG. 4 illustrates a circuit diagram of a power factor correction system, in accordance with another aspect of the present disclosure.
In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.
DETAILED DESCRIPTION
The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognise that other embodiments for carrying out or practising the present disclosure are also possible.
The description set forth below in connection with the appended drawings is intended as a description of certain embodiments of a power factor correction system and is not intended to represent the only forms that may be developed or utilised. The description sets forth the various structures and/or functions in connection with the illustrated embodiments; however, it is to be understood that the disclosed embodiments are merely exemplary of the disclosure that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimised to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.
The terms “comprise”, “comprises”, “comprising”, “include(s)”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, system that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or system. In other words, one or more elements in a system or apparatus preceded by “comprises... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or apparatus.
In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings and which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.
The present disclosure will be described herein below with reference to the accompanying drawings. In the following description, well known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.
As used herein, the term “power factor correction system”, “PFC system” and “system” are used interchangeably and refer to an electrical system designed to regulate and improve the power factor of an AC electrical network by minimizing reactive power consumption and reducing harmonic distortion. The system typically comprises a power conversion circuit, such as a boost converter, and a control mechanism configured to adjust the input current waveform to align with the voltage waveform, thereby achieving a power factor close to unity.
As used herein, the term “power factor correction” and “PFC” are used interchangeably and refer to a technique implemented in electrical power networks to improve the power factor by reducing reactive power consumption and minimizing harmonic distortion. Power factor is the ratio of real power to apparent power in an AC electrical system, and a low power factor indicates inefficient power usage. PFC systems adjust the phase angle between voltage and current waveforms or reduce harmonic distortion to bring the power factor closer to unity (1.0), thereby improving energy efficiency, reducing losses, and ensuring compliance with electrical grid regulations.
As used herein, the term “boost converter circuit” refers to a power electronic circuit configured to step up an input voltage to a higher output voltage using energy storage elements such as inductors and capacitors. The circuit typically comprises at least one switching device, such as a transistor, a diode, an inductor, and a capacitor. During operation, the switching device alternates between conducting and non-conducting states, controlling the energy transfer from the input source to the output load.
As used herein, the term “at least one switching device” and “switching device” are used interchangeably and refer to an electronic component capable of transitioning between conducting and non-conducting states to regulate power flow. This may include, but is not limited to, transistors such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Bipolar Junction Transistors (BJTs), or Silicon-Controlled Rectifiers (SCRs).
As used herein, the term “voltage control loop” refers to a feedback control mechanism configured to regulate and maintain a desired voltage level within an electrical or electronic system. The voltage control loop typically comprises a controller, that compares a measured voltage with a predefined reference voltage and generates a control signal to adjust the operation of a power conversion or regulation circuit accordingly. The voltage control loop ensures voltage stability by compensating for variations in load conditions, input voltage fluctuations, and other disturbances, thereby enhancing system reliability and performance.
As used herein, the term “DC link” refers to an electrical connection or circuit section within a power conversion system that establishes an intermediate direct current (DC) voltage between two stages of power conversion. The DC link typically consists of a capacitor, inductor, or both, and serves as an energy buffer between an input power source (such as an AC supply rectified through a converter) and an output stage (such as an inverter or DC-DC converter). The DC link is designed to maintain a stable DC voltage, minimize voltage fluctuations, and facilitate efficient energy transfer, thereby improving system performance and reliability.
As used herein, the term “DC link voltage” refers to the direct current (DC) voltage present across the energy storage element, such as a capacitor, in a power conversion system that interfaces different stages of power conversion. The DC link voltage serves as an intermediate voltage level between the rectification and inversion or regulation stages in applications such as power factor correction (PFC) circuits, DC-DC converters, and inverter-based systems.
As used herein, the term “current control loop” refers to a feedback control mechanism designed to regulate and maintain the current flow within a defined range or to track a reference current. The current control loop typically involves the measurement of the output or input current, which is compared against a reference current value or setpoint. The difference (error) between the measured current and the reference current is processed by a controller, such as the proportional-integral (PI) controller or model predictive controller (MPC), to generate control signals that adjust the operation of switching devices (e.g., transistors or MOSFETs) to minimize this error.
As used herein, the term “input power factor” refers to the ratio of real power (active power) to apparent power at the input of a power system, typically expressed as a dimensionless number between 0 and 1. The input power factor is a measure of how efficiently electrical power is being used, indicating the phase difference between the input voltage and input current waveforms. A power factor close to 1 implies that most of the power supplied is being effectively utilized, while a lower power factor indicates that a significant portion of the input power is reactive, leading to inefficient power usage.
As used herein, the term “controller” refers to an electronic or computational system that manages, regulates, or directs the operation of the device or system based on specific inputs and pre-defined control algorithms. The controller typically comprises hardware, software, or a combination of both, and is designed to perform specific control functions such as monitoring, adjusting, and optimizing the performance of the system in real-time. The controller may include components like processors, microcontrollers, digital signal processors (DSPs), or application-specific integrated circuits (ASICs), as well as associated software that implements control strategies such as feedback loops, predictive algorithms, or optimization methods. The controller receives inputs from sensors, processes the input according to a control algorithm, and generates output signals to control actuators, switches, or other system elements to achieve the desired system behaviour.
As used herein, the term “grid phase angle” refers to the angle that represents the phase difference between the voltage waveform of the power grid (typically the AC mains supply) and a reference waveform, such as a sinusoidal waveform in the system.
As used herein, the term “phase locked loop” and “PLL” are used interchangeably and refer to a control system used to synchronize an output signal's phase and frequency with a reference signal. The PLL consists of a feedback loop where a phase detector compares the phase difference between the input reference signal and the output signal. The phase detector produces an error signal proportional to the phase difference, which is then processed by a loop filter to smooth the error signal. The error signal is used to adjust the frequency of a voltage-controlled oscillator (VCO), which generates the output signal.
As used herein, the term “estimated phase angle” refers to the calculated or inferred angle that represents the phase difference between the grid voltage and the reference signal in an AC power system. The phase angle is typically estimated using a Phase-Locked Loop (PLL) or similar technique, which synchronizes the system's internal reference with the grid voltage.
As used herein, the term “reference current magnitude” refers to the desired amplitude of the input current that the system strives to maintain to achieve optimal power factor and regulated DC-link voltage. The reference current magnitude is a control parameter that is generated based on the system's voltage control loop, typically using a PI controller and a low-pass filter.
As used herein, the term “reference input current” refers to a calculated or desired current that serves as a target for regulating the input current to the system. The reference input current is derived from the grid phase angle and the required DC-link voltage, ensuring that the system operates efficiently and meets the power factor correction objectives.
As used herein, the term “cost function” refers to a mathematical representation or model used to quantify the performance, efficiency, or trade-offs within the system, often used in optimization problems or control strategies. The cost function typically incorporates various system parameters (such as current, voltage, power, or error terms) and is designed to measure a specific aspect of system behaviour, such as minimizing energy losses, reducing error, or optimizing operational performance.
As used herein, the term “inductor current ripple” refers to the periodic variation or fluctuation in the current flowing through an inductor in a power electronic circuit, typically observed in DC-DC converters or power factor correction systems. The inductor current ripple is caused by the switching actions of power devices within the converter, where the inductor current rises and falls due to the alternating connection and disconnection of energy storage elements.
As used herein, the term “switching state” refers to a specific configuration of the switching devices (such as transistors or MOSFETs) in a power electronic circuit, which determines the flow of current through the circuit at a given time. Each switching state represents the on/off status or the timing of the switches that control the operation of components like the boost converter, inverter, or other power conversion units. The switching state governs the power flow, voltage levels, and current characteristics within the circuit, and is typically used in control strategies to optimize efficiency, performance, and stability of the system.
As used herein, the term “interleaved boost converter” refers to a type of power converter that utilizes multiple boost converter cells connected in parallel, with each cell operating out of phase with the others. The cells share a common input and output, but the switching operations are phase-shifted relative to each other, typically by 180 degrees, to reduce input current ripple and improve overall efficiency.
As used herein, the term “boost converter cells” refers to individual, modular components within a boost converter circuit that are configured to operate in parallel or interleaved to achieve enhanced power conversion performance. Each cell typically consists of a switching device (e.g., transistor), an inductor, a diode, and a capacitor, which together function to step up the input voltage to a higher output voltage.
As used herein, the term “delay function” refers to a mathematical or algorithmic function used to introduce a time delay or phase shift between signals, typically to manage the timing of switching events in systems like interleaved converters or multi-phase power supplies.
As used herein, the term “predicted inductor current” refers to the estimated value of the current flowing through an inductor at a future time based on a mathematical model, control algorithm, or system dynamics. The prediction is derived from the real-time measurements, such as the input voltage, current, and system parameters, and is typically calculated using techniques like model predictive control (MPC) or other forecasting methods.
As used herein, the term “reference inductor current” refers to the ideal or target value of the inductor current that the system aims to achieve or maintain during operation. The reference current is typically generated based on the desired performance criteria, such as regulating the output voltage or maintaining a specific power factor.
As used herein, the term “PI controller” refers to a type of feedback control system that combines two control actions including proportional and integral into a single control mechanism to regulate a desired output. The proportional term (P) is responsible for correcting the error by producing an output proportional to the current error between the setpoint and the measured process variable. The integral term (I) addresses the accumulation of past errors over time, helping to eliminate any steady-state error by adjusting the output to reduce the cumulative deviation.
As used herein, the term “low-pass filter” refers to an electrical circuit or system that allows signals with a frequency lower than a specified cutoff frequency to pass through while attenuating (reducing the amplitude of) signals with frequencies higher than the cutoff. The low-pass filter works by rejecting high-frequency noise or unwanted components and maintaining the integrity of the desired low-frequency signal.
As used herein, the term “finite-control set model predictive control” and “FCS-MPC” are used interchangeably and refer to an advanced control strategy used to optimize the performance of dynamic systems, such as power converters, by selecting control inputs from a finite set of predefined values. The FCS-MPC operates by evaluating a set of possible control inputs (switching states) over a finite horizon and selecting the one that minimizes a cost function, typically related to the system performance metrics such as error, power quality, or system efficiency.
Figure 1, in accordance with an embodiment describes a power factor correction system 100. The system 100 comprises a boost converter circuit 102 having at least one switching device 104, a voltage control loop 106 configured to regulate a DC-link voltage, a current control loop 108 configured to regulate an input power factor and a controller 110. The controller 110 configured to estimate a grid phase angle using a phase locked loop 112, generate a unit vector for a reference current based on the estimated phase angle, generate a reference current magnitude using a PI controller 114 and a low-pass filter 116 to maintain the DC-link voltage at a reference value, multiply the reference current magnitude by the unit vector to obtain a reference input current, predict a future value of the reference input current, calculate a cost function incorporating an inductor current ripple and select a switching state for the at least one switching device 104 based on the calculated cost function.
The present disclosure discloses the power factor correction system 100. The power factor correction system 100 as disclosed by present disclosure is advantageous in terms of the ability of the system 100 to achieve a faster dynamic response compared to conventional PI controllers, ensuring rapid adaptation to grid fluctuations and load variations. Beneficially, the system 100 reduces reliance on multiple PI controllers, thereby enhancing overall stability and minimizing the complexities associated with PI tuning. Furthermore, the system 100 effectively reduces input current total harmonic distortion (THD) as compared to conventional techniques which leads to improved power quality and compliance with precise grid regulations. Moreover, the system 100 with the control algorithm considers certain predefined system constraints such as voltage, current limits, switching states, and power quality requirements while making the control decisions. Beneficially, by integrating the control algorithm into the model predictive control (MPC) strategy significantly ensures that the system 100 does not exceeds the safe operating limits, thereby preventing excessive current, voltage spikes, or unstable operation. Beneficially, the system 100 improves the reliability and safety by ensuring that all control actions remain within acceptable boundaries, avoiding potential failures, component stress, or violations of grid regulations. Furthermore, the inclusion of an interleaved boost converter topology optimizes the performance by distributing the input current among the at least two parallel-connected boost converter cells 102a, 102b, thereby reduces the ripple, mitigating the electromagnetic interference, and enhances the thermal management. Furthermore, the controller 110 have an ability to generate phase-shifted reference currents and maintain a 180-degree phase shift between switching states which beneficially ensures the balanced power distribution and reduced stress on individual components. Furthermore, the system 100 operates at a fixed switching frequency, which results in constant switching losses. Additionally, the system 100 incorporates the fault-tolerant operation by evaluating individual cost functions for each boost converter cell, thereby improving reliability in the event of component failures. Overall, the system 100 provides a robust, efficient, and high-performance power factor correction solution suitable for modern power electronic applications requiring superior power quality, stability, and energy efficiency.
In an embodiment, the boost converter circuit 102 comprises an interleaved boost converter having at least two parallel-connected boost converter cells 102a, 102b. The interleaved configuration allows the at least two parallel-connected converter cells 102a, 102b to operate in a phase-shifted manner which effectively distributing the input current between multiple inductors. Beneficially, the improved design with the at least two parallel-connected converter cells 102a, 102b reduces the overall input current ripple, enhances efficiency, and minimizes electromagnetic interference. Additionally, the interleaved structure improves thermal management by spreading power dissipation across multiple switching devices, thereby enhancing the reliability and performance of the system 100.
In an embodiment, the controller 110 is configured to generate a phase-shifted reference current for each boost converter cell using a delay function and calculate individual cost functions for each of the boost converter cell. The controller 110 generates a phase-shifted reference current for each boost converter cell to ensure optimal current sharing and minimize ripple. The optimal current sharing and minimize ripple may be achieved by applying a delay function, which introduces a controlled phase shift between the reference currents of the individual converter cells, thereby improving power distribution and reducing electromagnetic interference. Additionally, the controller 110 calculates individual cost functions for each boost converter cell which allows precise switching state selection based on predicted inductor currents and inductor current ripple. By optimizing the cost function separately for each cell, the system 100 enhances overall efficiency, reduces current distortion, and ensures balanced operation between the interleaved boost converter cells 102a, 102b.
In an embodiment, the controller 110 is configured to maintain a 180-degree phase shift between the switching states of the parallel-connected boost converter cells. Beneficially, by ensuring a 180-degree phase shift between the switching signals of the at least two parallel-connected boost converter cells 102a, 102b, the system 100 achieves better input current ripple cancellation, thereby minimizing the electromagnetic interference and improving power quality. Furthermore, the 180-degree phase shift operation also leads to improved thermal performance by distributing the power loss across the at least one switching device 104, thereby reducing the stress on individual components and enhances the reliability of the system 100.
In an embodiment, the cost function is calculated based on a difference between a predicted inductor current and a reference inductor current and the inductor current ripple. The controller 110 predicts the future value of the inductor current using the system 100 and compares the future value with the predefined reference inductor current to determine the deviation. The difference represents the tracking error, which is a critical factor in evaluating the accuracy of current control. Additionally, the inductor current ripple within the switching cycle may be considered in the cost function to minimize oscillations and improve power quality. Beneficially, by incorporating both the predicted inductor current deviation and the current ripple into the cost function, the system 100 achieves enhanced dynamic response, thereby reduces the harmonic distortion, and improves the overall stability.
In an embodiment, the power factor correction system 100. The system 100 comprises the boost converter circuit 102 having the at least one switching device 104, the voltage control loop 106 configured to regulate the DC-link voltage, the current control loop 108 configured to regulate an input power factor and the controller 110. The controller 110 configured to estimate the grid phase angle using the phase locked loop 112, generate the unit vector for the reference current based on the estimated phase angle, generate the reference current magnitude using the PI controller 114 and the low-pass filter 116 to maintain the DC-link voltage at the reference value, multiply the reference current magnitude by the unit vector to obtain the reference input current, predict the future value of the reference input current, calculate the cost function incorporating the inductor current ripple and select the switching state for the at least one switching device 104 based on the calculated cost function. Furthermore, the boost converter circuit 102 comprises the interleaved boost converter having the at least two parallel-connected boost converter cells 102a, 102b. Furthermore, the controller 110 is configured to generate the phase-shifted reference current for each boost converter cell using the delay function and calculate individual cost functions for each of the boost converter cell. Furthermore, the controller 110 is configured to maintain the 180-degree phase shift between the switching states of the parallel-connected boost converter cells. Furthermore, the cost function is calculated based on the difference between a predicted inductor current and the reference inductor current and the inductor current ripple.
Figure 2, describes a method 200 of controlling a power factor correction system 100. The method 200 starts at step 202 and completes at step 214. At step 202, the method 200 comprises estimating a grid phase angle using a phase locked loop 112. At step 204, the method 200 comprises generating a unit vector for a reference current based on the estimated phase angle. At step 206, the method 200 comprises generating a reference current magnitude using a PI controller 114 and a low-pass filter 116 to maintain a DC-link voltage at a reference value. At step 208, the method 200 comprises multiplying the reference current magnitude by the unit vector to obtain a reference input current. At step 210, the method 200 comprises predicting a future value of the reference input current. At step 212, the method 200 comprises calculating a cost function incorporating an inductor current ripple. At step 214, the method 200 comprises selecting a switching state for at least one switching device 104 based on the calculated cost function.
In an embodiment, the power factor correction system 100 comprises an interleaved boost converter having at least two parallel-connected boost converter cells 102a, 102b, and the method 200 comprises generating phase-shifted reference currents for the parallel-connected boost converter cells using a delay function and calculating individual cost functions for each of the boost converter cell.
In an embodiment, the method 200 comprises maintaining a 180-degree phase shift between switching states of the parallel-connected boost converter cells.
In an embodiment, calculating the cost function comprises determining a difference between a predicted inductor current and a reference inductor current, calculating the inductor current ripple and combining the difference and the inductor current ripple to generate the cost function.
In an embodiment, the method 200 comprises selecting from a predefined set of allowable switching states comprising a first state where a first switch is on and a second switch is off, a second state where the first switch is off and the second switch is on, a third state where both switches are on and a fourth state where both switches are off.
It would be appreciated that all the explanations and embodiments of the portable device 100 also applies mutatis-mutandis to the method 200.
In an embodiment, the method 200 of controlling the power factor correction system 100. The method 200 starts at step 202 and completes at step 214. At step 202, the method 200 comprises estimating the grid phase angle using the phase locked loop 112. At step 204, the method 200 comprises generating the unit vector for the reference current based on the estimated phase angle. At step 206, the method 200 comprises generating the reference current magnitude using the PI controller 114 and the low-pass filter 116 to maintain the DC-link voltage at the reference value. At step 208, the method 200 comprises multiplying the reference current magnitude by the unit vector to obtain the reference input current. At step 210, the method 200 comprises predicting the future value of the reference input current. At step 212, the method 200 comprises calculating the cost function incorporating an inductor current ripple. At step 214, the method 200 comprises selecting the switching state for at least one switching device 104 based on the calculated cost function. Furthermore, the power factor correction system 100 comprises the interleaved boost converter having the at least two parallel-connected boost converter cells 102a, 102b, and the method 200 comprises generating phase-shifted reference currents for the parallel-connected boost converter cells using the delay function and calculating individual cost functions for each of the boost converter cell. Furthermore, the method 200 comprises maintaining the 180-degree phase shift between switching states of the parallel-connected boost converter cells. Furthermore, calculating the cost function comprises determining the difference between the predicted inductor current and the reference inductor current, calculating the inductor current ripple and combining the difference and the inductor current ripple to generate the cost function. Furthermore, the method 200 comprises selecting from the predefined set of allowable switching states comprising the first state where the first switch is on and the second switch is off, the second state where the first switch is off and the second switch is on, the third state where both switches are on and the fourth state where both switches are off.
Figure 3, describes a control system 300 for an interleaved boost power factor correction converter 318, comprising a voltage control loop 306 comprising a PI controller 314 and a low-pass filter 316 configured to generate a reference input current magnitude, a current control loop 308 configured to implement finite-control set model predictive control and a controller 310. The controller 310 configured to generate phase-shifted reference currents for parallel-connected boost converter cells, calculate individual cost functions for each boost converter cell incorporating inductor current ripple and select optimal switching states for each boost converter cell based on the calculated cost functions.
In an embodiment, the controller 310 is configured to maintain fixed switching frequency operation and implement fault-tolerant operation through individual cost function calculation for each boost converter cell.
In an embodiment, the control system 300 for the interleaved boost power factor correction converter 318, comprising the voltage control loop 306 comprising the PI controller 314 and the low-pass filter 316 configured to generate the reference input current magnitude, the current control loop 308 configured to implement finite-control set model predictive control and the controller 310. The controller 310 configured to generate phase-shifted reference currents for parallel-connected boost converter cells, calculate individual cost functions for each boost converter cell incorporating inductor current ripple and select optimal switching states for each boost converter cell based on the calculated cost functions. Furthermore, the controller 310 is configured to maintain fixed switching frequency operation and implement fault-tolerant operation through individual cost function calculation for each boost converter cell.
Figure 4, describes a circuit arrangement for a power factor correction system 100. The system 100 comprises an AC power supply connected to an interleaved boost converter comprising at least two parallel-connected boost converter cells 102a, 102b. The first boost converter cell 102a consists of two diodes (Db1, Db3), an inductor carrying current (iL1), a diode (D1), and a switching device (SW1). Similarly, the second boost converter cell 102b includes two diodes (Db2, Db4), an inductor carrying current (iL2), a diode (D1), and a switching device (SW2). The output of the system 100 is connected to a DC-link capacitor to maintain a stable DC voltage. A control system 300 is implemented, wherein the switches (SW1, SW2) are controlled based on a cost function calculation to optimize switching states, ensuring improved power factor correction, reduced harmonic distortion, and enhanced system efficiency.
In the description of the present invention, it is also to be noted that, unless otherwise explicitly specified or limited, the terms “disposed,” “mounted,” and “connected” are to be construed broadly, and may for example be fixedly connected, detachably connected, or integrally connected, either mechanically or electrically. They may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Modifications to embodiments and combination of different embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as “including”, “comprising”, “incorporating”, “have”, “is” used to describe and claim the present disclosure are intended to be construed in a non- exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural where appropriate.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the present disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
,CLAIMS:We Claim:
1. A power factor correction system (100), wherein the system (100) comprises:
- a boost converter circuit (102) having at least one switching device (104);
- a voltage control loop (106) configured to regulate a DC-link voltage;
- a current control loop (108) configured to regulate an input power factor; and
- a controller (110) configured to:
- estimate a grid phase angle using a phase locked loop (112);
- generate a unit vector for a reference current based on the estimated phase angle;
- generate a reference current magnitude using a PI controller (114) and a low-pass filter (116) to maintain the DC-link voltage at a reference value;
- multiply the reference current magnitude by the unit vector to obtain a reference input current;
- predict a future value of the reference input current;
- calculate a cost function incorporating an inductor current ripple; and
- select a switching state for the at least one switching device (104) based on the calculated cost function.
2. The system (100) as claimed in claim 1, wherein the boost converter circuit (102) comprises an interleaved boost converter having at least two parallel-connected boost converter cells (102a, 102b).
3. The system (100) as claimed in claim 2, wherein the controller (110) is configured to:
- generate a phase-shifted reference current for each boost converter cell using a delay function; and
- calculate individual cost functions for each of the boost converter cell.
4. The system (100) as claimed in claim 2, wherein the controller (110) is configured to maintain a 180-degree phase shift between the switching states of the parallel-connected boost converter cells.
5. The system (100) as claimed in claim 1, wherein the cost function is calculated based on:
- a difference between a predicted inductor current and a reference inductor current; and
- the inductor current ripple.
6. A method (200) of controlling a power factor correction system (100), wherein the method (200) comprises:
- estimating a grid phase angle using a phase locked loop (112);
- generating a unit vector for a reference current based on the estimated phase angle;
- generating a reference current magnitude using a PI controller (114) and a low-pass filter (116) to maintain a DC-link voltage at a reference value;
- multiplying the reference current magnitude by the unit vector to obtain a reference input current;
- predicting a future value of the reference input current;
- calculating a cost function incorporating an inductor current ripple; and
- selecting a switching state for at least one switching device (104) based on the calculated cost function.
7. The method (200) as claimed in claim 6, wherein the power factor correction system (100) comprises an interleaved boost converter having at least two parallel-connected boost converter cells (102a, 102b), and the method (200) comprises:
- generating phase-shifted reference currents for the parallel-connected boost converter cells using a delay function; and
- calculating individual cost functions for each of the boost converter cell.
8. The method (200) as claimed in claim 7, wherein the method (200) comprises maintaining a 180-degree phase shift between switching states of the parallel-connected boost converter cells.
9. The method (200) as claimed in claim 6, wherein calculating the cost function comprises:
- determining a difference between a predicted inductor current and a reference inductor current;
- calculating the inductor current ripple; and
- combining the difference and the inductor current ripple to generate the cost function.
10. The method (200) as claimed in claim 6, wherein the method (200) comprises selecting from a predefined set of allowable switching states comprising:
- a first state where a first switch is on and a second switch is off;
- a second state where the first switch is off and the second switch is on;
- a third state where both switches are on; and
- a fourth state where both switches are off.
11. A control system (300) for an interleaved boost power factor correction converter (318), comprising:
- a voltage control loop (306) comprising a PI controller (314) and a low-pass filter (316) configured to generate a reference input current magnitude;
- a current control loop (308) configured to implement finite-control set model predictive control; and
- a controller (310) configured to:
- generate phase-shifted reference currents for parallel-connected boost converter cells;
- calculate individual cost functions for each boost converter cell incorporating inductor current ripple; and
- select optimal switching states for each boost converter cell based on the calculated cost functions.
12. The control system (300) as claimed in claim 11, wherein the controller (310) is configured to:
- maintain fixed switching frequency operation; and
- implement fault-tolerant operation through individual cost function calculation for each boost converter cell.