Description:The following specification particularly describes the invention and the manner in which it is to be performed

A METHOD FOR ONLINE DC INSULATION RESISTANCE MEASUREMENT, AND INSULATION FAULT LOCATION FOR UNGROUNDED POWER SUPPLY SYSTEM.
FIELD OF DISCLOSURE
The present disclosure generally relates to insultation resistance measurement and specifically relates to online direct current (DC) insulation resistance measurement, and insulation fault location for ungrounded power supply system.
BACKGROUND OF THE DISCLOSURE
Embodiments of the present invention generally relate to a system and method for online direct current (DC) insulation resistance measurement, and insulation fault location for ungrounded power supply system.
In an ungrounded direct current isolated terra (DC IT) power supply system, the active bus conductors (+ and -) are isolated from the earth or chassis ground. Consequently, a single insulation fault—an insulation fault occurring between any one of the two active conductors and the earth—results in a small leakage current between the active conductor and the ground. Further, a second insulation fault triggers the circuit breaker, causing the load to disconnect. Therefore, continuous insulation monitoring is essential to detect insulation faults promptly.
In the field of insulation resistance measurement for DC systems, there are two primary approaches: passive and active. In the passive measurement method, the insulation resistance is measured using the DC supply input of the system. One common technique in this category is the balanced bridge method that utilizes a balanced bridge circuit that only requires precise resistors and a differential amplifier. This method also provides a fast response time and is not affected by system leakage capacitance (Ce). However, this method cannot detect faults or measure insulation resistance in the absence of DC supply. It also fails to monitor symmetrical insulation faults. Furthermore, the method cannot measure or locate the insulation resistance of each conductor individually, and the accuracy is impacted by resistance tolerance and temperature drift.
Another technique under the passive method is the direct measurement with resistive divider method that provides a fast response time. However, it cannot detect faults or measure insulation resistance without the DC supply. It also requires precise resistor values to avoid errors in leakage current calculations, and the system DC voltage needs to be monitored. Input DC voltage harmonics, noise, and large system leakage capacitance can impact measurement accuracy and time in this method.
In contrast the passive methods, the active measurement method is independent of DC supply input provided to the system. Instead, it generates a test using an auxiliary power supply for measurement. One commonly used method under this category is the DC Pulsating Method that can even detect insulation faults in the absence of DC supply input. However, this method requires careful calibration and measurement of the excitation signal. Additional protective measures are needed for the excitation signal, and the method's accuracy can be affected by low-frequency components in the DC supply, fluctuating loads, and inductive or capacitive loads. The method is also susceptible to measurement errors due to leakage capacitive and resistive currents.
An insulation monitoring relay (IMR) or insulation monitoring device (IMD) used in an unearthed DC IT system ensures the operational and electrical safety of the supply system and the connected load equipment by detecting insulation faults early. By continuously monitoring insulation resistance, an online DC insulation monitoring device can detect and prevent insulation breakdowns before they result in costly damage or dangerous electrical failures. If the insulation resistance between the two conductors D+ and D- falls below a set pre-warning value, the device alerts the operator through visual and sound signals. Thereby, it helps ensure human safety against indirect contact or fire by adhering to the rules set by the OEM.
Various traditional methods for measuring insulation resistance exist, but such methods encounter various challenges and difficulties. Further, it is also crucial to improve the accuracy of the measured insulation resistance values. The majority traditional method requires DC supply input to be active for the measurement. In absence of DC supply input, the insulation resistance can’t be measured. Additionally, the traditional methods are incapable of measuring the insulation resistance in symmetrical fault / no fault conditions.
Furthermore, the impact of the leakage capacitance on the insulation resistance measurement is also difficult to identify or measure using the traditional methods. Although, the existing methods may measure the overall insulation resistance but cannot measure or locate insulation resistance fault of each conductor with respect to PE. In addition to this, the traditional methods may have poor accuracy at lower values of the insulation resistance.
Therefore, there is a need of to develop new method - online direct current (DC) insulation measurement resistance, and insulation fault location for ungrounded power supply system. This method detects the fault or measure insulation resistance in absence of DC voltage. Moreover, this method is capable of improve the accuracy of the measured insulation resistance values and that too in symmetrical fault / no fault conditions
SUMMARY
The following is a summary description of illustrative embodiments of the invention. It is provided as a preface to assist those skilled in the art to more rapidly assimilate the detailed design discussion which ensues and is not intended in any way to limit the scope of the claims which are appended hereto in order to particularly point out the invention.
Embodiments in accordance with the present invention provide a method for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system. Embodiments of the present invention may provide a number of advantages depending on its particular configuration.
The present disclosure aims to solves the major limitations of traditional measurement methods.
An objective of the present disclosure is to develop an online direct current (DC) insulation resistance measurement, and insulation fault location for ungrounded power supply system method that allows for accurate insulation resistance measurement even when the DC IT system is not active.
Another objective of the present disclosure is to ensure the health of DC supply lines i.e. D+, D-. Another objective of the present disclosure is to ensure compliance with IEC/EN 61557-8 requirements to guarantee reliability and standardization.
Another objective of the present disclosure is to develop a method to improve the accuracy of the measured insulation resistance values.
Another objective of the present disclosure is to develop a method that can facilitate easy implementation and use without requiring extensive training or specialized knowledge.
Another objective of the present disclosure is to provide a reliable and safe means of measuring insulation resistance in DC IT systems.
Another objective of the present disclosure is to reduce the risk of undetected insulation faults.
Yet another objective of the present disclosure is to develop a method that can be easily integrated with the measurement process without requiring significant system modifications.
In light of above disclosure, in an aspect of the present invention a method for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system is disclosed herein. The method includes connecting an insulation monitoring device (IMD) between a positive terminal (D+) and a negative terminal (D-) of a direct current (DC) source voltage (VDC), applied excitation voltage (Vs) and a protective earth. The method also includes measuring alternately insulation resistance through positive and negative arms of the insulation monitoring device upon power-up. The insulation resistance is measured alternatively through positive and negative arms at zero-volt DC (VDC) by applying DC excitation voltage (Vs) pulses. The method also includes allowing detection of symmetrical and asymmetrical insulation conditions. The method also includes detecting insulation fault occurring due to an insulation breakdown and/or at least one broken wire in supply lines. The method also includes stopping immediately the measuring circuit via an online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system. The method also includes generating a first alarm as a warning and a second alarm as a fault. The method also includes keeping the insulation measurement relay (IMR) in the fault condition unless and until the fault is resolved by recovery of the insulation break down and/or detection and recovery of the broken wire. The method also includes utilizing a two-point calibration to enhance measurement accuracy.
In one embodiment, the calculation of insulation resistance with both the direct current (DC) source voltage (VDC) and an applied excitation voltage (Vs) being in active state is performed, having a first switch (SW1) and a third switch (SW3) closed and a second switch (SW2) and a fourth switch (SW4) open.
In one embodiment, the calculation of insulation resistance with both the direct current (DC) source voltage (VDC) and the applied excitation voltage (Vs) being in active state is performed, having the first switch (SW1) and the fourth switch (SW4) open and the second switch (SW2) and the third switch (SW3) closed.
In one embodiment, the calculation of insulation resistance with the direct current (DC) source voltage (VDC) at zero and the applied excitation voltage (Vs) in active state is performed, having the first switch (SW1) and the third switch (SW3) closed and the second switch (SW2) and the fourth switch (SW4) open.
In one embodiment, the calculation of insulation resistance with the direct current (DC) source voltage (VDC) at zero and the applied excitation voltage (Vs) in active state is performed, having the second switch (SW2) and the third switch closed and the first switch (SW1) and the fourth switch (SW4) open.
In one embodiment, the detection of the broken wires in a direct current (DC) supply further comprises monitoring the voltage across the positive terminal (D+) and the negative terminal (D-) of the live voltage supply. The process further comprises determining if the voltage across the positive terminal (D+) and the negative terminal (D-) is less than a prespecified value. The process further comprises applying an excitation voltage (Vs) through the fourth switch (SW4) and the first switch (SW1) closed and the second switch (SW2) and the third switch (SW3) open to the measurement ground (GND iso). The process further comprises measuring the voltage between the positive terminal (D+) and the measurement ground (GND iso). The process further comprises concluding a broken wire condition if the measured voltage between terminal D positive terminal (D+) and the measurement ground (GND iso) is near 0V. The process further comprises concluding no broken wire if the measured voltage is greater than 90% of the applied excitation voltage (Vs).
In one embodiment, the two-point calibration enables good accuracy towards lower resistance values.
In one embodiment, wherein the voltage calibration for the positive terminal (D+) arm with the direct current (DC) source voltage (VDC) set to higher voltage further includes keeping the first simulated resistance (RisoP) at high and keeping the second simulated resistance (RisoN) opened. The method further includes keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method further includes switching ON the voltage supply and measuring a first actual ADC value (Actual value1) by closing the first switch (SW1) and the third switch (SW3), the second switch (SW2) and the fourth switch (SW4) remain open to obtain a first calculation value (Cal point 1). The method further includes keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened. The method further includes keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method further includes measuring a second actual ADC value (Actual value2) by closing the first switch (SW1) and the third switch (SW3), the second switch (SW2) and the fourth switch (SW4) remain open to obtain a second calculation value (Cal point 2). The method further includes calculating a positive ARM voltage value (VP) based on ADC reading.
In one embodiment, the voltage calibration for the negative terminal (D-) arm with the direct current (DC) source voltage (VDC) set to higher voltage further includes keeping the first simulated resistance (RisoP) at low and keeping the second simulated resistance (RisoN) opened. The method further includes keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method further includes switching ON the voltage supply and measuring the first actual ADC value (Actual value1) by closing the second switch (SW2) and the third switch (SW3), the first switch (SW1) and the fourth switch (SW4) open to obtain the first calculation value (Cal point 1). The method further includes keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened. The method further includes keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method further includes measuring the second actual ADC value (Actual value2) by closing the second switch (SW2) and the third switch (SW3), the first switch (SW1) and the fourth switch (SW4) open to obtain the second calculation value (Cal point 2). The method further includes calculating a negative ARM voltage value (VN) based on ADC reading.
In one embodiment, the voltage calibration for the positive terminal (D+) arm and the negative terminal (D-) arm with the direct current (DC) source voltage (VDC) set to zero or lower voltage further includes keeping the first simulated resistance (RisoP) at low and keeping the second simulated resistance (RisoN) opened. The method further includes keeping the direct current (DC) source voltage (VDC) at zero volt. The method further includes switching ON the voltage supply and measuring the first actual ADC value (Actual value1) by closing the first switch (SW1) to measure the positive ARM voltage value (VP) to obtain the first calculation value (Cal point 1) and measuring the negative ARM voltage value (VN) by closing the second switch (SW2) to obtain the first calculation value (Cal point 1). The method further includes keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened. The method further includes keeping the direct current (DC) source voltage (VDC) at zero. The method further includes measuring the second actual ADC value (Actual value2) by closing second switch (SW2) to obtain the second calculation value (Cal point 2). The method further includes calculating the negative ARM voltage value (VN) based on ADC reading. The method further includes measuring the actual ADC value (i.e. Actual value2) for the positive ARM voltage value (VP) by closing first switch (SW1) and for the negative ARM voltage value (VN) by closing second switch (SW2) and calculating the second calculation value (Cal point 2).
These and other advantages will be apparent from the present application of the embodiments and solves above mentioned limitations in the traditional system.
The preceding is a simplified summary to provide an understanding of some embodiments of the present invention. This summary is neither an extensive nor exhaustive overview of the present invention and its various embodiments. The summary presents selected concepts of the embodiments of the present invention in a simplified form as an introduction to the more detailed description presented below. As will be appreciated, other embodiments of the present invention are possible utilizing, alone or in combination, one or more of the features set forth above or described in detail below.
These elements, together with the other aspects of the present disclosure and various features are pointed out with particularity in the claims annexed hereto and form a part of the present disclosure. For a better understanding of the present disclosure, its operating advantages, and the specified object attained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated exemplary embodiments of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and still further features and advantages of embodiments of the present invention will become apparent upon consideration of the following detailed description of embodiments thereof, especially when taken in conjunction with the accompanying drawings, and wherein:
FIG. 1A illustrates a block diagram of a method 100 for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system, according to an embodiment of the present invention;
FIG. 1B illustrates a simulation circuit for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system, according to an embodiment of the present invention;
FIG. 1C illustrates a simulation circuit for current flow (Im1), when the first switch (SW1) and the third switch (SW3) is closed, the second switch (SW2) and the fourth switch (SW4) is open and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention;
FIG. 1D illustrates a simulation circuit for current flow (Im2), when the first switch (SW1) and the third switch (SW3) is closed, the second switch (SW2) and the fourth switch (SW4) is open is closed and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention;
FIG. 1E illustrates a simulation circuit for current flow (Im3), when the first switch (SW1) and the third switch (SW3) is closed, the second switch (SW2) and the fourth switch (SW4) is open and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention;
FIG. 1F illustrates a simulation circuit for current flow (Im4), when the second switch (SW2) and the third switch (SW3) is closed, the first switch (SW1) and the fourth switch (SW4) is open the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention;
FIG. 1G illustrates a simulation circuit for current flow (Im1), when the direct current (DC) supply input is active with the direct current (DC) source voltage (VDC) at zero volts and excitation signal (Vs) is active, according to an embodiment of the present invention;
FIG. 1H illustrates a simulation circuit for current flow (Im2), when the direct current (DC) supply input is active with the direct current (DC) source voltage (VDC) at zero volts and excitation signal (Vs) is active, according to an embodiment of the present invention;
FIG. 1I illustrates a simulation circuit for broken wire detection, when the first switch (SW1) and the fourth switch (SW4) is closed, the third switch (SW3) and the second switch (SW2) is open and the direct current (DC) source voltage (VDC) is zero volts, according to an embodiment of the present invention; and
FIG. 1J illustrates a simulation circuit for calibration of D+ and D- Arm with the third switch (SW3) closed and the fourth switch (SW4) open, according to an embodiment of the present invention.
The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including but not limited to. To facilitate understanding, like reference numerals have been used, where possible, to designate like elements common to the figures. Optional portions of the figures may be illustrated using dashed or dotted lines, unless the context of usage indicates otherwise.
DETAILED DESCRIPTION
The following description includes the preferred best mode of one embodiment of the present invention. It will be clear from this description of the invention that the invention is not limited to these illustrated embodiments but that the invention also includes a variety of modifications and embodiments thereto. Therefore, the present description should be seen as illustrative and not limiting. While the invention is susceptible to various modifications and alternative constructions, it should be understood, that there is no intention to limit the invention to the specific form disclosed, but, on the contrary, the invention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the invention as defined in the claims.
In any embodiment described herein, the open-ended terms "comprising," "comprises,” and the like (which are synonymous with "including," "having” and "characterized by") may be replaced by the respective partially closed phrases "consisting essentially of," consists essentially of," and the like or the respective closed phrases "consisting of," "consists of, the like.
As used herein, the singular forms “a”, “an”, and “the” designate both the singular and the plural, unless expressly stated to designate the singular only.
FIG. 1A illustrates a block diagram of a method 100 for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system, according to an embodiment of the present invention. The method 100 may comprise following steps.
At 102, connecting an insulation monitoring device (IMD) between a positive terminal (D+) and a negative terminal (D-) of a direct current (DC) source voltage (VDC), applied excitation voltage (Vs) and a protective earth.
At 104, measuring alternately insulation resistance through positive and negative arms of the insulation monitoring device upon power-up.
The insulation resistance may be measured alternatively through positive and negative arms at zero-volt DC (VDC) by applying DC excitation voltage (Vs) pulses.
At 106, allowing detection of symmetrical and asymmetrical insulation conditions.
At 108, detecting insulation fault occurring due to an insulation breakdown and/or at least one broken wire in supply lines.
At 110, stopping immediately the measuring circuit via an online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system.
At 112, generating a first alarm as a warning and a second alarm as a fault.
At 114, keeping the insulation measurement relay (IMR) in the fault condition unless and until the fault is resolved by recovery of the insulation break down and/or detection and recovery of the broken wire.
At 116, utilizing a two-point calibration to enhance measurement accuracy.
FIG. 1B illustrates a simulation circuit for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system, according to an embodiment of the present invention.
In an embodiment of the present disclosure, the online DC Insulation monitoring device (IMD) may be used to monitor the insulation resistance between the live supply D+ and D-, monitoring of insulation resistance even with DC supply is zero with DC excitation pulses, monitoring of supply lines D+/D- and the earth in the electrical system. The online DC IMD may detect the insulation fault when the insulation between live supply conductors and the earth breaks down and the broken wire may be detected for supply lines D+ and D-.
FIG. 1C illustrates a simulation circuit for current flow (Im1), when the first switch (SW1) is closed and the third switch (SW3) is closed, the second switch (SW2) and the fourth switch (SW4) is open and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention.
FIG. 1D illustrates a simulation circuit for current flow (Im2), when the first switch (SW1) is closed and the third switch (SW3) is closed, the second switch (SW2) and the fourth switch (SW4) is open and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention.
The calculation of insulation resistance may be with both the direct current (DC) source voltage (VDC) and an applied excitation voltage (Vs) being in active state is performed, having a first switch (SW1) and a third switch (SW3) closed and a second switch (SW2) and a fourth switch (SW4) open.
As per Kirchhoff’s Voltage Law,
Vs – (Im1*RisoN) + VDC + (Im1 + Im2) * (Rstp + Rin) = 0
Where (Im1 + Im2) = VP / (Rstp + Rin) --------------------- equation 1
Vs + VDC – (Im1 * RisoN) – VP = 0
Im1 = (Vs+ VDC – VP) / RisoN ----------------------------- equation 2
Vs – (Im2 * RisoP) – (Im1 + Im2) * (Rstp + Rin) = 0
Vs – VP – (Im2 * Risop) = 0
Im2 = (Vs – VP) / RisoP --------------------------------- equation 3

FIG. 1E illustrates a simulation circuit for current flow (Im3), when the second switch (SW2) is closed and the third switch (SW3) is closed, the first switch (SW1) and the fourth switch (SW4) is open and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention.
FIG. 1F illustrates a simulation circuit for current flow (Im4), when the second switch (SW2) is closed and the third switch (SW3) is closed, the first switch (SW1) and the fourth switch (SW4) is open and the direct current (DC) source voltage (VDC) is active, according to an embodiment of the present invention.
The calculation of insulation resistance may be with both the direct current (DC) source voltage (VDC) and the applied excitation voltage (Vs) being in active state is performed, having the first switch (SW1) and the fourth switch (SW4) open and the second switch (SW2) and the third switch (SW3) closed.
Vs – (Im3 * RisoP) – VDC – (Im3 + Im4) * (Rstn + Rin) = 0
(Im3 + Im4) = VN/(RstN + Rin) --------------------------- equation 4
Im3 = Vs – VDC – VN/RisoP ------------------------------- equation 5
Vs – (Im4 * RisoN) – (Im3 + Im4) * (RstN + Rin) = 0
Im4 = (Vs– VN)/ RisoN ------------------------------ equation 6
Solving equation 1 to 6
RisoP = (Rstp + Rin) * ((VDC * (VDC + VN – VP))/ ((VP * Vs) – ((VN * (Vs + VDC)))
RisoN = (Rstn + Rin) * ((VDC * (VP – VN – VDC))/ ((VP * (Vs – VDC)) – (VN * Vs))
FIG. 1G illustrates a simulation circuit for current flow (Im1), when the direct current (DC) supply input is active with the direct current (DC) source voltage (VDC) at zero volts and excitation signal (Vs) is active, according to an embodiment of the present invention.
The calculation of insulation resistance may be with the direct current (DC) source voltage (VDC) at zero and the applied excitation voltage (Vs) in active state is performed, having the first switch (SW1) and the third switch (SW3) closed, and the second (SW2) and the fourth switch (SW4) open.
When SW1 is closed as per Kirchhoff’s voltage law,
Vs – Im1 * ((RisoP * RisoN)/(RisoP + RisoN)) – Im1 * (Rstp + Rin) = 0
Im1 = VP/(Rstp + Rin)
((RisoP * RisoN)/(RisoP + RisoN)) = (Vs – VP)/Im1
Hence, parallel combination of RisP & RisoN = (Rstp + Rin) * (Vs – VP)/VP.
FIG. 1H illustrates a simulation circuit block for current flow (Im2), when the direct current (DC) supply input is active with the direct current (DC) source voltage (VDC) at zero volts and excitation signal (Vs) is active, according to an embodiment of the present invention.
The calculation of insulation resistance may be with the direct current (DC) source voltage (VDC) at zero and the applied excitation voltage (Vs) in active state is performed, having the switch (SW2) and the third switch (SW3) closed, and the switch (SW1) and the fourth switch (SW4) is open.
Similarly, when SW2 is closed as per Kirchoff’s Voltage law,
Vs – Im2 * ((RisoP * RisoN)/(RisoP + RisoN)) – Im2 * (Rstp + Rin) = 0
Im2 = VP/(Rstp + Rin)
((RisoP * RisoN)/(RisoP + RisoN)) = (Vs – VN)/Im2
Hence, parallel combination of RisoP & RisoN = (RstN +Rin) * (Vs-VN)/VN.
FIG. 1I illustrates a simulation circuit for broken wire detection, when the first switch (SW1) and the fourth switch (SW4) is closed, the third switch (SW3) and the second switch (SW2) is open and the direct current (DC) source voltage (VDC) is zero volts, according to an embodiment of the present invention.
The detection of the broken wires in a direct current (DC) supply may further comprise monitoring the voltage across the positive terminal (D+) and the negative terminal (D-) of the live voltage supply. The method 100 may further comprise determining if the voltage across the positive terminal (D+) and the negative terminal (D-) is less than a prespecified value. The method 100 may further comprise applying an excitation voltage (Vs) through the fourth switch (SW4), the first switch (SW1) closed and the second switch (SW2) and the third switch (SW3) open, to the measurement ground (GND iso). The method 100 may further comprise measuring the voltage between the positive terminal (D+) and the measurement ground (GND iso). The method 100 may further comprise concluding a broken wire condition if the measured voltage between terminal D positive terminal (D+) and the measurement ground (GND iso) is near 0V. The method 100 may further comprise concluding no broken wire if the measured voltage is greater than 90% of the applied excitation voltage (Vs).
In an exemplary embodiment, the voltage across “D+” and “D-” is greater than 75% of rated voltage, then no need to check for open detect as voltage is available. In another exemplary embodiment, the voltage across “D+” and “D-” is less than 10V, then there is a need to check for open detect. The excitation voltage may be applied through the fourth switch (SW4) and the measurement ground “GND iso”. Then, voltage is measured in D+ and measurement ground “GND iso”. If there is wire break in either of “D+” or” D-” or both, then voltage at “D+” and “GND iso” will be near about 0V. In this case it is concluded that, there is wire break [Open detected]. Also, if voltage obtained in between “D+” and “GND iso” is greater than 90% of applied “excitation voltage considering the drop due to internal impedance of source, then it is concluded that there is no break.
In an exemplary embodiment, when the DC supply input is inactive i.e. VDC = 0 or DC supply is open, the excitation signal (Vs) is active and broken supply wire i.e. D+ or D-. The DC supply input (VDC) and DC excitation signal (Vs) and additional switch circuitry is used to broken wired detection for the signal for the insulation resistance measurement. The broken wire detection comes in pictured only when the DC source voltage is zero or the DC source voltage is open.
FIG. 1J illustrates a simulation circuit for calibration of D+ and D- Arm with the third switch (SW3) closed and the fourth switch (SW4) open, according to an embodiment of the present invention.
The two-point calibration may enable good accuracy towards lower resistance values.
The voltage calibration for the positive terminal (D+) arm with the direct current (DC) source voltage (VDC) set to higher voltage may further include keeping the first simulated resistance (RisoP) at high and keeping the second simulated resistance (RisoN) opened. The method 100 may further comprise keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method 100 may further comprise switching ON the voltage supply and measuring a first actual ADC value (Actual value1) by closing the first switch (SW1) and the third switch (SW3), the second switch (SW2) and the fourth switch (SW4) remain open to obtain a first calculation value (Cal point 1). The method 100 may further comprise keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened. The method 100 may further comprise keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method 100 may further comprise measuring a second actual ADC value (Actual value2) by closing the first switch (SW1) and the third switch (SW3), the second switch (SW2) and the fourth switch (SW4) remain open to obtain a second calculation value (Cal point 2). The method 100 may further comprise calculating a positive ARM voltage value (VP) based on ADC reading.

offset=((Actual Value2-ActualValue1)/(Cal point2 value-Cal point1 value))*(-Cal point1 value)+ActualValue1
GainFactor=Cal point2 value/(ActualValue2-offset)

CalValue=(AdcReading in Voltage-offset)*GainFactor

The voltage calibration for the negative terminal (D-) arm with the direct current (DC) source voltage (VDC) set to higher voltage may further include keeping the first simulated resistance (RisoP) at low and keeping the second simulated resistance (RisoN) opened. The method 100 may further comprise keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method 100 may further comprise switching ON the voltage supply and measuring the first actual ADC value (Actual value1) by closing the second switch (SW2) and the third switch (SW3), the first switch (SW1) and the fourth switch (SW4) remain open to obtain the first calculation value (Cal point 1). The method 100 may further comprise keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened. The method 100 may further comprise keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input. The method 100 may further comprise measuring the second actual ADC value (Actual value2) by closing second switch (SW2) and the third switch (SW3), the first switch (SW1) and the fourth switch (SW4) open to obtain the second calculation value (Cal point 2). The method 100 may further comprise calculating a negative ARM voltage value (VN) based on ADC reading.

offset=((Actual Value2-ActualValue1)/(Cal point2 value-Cal point1 value))*(-Cal point1 value)+ActualValue1
GainFactor=Cal point2 value/(ActualValue2-offset)

CalValue=(AdcReading in Voltage-offset)*GainFactor

The voltage calibration for the positive terminal (D+) arm and the negative terminal (D-) arm with the direct current (DC) source voltage (VDC) set to zero or lower voltage may further include keeping the first simulated resistance (RisoP) at low and keeping the second simulated resistance (RisoN) opened. The method 100 may further comprise keeping the direct current (DC) source voltage (VDC) at zero volt. The method 100 may further comprise switching ON the voltage supply and measuring the first actual ADC value (Actual value1) by closing the first switch (SW1) to measure the positive ARM voltage value (VP) to obtain the first calculation value (Cal point 1) and measuring the negative ARM voltage value (VN) by closing the second switch (SW2) to obtain the first calculation value (Cal point 1). The method 100 may further comprise keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened. The method 100 may further comprise keeping the direct current (DC) source voltage (VDC) at zero. The method 100 may further comprise measuring the second actual ADC value (Actual value2) by closing second switch (SW2) to obtain the second calculation value (Cal point 2). The method 100 may further comprise calculating the negative ARM voltage value (VN) based on ADC reading. The method 100 may further comprise measuring the actual ADC value (i.e. Actual value2) for the positive ARM voltage value (VP) by closing first switch (SW1) and for the negative ARM voltage value (VN) by closing second switch (SW2) and calculating the second calculation value (Cal point 2).

offset=((Actual Value2-ActualValue1)/(Cal point2 value-Cal point1 value))*(-Cal point1 value)+ActualValue1
GainFactor=Cal point2 value/(ActualValue2-offset)

CalValue=(AdcReading in Voltage-offset)*GainFactor
The method 100 meets the requirements specified by safety standard IEC61557-8. The method 100 meets measuring voltage & current maximum ratings. The method 100 meets peak value of measurement voltage (Um) < 120 V at an infinite value of insulation resistance. The method 100 has measurement current (Im) < 10mA at insulation resistance = 0. The method 100 has internal DC resistance Ri > = 30 Ohm/ vol * nominal supply voltage (Ri min = 15Kohm or Zi min= 1.8Kohm. The method 100 has capability of symmetrical and asymmetrical insulation resistance monitoring. The method 100 has insulation warning current defined as 2mA, meaning waring flag or indication is set when insulation. The method 100 has resistance < = VBUS voltage * 500 Ohm/V. Thus, for 1000V DC supply, Ran i.e. specified insulation threshold would be 500K. The method 100 has insulation fault current defined as 10mA, meaning waring flag or indication is set when insulation. The method 100 has resistance < = VBUS voltage * 100 Ohm/V. Thus, for 1000V DC supply, Ran i.e. specified insulation threshold would be 100K. The method 100 provides visual indication through HMI (LIW) or RIW relayed through data communication channel or by relay output or electronic switching output. The method 100 has provision for permanent setting of Specified response value (Ran) as fixed or adjustable via user interface or communication channel. Firmware security (key or password or tool) is required for adjustable setting. The method 100 may use an insulation measurement device (IMD) may be capable of monitoring insulation resistance up to the system leakage capacitance Ce = 1uF to max. with Relative % uncertainty (A) (i.e. insulation resistance monitoring accuracy) <+/-15% & Response time(tan) < 100s for DC insulation measurement device.
The present invention offers many advantages over the traditional methods. The method 100 enhances the safety, reliability, and efficiency of DC IT systems through improved insulation resistance measurement and calibration techniques. The method 100 even allows for accurate insulation resistance measurement even when the DC IT system is not active.
The method 100 may achieve low manufacturing cost of a product. The method 100 may be provide faster results as compared to the traditional methods. The method 100 may have ADC’s full-scale range that may be used for better resolution and accuracy. The two point’s calibration methods as described above may be used for insulation resistance measurement circuit and voltage source measurement. In addition, for failsafe design, power on self-test and on-the-fly tests will be conducted for PE ground connection checking, excitation voltage & DC input supply voltage presence.
The method 100 also ensures compliance with IEC/EN 61557-8 requirements to guarantee the reliability and standardization of the procedure. The method 100 enables advanced calibration to improve the accuracy of the measured insulation resistance values. The method 100 also ensures easy integration with the measurement process without requiring significant modifications.
The method 100 also provides a reliable and safe means of measuring insulation resistance in DC IT systems and reduces the risk of undetected insulation faults. Therefore, the present invention enhances overall maintenance and diagnostics by providing accurate and timely insulation resistance data. The method 100 ensures easy implementation without requiring extensive training or specialized knowledge.
The method 100 is versatile and compatible with a wide range of DC IT systems and configurations. Further, it is also integrable with other monitoring and diagnostic tools to provide a comprehensive health overview for a system. The method 100 ensures that the insulation measurement provides consistent, accurate, and reliable insulation resistance results. The method 100 also facilitates effective insulation resistance monitoring and thereby, support proactive maintenance practices that extend the life of the overall system
While the invention has been described in connection with what is presently considered to be the most practical and various embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements within substantial differences from the literal languages of the claims.
, C , Claims:CLAIMS
I/We Claim:
1. A method (100) for online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system, the method (100) comprising:
connecting an insulation monitoring device (IMD) between a positive terminal (D+) and a negative terminal (D-) of a direct current (DC) source voltage (VDC), applied excitation voltage (Vs) and a protective earth;
measuring alternately insulation resistance through positive and negative arms of the insulation monitoring device upon power-up,
wherein the insulation resistance is measured alternatively through positive and negative arms at zero-volt DC (VDC) by applying DC excitation voltage (Vs) pulses;
allowing detection of symmetrical and asymmetrical insulation conditions;
detecting insulation fault occurring due to an insulation breakdown or at least one broken wire in supply lines;
stopping immediately the measuring circuit via an online direct current (DC) insulation measurement, and insulation fault location for ungrounded power supply system;
generating a first alarm as a warning and a second alarm as a fault;
keeping the insulation measurement relay (IMR) in the fault condition unless and until the fault is resolved by recovery of the insulation break down and/or detection and recovery of the broken wire; and
utilizing a two-point calibration to enhance measurement accuracy.
2. The method (100) as claimed in claim 1, wherein the calculation of insulation resistance with both the direct current (DC) source voltage (VDC) and an applied excitation voltage (Vs) being in active state is performed, having a first switch (SW1) and a third switch (SW3) closed and a second switch (SW2) and a fourth switch (SW4) open.
3. The method (100) as claimed in claim 1, wherein the calculation of insulation resistance with both the direct current (DC) source voltage (VDC) and the applied excitation voltage (Vs) being in active state is performed, having the first switch (SW1) and the third switch (SW3) open and the second switch (SW2) and the fourth switch (SW4) closed.
4. The method (100) as claimed in claim 1, wherein the calculation of insulation resistance with the direct current (DC) source voltage (VDC) at zero and the applied excitation voltage (Vs) in active state is performed, having the first switch (SW1) closed and the third switch (SW3) closed and the second switch (SW2) and the fourth switch (SW4) open.
5. The method (100) as claimed in claim 1, wherein the calculation of insulation resistance with the direct current (DC) source voltage (VDC) at zero and the applied excitation voltage (Vs) in active state is performed, having the second switch (SW2) closed and the third switch closed and the first switch (SW1) and the fourth switch (SW4) open.
6. The method (100) as claimed in claim 1, wherein the detection of the broken wires in a direct current (DC) supply further comprises:
monitoring the voltage across the positive terminal (D+) and the negative terminal (D-) of the live voltage supply;
determining if the voltage across the positive terminal (D+) and the negative terminal (D-) is less than a prespecified value;
applying an excitation voltage (Vs) through the fourth switch (SW4), with the first switch (SW1) closed and the second switch (SW2) and the third switch (SW3) open, to the measurement ground (GND iso);
measuring the voltage between the positive terminal (D+) and the measurement ground (GND iso);
concluding a broken wire condition if the measured voltage between the positive terminal (D+) and the measurement ground (GND iso) is near 0V; and
concluding no broken wire if the measured voltage is greater than 90% of the applied excitation voltage (Vs).
7. The method (100) as claimed in claim 1, wherein the two-point calibration enables good accuracy towards lower resistance values.
8. The method (100) as claimed in claim 7, wherein the voltage calibration for the positive terminal (D+) arm with the direct current (DC) source voltage (VDC) set to higher voltage further includes:
keeping the first simulated resistance (RisoP) at high and keeping the second simulated resistance (RisoN) opened;
keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input;
switching ON the voltage supply and measuring a first actual ADC value (Actual value1) by closing the first switch (SW1) and the third switch (SW3), the second switch (SW2) and the fourth switch (SW4) remain open to obtain a first calculation value (Cal point 1);
keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened;
keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input;
measuring a second actual ADC value (Actual value2) by closing the first switch (SW1) and the third switch (SW3), the second switch (SW2) and the fourth switch (SW4) remain open to obtain a second calculation value (Cal point 2); and
calculating a positive ARM voltage value (VP) based on ADC reading.
9. The method (100) as claimed in claim 7, wherein the voltage calibration for the negative terminal (D-) arm with the direct current (DC) source voltage (VDC) set to higher voltage further includes:
keeping the first simulated resistance (RisoP) at low and keeping the second simulated resistance (RisoN) opened;
keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input;
switching ON the voltage supply and measuring the first actual ADC value (Actual value1) by closing the second switch (SW2) and the third switch (SW3), the first switch (SW1) and the fourth switch (SW4) remain open to obtain the first calculation value (Cal point 1);
keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened;
keeping the direct current (DC) source voltage (VDC) at high and/or at maximum voltage and applying between the direct current (DC) supply input;
measuring the second actual ADC value (Actual value2) by closing second switch (SW2) and the third switch (SW3), the first switch (SW1) and the fourth switch (SW4) remain open to obtain the second calculation value (Cal point 2); and
calculating a negative ARM voltage value (VN) based on ADC reading.
10. The method (100) as claimed in claim 7, wherein the voltage calibration for the positive terminal (D+) arm and the negative terminal (D-) arm with the direct current (DC) source voltage (VDC) set to zero or lower voltage further includes:
keeping the first simulated resistance (RisoP) at low and keeping the second simulated resistance (RisoN) opened;
keeping the direct current (DC) source voltage (VDC) at zero volt;
switching ON the voltage supply and measuring the first actual ADC value (Actual value1) by closing the first switch (SW1) to measure the positive ARM voltage value (VP) to obtain the first calculation value (Cal point 1) and measuring the negative ARM voltage value (VN) by closing the second switch (SW2) to obtain the first calculation value (Cal point 1);
keeping the second simulated resistance (RisoN) at a lower value and keeping the first simulated resistance (RisoP) opened;
keeping the direct current (DC) source voltage (VDC) at zero;
measuring the second actual ADC value (Actual value2) by closing second switch (SW2) to obtain the second calculation value (Cal point 2);
calculating the negative ARM voltage value (VN) based on ADC reading; and
measuring the actual ADC value (i.e. Actual value2) for the positive ARM voltage value (VP) by closing first switch (SW1) and for the negative ARM voltage value (VN) by closing second switch (SW2) and calculating the second calculation value (Cal point 2).