Description:The motivation behind this work is design and develop of a lightweight block cipher algorithm that can provide strong encryption while minimizing the use of resources. The proposed algorithm takes advantage of the benefits of both SP-type and Feistel-type network structures to create a novel encryption method that can support 256-bit keys and 64-bit data blocks, which are commonly used in block cipher design. The SP-type network structure is based on the substitution-permutation (SP) type network, which applies a substitution and permutation layer to the plaintext in a parallel fashion. The Feistel-type network structure, on the other hand, uses a series of rounds to encrypt the plaintext, where each round involves splitting the plaintext into two halves, applying a function to one half, and then XOR ing the output of the function with the other half before swapping the two halves and repeating the process. The proposed block cipher algorithm combines the SP-type and Feistel-type network structures to create a hybrid encryption method that takes advantage of the strengths of both structures. The proposed block cipher algorithm supports 256-bit keys and 64-bit data blocks, which makes it suitable for use in resource-constrained environments such as IoT devices.
Here, a method is given that employs bit jumbling, concatenation, and simple logical XOR operations. As a result, only a person with access rights may decrypt the data for use the disclosed system was designed to be as lightweight as feasible and employs 64 bits of unencrypted data.

The disclosed system was designed to be as lightweight as feasible and employs 64 bits of unencrypted data. The big block of data is divided into several blocks of 32 bits as a result, each of which is handled by a distinct data channel. The procedure is repeated for any additional data blocks. The output of processing each data block is integrated to form the encrypted data. Eight 32-bit sub keys that are created from the primary key are used in many rounds of encryption. Good performance for devices with constrained resources requires Enciphering using the suggested method requires little power, little memory, and little storage space.

Figure.2 illustrates an encryption process of proposed block cipher in accordance with an embodiment of the present disclosure. Eight sub keys each of 32-bit width (SK_1, SK_2, SK_3, SK_4, SK_5, SK_6, SK_7 and SK_8) are derived from the eight round keys obtained by splitting the main 256 bits key in eight parts in the proposed method of encryption process and decryption process. By feeding various sub keys into various F-functions of several rounds of encryption, a strong but straightforward key generation method has been developed in response to the necessity to create a lightweight encryption process. Eight separate sub key sequences are used in eight different levels of round operation during the eight different encryption rounds, as was previously described, to ensure resilience against related key assaults. Key generation technique includes a diagram of the sub key creation strategy. The newly developed method skips over a number of monotonous operations, including XOR gates and F-function for eight iterative operations. After each cycle, intermediate cypher text outputs are produced and promptly fed into the following round. The final cypher text output is produced when ten successive rounds have been completed (CT).
The proposed lightweight cryptography system is reportedly designed and developed in Verilog, and its correctness is confirmed using Xilinx Vivado 2018.2 to run a behavioural simulation that takes two inputs: 64 bits of plaintext and 256 bits of key, which results in 64 bits of cipher text are output. To validate the real-time implementation of the recently developed encryption system, a smaller version of the algorithm, requiring 16 bits of input for both the key and the plaintext, is put into practice on the Artix 7 FPGA board.
We have designed a new block cipher that supports 64 bits of plaintext and 256 bits of key. The new cipher has a gate equivalent area (GE) of only 960, which is significantly lesser than 1000 that’s why it can be called as a ultra-lightweight block cipher .This means that the new cipher uses fewer gates, which reduces computational delay while still maintaining a high level of security through bit jumbling and repeating. Compared to other lightweight variants, this block cipher consumes only 2.89 mW of power, which is relatively low. This makes the cipher architecture well-suited for applications where power consumption and compact area are the primary limitations, such as in low-power embedded systems or IoT devices. The delay of a cryptographic algorithm refers to the time it takes for the algorithm to encrypt a given input. In general, a lower delay is desirable, as it allows the algorithm to process data more quickly and efficiently. The lower delay of the proposed block cipher design can be seen as a significant advantage over existing block ciphers, especially in applications where fast processing of large amounts of data is required. , Claims:We Claim:
1. A Different encryption method has been introduced that combines the benefits of both SPN-type and Feistel-type network structures.
2. Comprising a processor configured to execute encryption and decryption operations using the combined SPN and Feistel Network structures.
3. Comprising memory resources for storing encryption keys and intermediate data generated during encryption and decryption processes.
4. A method for generating encryption keys compatible with the lightweight encryption method of utilizing techniques optimized for IoT devices to ensure cryptographic strength and key entropy.
5. A method for securely updating the encryption algorithm and encryption keys used by IoT devices.
6. It can be used in be used in central processing units block for security purposes.