Description:Complete Specification:
The following specification describes and ascertains the nature of this invention and the manner in which it is to be performed.

Field of the invention:
[0001] The present invention relates to a global event monitoring unit for timing analysis on a System-on-Chip (SoC).

Background of the invention:
[0002] As it is known, silicon fabrication is one of the prime and vital steps of Integrated Chip (IC) manufacturing process. Before this step i.e., during the development stage, a plethora of ways are deployed to verify the IC in terms of functionality, performance, reliability and any such metrics. This is all possible by use of various simulation, emulation environments and tools. These tools provide access to the internal signals of all the peripherals of the IC/System on Chip (SoC). Along with their many use-cases, these signals are essential and can be conveniently used for timing analysis (of various internal events in SoC) - which is critical in optimizing the design and fixing major bugs before design is finalized.

[0003] Once the IC is fabricated, similar timing analysis becomes a very challenging task as the internal signals are completely inaccessible. However, there are some conventional methods in use to measure time interval between a set of events as described below in brief. The methods are Status polling, Interrupt Service Routine (ISR) and using external devices. In the status polling status register is read in a loop to capture an event(s). In ISR interrupts from various peripherals used to capture an event(s). The use of external devices comprises probing General Purpose Input Output (GPIOs) on SoC by devices like Cathode Ray Oscilloscope (CRO), a Digital Storage Oscilloscope (DSO) to capture a signal(s) or event(s).

[0004] All the above methods possess certain limitations described briefly as follows. In status polling, there is software overhead, wastage of Central Processing Unit (CPU) bandwidth. Only the module Special Function Register (SFRs) is readable which means, the internal signals whose status is not logged in registers are not usable for event capturing. There is a possibility that the status polling is interrupted by a higher priority task or interrupt in multitasking environment. In ISR, there is Software overhead, interrupt latency, interrupts are available only for limited number of internal signals, interrupt pre-emption by higher priority interrupt, etc. Similarly, the use of external devices involves complex and costly setups and, in this case, only the externally available GPIO signals are usable, and it is a time-intensive activity. Owing to these limitations, the precise timing measurement between events is not always possible – which is a decisive factor in optimizing system design and validation of system timing specification.

[0005] According to a patent literature US2013339638, status polling of memory devices using an independent status bus is disclosed. Apparatus includes multiple memory devices and a memory controller. The memory controller is configured to store and retrieve data by communicating with the memory devices over a first bus interface, and to query a status of the memory devices by communicating with the memory devices over a second bus interface that is separate from the first bus interface.

Brief description of the accompanying drawings:
[0006] An embodiment of the disclosure is described with reference to the following accompanying drawings,
[0007] Fig. 1 illustrates a block diagram of a global event monitoring unit for an SoC, according to an embodiment of the present invention, and
[0008] Fig. 2 illustrates an example use case of the global event monitoring unit, according to an embodiment of the present invention.

Detailed description of the embodiments:
[0009] Fig. 1 illustrates a block diagram of a global event monitoring unit for an SoC, according to an embodiment of the present invention. The global event monitoring unit (GEMU) 100 comprises, characterized in that, an accumulator module 110 which comprises at least one mode to receive an input signal for at least one event, a logger module 120 to measure time interval for said at least one event, and a handler module 132 to enable generation of interrupts for the at least events logged by the logger module 120. The handler module 132 is shown within the logger module 120 but the same is possible to be separate. The at least one mode comprises a Port signal Block 102, internal signal Multiplexer (Mux) block 104, a Module Special Function Register (SFR) block 106 (or SFR module block) and a host (Central Processing Unit (CPU)) 108 or host controlled block. Each of the modes is further selectable through a primary multiplexer (Mux) 174 through a selector register 112. The output of the primary Mux 174 is event status 114. The module, sub-module, blocks are usable in interchangeable manner as they mean to refer a specific component. Also, the term “global” refers to internal and external source of signals with respect to the SoC for the at least one event.

[0010] The external accumulator module 110 captures/records global events accurately from GPIO signals 138 through port signal block 102, internal output signals from peripheral modules on SoC, module SFR block 106, and direct host CPU 108 or host controlled block. Generally, software are used to read module register contents to capture the event whenever required. But as per the global event monitoring unit 100, it is possible to do the same with higher precision (as the hardware is involved instead of software). The logger module 120 uses the captured global events to accurately measure time interval therebetween. An optimized hardware/system is implemented to re-use the accumulator module 110 to capture these events. The handler module 132 supports easy, flexible, and accurate event handling during run time by generating interrupt(s) to the core, in correspondence to the logged events, thus reducing the load on CPU. The add-on is that in case of events which does not generate a direct interrupt, the global event monitoring unit 100 is enabled to generate the interrupt to the core by processing content of the module SFR block 106. A robust Finite State Machine (FSM) is designed to manage the internal state transitions of the global event monitoring unit 100 in a precise manner.

[0011] According to an embodiment of the present invention, the port signal block 102 comprises interface to connect with required General Purpose Input Output (GPIO) pins to receive an input 138. The internal signal Mux 104 comprises access to internal signals of different modules on the SoC, and the Module SFR block 106 is able to read module registers. The Port Signal Block 102 comprises a first multiplexer (Mux) 140 that is able to access all the available/required GPIO signals and an edge detection module 144. The edge detection module 144 comprises a logic which gives provision to detect a specific number of programmed edges of the selected GPIO signal before raising an event for further processing. The edge detection module 144 is configured to detect rising edge of a signal, a falling edge of the signal and either of rising and falling edge of the signal. Once detected, a counter 146 counts and stores as a count value which is compared with a target count 148 stored in a memory unit through a first comparator 150. This helps in measurement of timing characteristics of modules such as Serial Peripheral Interface (SPI), Inter-Integrated-Circuit (I2C), Universal Asynchronous Reception and Transmission (UART), etc. Further, the output from the first Mux 140 is possible to be directly sent for further processing bypassing the counter 146 through a switch 147. Further, a port signal select register 142 is provided to configure port signal block 102.

[0012] According to an embodiment of the present invention, the Internal Signal Mux 104 comprises access to specific signals from various modules on the SoC (these signals can correspond to interrupts or Direct memory access (DMA) triggers or any other output signals chosen during system integration for event logging purposes). The captured signal are used to raise an event to further blocks. An Internal module signal select register 156 is provided as input to a second Multiplexer (Mux) 154. The second input 152 to the Internal Signal Mux 104 is selectable from but not limited to SPI, I2C, MCAN and Mod n.

[0013] According to an embodiment of the present invention, the Module SFR block 106 which is a bus master that is able to access 160 the module status registers in read-only mode (read access to all the registers is possible but left to the programmer’s discretion as it might cause unexpected module behavior). When the value read from status register matches the expected value, an event is raised to further blocks. The module SFR block 106 comprises an Advanced High-Performance Bus (AHB) master 162 that is able to initiate the communication on AHB bus 158 and perform only read transaction from the SFR memory space of different modules (Ex: CAN, SPI, I2C etc.). The user needs to provide the SFR address 164 and then AHB master 162 reads data from the SFR memory space periodically through the system bus (AHB bus 158). Along with the SFR address 164, the user needs to configure the bit mask value and expected value 172 in the Module SFR block 106. Once the data is read by the AHB bus master 162, it is masked by bit mask 166 and finally a third comparator 170 compares the current data value 168 (masked data) with the expected value 172 and raises the event to the further blocks in case there is a match.

[0014] The global event monitoring unit 100 comprises a provision to raise the event to further blocks through direct host 108 or host controlled block (in case above mentioned accumulation methods are not feasible).

[0015] The global event monitoring unit 100 is a hardware unit fabricated on chip on the SoC along with the Central Processing Unit (CPU). According to the present invention, the logger module 120 of the global event monitoring unit 100 comprises a timer 124 to log time of the at least one event from start to end of the input signal using a start latch 116 and an end latch 118. The timer 124 is aided by division sub-module 122 for time calculation. A memory unit (not shown) to store logged timing of the at least one event, a statistic sub-module 126 to generate statistics using the logged timing and a fourth comparator 130 to compare the processed value 128 with a threshold time. The processed value 128 corresponds to either the logged time from the timer 124 or processed logged time from the statistic sub-module 126. The statistic sub-module 126 is optional and is bypassed when needed as shown by the dashed line. In an embodiment, the statistic sub-module 126 is configurable to process logged timings to determine mean, minimum, maximum values for logged at least one event.

[0016] According to the present invention, the handler module 132 comprises an enabler to support generation of at least three types of interrupts, process done, timeout and overflow. The enabler is further controlled by enable/disable register 134. The interrupt is forwarded to internal modules (such as the CPU) and/or external modules for analysis.

[0017] In accordance to an embodiment of the present invention, the global event monitoring unit 100 is made part of a controller or control unit which is provided with necessary signal detection, acquisition, and processing circuits. The controller is the one which comprises input interface, output interfaces having pins or ports, the memory element (not shown) such as Random Access Memory (RAM) and/or Read Only Memory (ROM), Analog-to-Digital Converter (ADC) and a Digital-to-Analog Convertor (DAC), clocks, timers, counters and at least one processor (capable of implementing machine learning) connected with each other and to other components through communication bus channels. The memory element is pre-stored with logics or instructions or programs or applications or modules/models and/or threshold values/ranges, reference values, predefined/predetermined criteria/conditions, which is/are accessed by the at least one processor as per the defined routines. The internal components of the controller are not explained for being state of the art, and the same must not be understood in a limiting manner. The controller may also comprise communication units such as transceivers to communicate through wireless or wired means such as Global System for Mobile Communications (GSM), 3G, 4G, 5G, Wi-Fi, Bluetooth, Ethernet, serial networks, and the like. The controller is implementable in the form of System-in-Package (SiP) or System-on-Chip (SoC) or any other known types. Examples of controller comprises but not limited to, microcontroller, microprocessor, microcomputer, etc.

[0018] Further, the processor may be implemented as any or a combination of one or more microchips or integrated circuits interconnected using a parent board, hardwired logic, software stored in the memory element and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). The processor is configured to exchange and manage the processing of various Artificial Intelligence (AI) modules.

[0019] The global event monitoring unit 100 is applicable for at least one selected from a group comprising but not limited to a module calibration, critical module performance measurement, timing analysis of modules, event timeout, debug module’s internal process timings and multi-threading process synchronization.

[0020] The logger module 120 comprises the timer 124, the statistic sub-module 126 and the fourth comparator 130 as the functional blocks. The handler module 132 supports generation of three kinds of interrupts – “process done”, timeout and Overflow. The design allows these interrupt signals to be forwarded to other internal modules (for ex. GPIO) for debug purposes.

[0021] According to the present invention, a general working of the global event monitoring unit 100 is described. The global event monitoring unit 100 (also referred to as Global Interval Logger and Handler (GILH)) is designed to measure the time interval between various system events and to act as an event handler to reduce the CPU load. The system events is relayed to the global event monitoring unit 100 in four different modes, i.e., through port signal block 102, internal signal Mux 104, module SFR block 106 and host 108 or host controlled block. Any combination of the above mentioned modes are usable to notify the global event monitoring unit 100 about Start and Stop of at least one event.

[0022] The operation of the timer 124 is explained. The timer 124 starts measuring the time interval once the start event is latched. When Stop event is latched, “process done” interrupt is generated, and the time interval recorded by the timer 124 is readable from the register based on requirement. In case the measured time interval exceeds the programmed timeout value 136 (such as threshold time), a timeout interrupt is raised. Necessary decisions can be taken by the CPU in such cases. If the measured time interval exceeds the range of the counter used, an overflow interrupt is generated. This acts as a safeguard mechanism when the above two interrupts could not be triggered due to unforeseen circumstances. The statistics sub-module 126 enables to compute minimum, maximum, mean values., etc., of the time interval over various iterations of a process. This is useful in scenarios such as calibration – where a precise time interval has to be calculated for various modules. During run time, the global event monitoring unit 100 is usable as an alternative to status polling method to achieve efficient and reliable handshake between Core and Peripherals.

[0023] Fig. 2 illustrates an example use case of the global event monitoring unit, according to an embodiment of the present invention. Consider a graph 200 illustrated in Fig. 2 where five signals are shown. The first four logic signals are for SPI, which are a Chip Select (active low signal from main to address subs and initiate transmission), referred to as CS 202, a Serial Clock (clock signal from main), referred to as SCLK 204, a Main Out Sub In (data output from main), referred to as MOSI 206, a Main In Sub Out (data output from sub) referred to as MISO 208. A fifth signal 210 is shown for DSPI_SRx.TCF. The DSPI is a SPI module present in a proprietary semiconductor modules. DSPIx_SR is the status register for SPI module x. TCF is the bitfield in SR register.

[0024] Two examples are shown. In a first example, the first time interval 212 is to be measured. Specifically, lead time (CS Active hold time) which is between CS falling edge first clock (rising) edge is to be measured. For this second example, kindly ignore the fifth signal 210. To measure the Interval using the global event monitoring unit 100, the following steps are performed assuming all the clock dividers are enabled.

[0025] For Start of Event of configuration,
a) Configure the MUX Select register to select particular port for CS signal in Port Signal Block 102.
b) Also Configure the block to detect falling edge. And configure the edge count to 1.
Similarly, for End of Event of configuration,
a) Configure the MUX Select register to select particular port for SCLK signal in Port Signal Block 102.
b) Also Configure the block to detect the rising edge. And configure the edge count to 1.
A different register interface are available to configure the START Event parameters and STOP event parameters. With the above steps, the configuration to capture different events are completed.

[0026] Now the global event monitoring unit 100 is in the RUN mode and waits for the event trigger. When the logger module 120 latches the START event, the STOP event parameters are re-configured in the accumulator module 110, and the time interval is stored in OUTPUT register of the timer 124. Finally, the process done interrupt is raised to the CPU.

[0027] In a second example, the internal timing characteristics of SPI need to be analyzed, i.e. SPI frame transmission completion time. To measure a second time interval 214 between CS 202 de-assertion to transmit complete flag (DSPI_SRx.TCF) assertion. To measure the second interval 214 using the global event monitoring unit 100, the following steps are performed assuming all the clock dividers are enabled.
For Start of Event of configuration
a) Configure the MUX in Port Signal Block 102.
b) Configure the block to detect rising edge (CS de-assertion). And configure the edge count to 1.
Similarly, for End of Event of configuration
a) Configure the SFR Address 164 of DSPIx_SR register in module SFR block 106.
b) Configure TCF bitfield mask as 0x80000000.
c) Configure Expected value 172 in the SFR block as 1.
With the above steps, the configuration to capture different events are completed.

[0028] Once the configuration is complete, the global event monitoring unit 100 is activated or run. In the activated or run mode, the global event monitoring unit 100 waits for the event trigger. After both start and stop events are captured, the time interval is logged by the timer 124 of the logger module 120 in an output register. Finally the process done interrupt is raised to the CPU by the logger module 120.

[0029] According to the present invention, the global event monitoring unit 100 or the Global event Interval Logger and Handler (GILH) is disclosed for timing analysis of at least one event on the SoC. The global event monitoring unit 100 is directed to improve efficiency in SoC by adding value in other application areas. The global event monitoring unit 100 need to be integrated on the SoC design itself (either during fabrication in fixed manner or in a removable manner) to efficiently perform the timing analysis of various internal signals and use the result for system optimization. The global event monitoring unit 100 is designed with dedicated hardware for the SoC which can be utilized for precise measurements of various timing parameters thus being the single alternative for existing non-accurate solutions. The timing measurement between global events is performed precisely. The global event monitoring unit 100 enables optimization of the system response time using the timing measurement results. The system performance evaluation becomes easy and effective. The timing characteristics of various modules can be validated with minimal intervention. The global event monitoring unit 100 is usable to poll the status of any global event.

[0030] It should be understood that the embodiments explained in the description above are only illustrative and do not limit the scope of this invention. Many such embodiments and other modifications and changes in the embodiment explained in the description are envisaged. The scope of the invention is only limited by the scope of the claims.
, Claims:We claim:
1. A global event monitoring unit (100) for a System-on-Chip (SoC), said global event monitoring unit (100) comprises, characterized in that,
an accumulator module (110) which comprises at least one mode to receive an input signal for at least one event;
a logger module (120) to measure time interval for said at least one event, and
a handler module (132) to enable generation of interrupts for said at least events logged by said logger module (120).

2. The global event monitoring unit (100) as claimed in claim 1, wherein said at least one mode comprises a Port signal Block (102), an internal signal Multiplexer (Mux) block (104), a Module Special Function Register (SFR) block (106) and a host (Central Processing Unit (CPU) module) (108).

3. The global event monitoring unit (100) as claimed in claim 2, wherein said port signal block (102) comprises a first multiplexer (Mux) (140) and an edge detection module (144), said first Mux (140) comprises an input connectable to General Purpose Input Output (GPIO) pins and an output usable as anyone of an input to said edge detection module (144) and as final output bypassing said edge detection module (144) through a switch (147), said edge detection module (144) connected to a counter (146) configurable to detect at least one of rising edge and a falling edge, and a first comparator (150) configurable to compare a count value of said counter (146) with a target count (148).

4. The global event monitoring unit (100) as claimed in claim 2, wherein said Module SFR block (106) comprises an Advanced High-performance Bus (AHB) master (162) connectable to a system Bus (158) of said SoC, said Module SFR block (106) comprises an address register (164) to receive an address for value retrieval from said system bus (158) and a third comparator (170) to compare retrieved value from said address register (164) with a configured expected value (172) for further processing.

5. The global event monitoring unit (100) as claimed in claim 1, wherein said logger module (120) comprises a timer (124) to log time from start to end of said input signal of said at least one event, a memory unit to store logged timing of said at least one event, a statistic sub-module (126) to generate statistics using said logged timing and a fourth comparator (130) to compare said logged time with a threshold time (136).

6. The global event monitoring unit (100) as claimed in claim 5, wherein said statistic sub-module (126) configured to process logged timings to determine at least one of a mean, a minimum, a maximum value for said at least one event.

7. The global event monitoring unit (100) as claimed in claim 1, wherein said handler module (132) comprises an enabler to support generation of at least three types of interrupts, process done, timeout and overflow, wherein said interrupt is forwarded to internal and/or external modules for analysis.

8. The global event monitoring unit (100) as claimed in claim 1 is a hardware unit fabricated on chip on said SoC along with a Central Processing Unit (CPU).

9. The global event monitoring unit (100) as claimed in claim 1 is applicable for at least one of module calibration, critical module performance measurement, timing analysis of modules, event timeout, debug module’s internal process timings and multi-threading process synchronization.