1. Title
[001] Status display ~scheme for Single Board Computer (830) in an
airborne communication system.
2. Field of Invention:
[002] The field of invention is related to Single Board Computer (580)
used in an airborne communication system. °
3. Background of the invention
[003] Single board computer (SBC)(1) are high density Printed Circuit
Boards (PCB)s. Single board computers (SEC) (1) consists of many
processing devices, mixed signal devices, networking devices and other
devices which are specific to functionality of the system.
[004] The Single board computeré (SEC) (1) are encountered with many
challenges right from initial board testing to integration in an electronic
communication system. During initial testing, the functionality of each
device has to be checked for availability of power supply, clock and reset.
ConventionalIy. monitoring of power, clock and reset are done on resistors
and by means of capacitors present in the power supply path of the device
which is difficult considering size of the components. This type of
monitoring has to be done to all the devices thai are prone to failures after
Single board computers ($80) (1) is powered up.
[005] At the time of deployment of application software into newly
designed Single board computers ($80) (1), there is no means for safe
uploading of software or to verify the software loaded into the system.
Conventionally, the Single board computer(SBC)(1)is loaded with the
earlier stable build software and the functionality is verified, if the device is
working with the stable build and not working with the new build then it is
the concluded as software problem. If the device is not working with stable
build as well as new build, then it is concluded as problem is with device.
This is the iterative cycle undertaken that is more time consuming and also
utilizes the programming limitation of devices.
[006] Further, the power supply and the clock which are independent and
supplied from instruments during the board bring up and application
development are supplied from power supply module and clock reference
module in integration. If the modules are not working as per specification,
then Single board computers (SBC)(1)may not function properly. It is
difficult to find out the reason behind failure of Single board computers
(SBC)(1) inside the chassis.
[007] AIso, there will be a need to retrieve checksum and version of the
software loaded inside processing devices present on Single board
computers (SBC)(1). The process of verifying the checksum is a time
consuming process. It involves reading the checksum from individual
processing devices or programming the processing devices.
[008] Hence there is a need for a display mechanism that has built in
features to retrieve the required status information, temperature and
checksum of software loaded in the Single Board Computer (880) (1).
3.1 Prior Art: -
US Patent: Apparatus System and Method for a Reconfigurable Base
Board Management Controller
Application no: 12/001, 065, Dec 6, 2007
The BMC (Baseboard management controller) described in the prior art is
capable of monitoring the power supply. temperature. The present
invention reads the status of the device, device temperature, clock
manager and version of the software loaded in single board computer. The
coIlected data is displayed in Graphical User Interface (GUI) on personal
computer through Ethernet. The above mentioned features are not present
in prior art. By using the prior art, it is difficult for a person skilled in art to
arrive all the problems associated with background on invention
4. Summary oflnvention
[009] The status displéy scheme is implemented in Single board
comp-uters (SBC) (1) with hardware connections to Field Programmable
Gate Array (2), firmware implementation in Field Programmable Gate Array
and software Graphical User Interface (GU|)(3)implementation in Personal
Computer.
[010] Field Programmable Gate Array (2) configures the device on power
‘ON’ and reads the status of device. The status of the devices is stored in
registers (10-13). Field Programmable Gate Array (2) feads the device
status periodically and updates the value in respective registers (10—13).
[011] The registers (10-13) are read periodically by Ethernet firmware
(19). The Ethernet ‘firmware (19) in Field Programmable Gate Array (2)
converts the register (10-13) contents into UDP packets and sends the
packets to PC through 100 Mbps Ethernet link (18).
[012] The Graphical User Interface (GUI) (3) implemented in visual basic
reads the packets and extracts the information and displays them in
-Graphical User |interface(GU|) (3).
5. Brief description of the drawings
Figure 1 Hardware Interconnection details. block diagram
Figure 2 Firmware Interconnection details block diagram
Figure 3 software Graphical User Interface (GUI) representation
6. Detailed Description of Invention
[013] The status display scheme displays various parameters of Single
board computer(SBC) (1). The single board computer (SEC) (1) in an
electronic communication system consists of various types of devices such
as the processing devices, application specific IC and networking IC.
[014] Processing devices include processor, digital signal processor and
Field Programmable Gate Array (2). The application specific ICs include
High Speed Digital to Analog converter (5), High Speed Analog to Digital
converter (4), Low speed Analog to Digital converter, Low speed digital to
analog converter. LMK clock manager (6).
[015] Networking devices include Ethernet PHY (8) device for sending
the data to outside World and collecting data from outside world. The
status display scheme gathers the device status information from all the
devices connected to the Field Programmable Gate Array (2). The ASIC
device status such as High Speed Analog to Digital Converter (4), High
Speed Digital to Analog Converter (5), LMK clock manager (6) status are
read through Field Programmable Gate Array (2).
[016] While developing the application it is very much important to ensure
the device is working, if the device is not working and there is no clue, it will
be very difficult to analyze whether the problem is due to the application
software or due to the failure of underlying device. The status information
from the devices is helpful in this context.
[017] The single board computer (380) (1) used in the software defined radio is a densely populated board, due to the continuous usage the device
temperature increases. As the device temperature increases it may lead to
failure of devices. The transmit path devices temperature are_ prone to
increase quickly when compared to receive components, the high speed
digital to analog converter (5) temperature is monitored under this scheme.
The temperature monitoring of other devices is also possible. based on the
requirement temperature monitoring for other devices can be added or can
be removed.
'
[018] In the development environment. most of the times doubt arises
regarding the version of the software being used in the single board
computer (SBC) (1). To come out of this problem there are two ways; one
is to read back the checksum of the files present in single board computer
'
(SBC) (1). The other'way is to display the checksum or date and time of
the file loaded. The display status scheme shows the date and time (21) of
the files loaded in single board computer (SBC) (1). In this way the display
status scheme assists in maintaining the version management of the
software in single board computer (SBC) (1).
[019] As shown in figure 1, The devices are connected to Field
Programmable Gate Array (2) through Serial Peripheral Interface (SPI) (15)
and PLB (16) address & data bus. The Field Programmable Gate Array (2)
reads the High Speed Digital to Analog Converter (HSDAC)(5) temperature
through register present in High Speed Digital to Ahalog
Converter(HSDAC) (2). This register updates the temperature of High
Speed Digital to Analog Converter (HSDAC) (5) Field Programmable Gate
Array (2) periodically reads the register through SP! (15) protocol and
updates the register present in the Field Programmable Gate Array (2).
This register stores the temperature (22) of the High Speed Digital to
Analog Converter (HSDAC) (5). One more register stores the High Speed
Digital to Analog Converter(HSDAC) (5) status after reading interface ok
register in High Speed Digital to Analog Converter (HSDAC) (5).
[020] Field Programmable Gate Array(2) reads the High Speed Analog to
Digital to Converter (HSADC) (4) status registers through Serial Peripheral
|interface(SPl) (15) protocol and declares High Speed Analog to Digital to
Converter (HSADC) (4) is functional.
[021] The Field Programmable Gate Array (2) firmware can be divided
into two parts, 1) device status collection in registers (10-13) and 2)
converting device status registers data into packets and sending them
across Ethernet (18).
[022] The device status registers (10-13) are periodically updated by the
Field Programmable Gate Array firmware. The updated registers are
periodically copied into First in First out Memory (FIFO) (14). The First in
First Out Memory (FIFO)(14) sends them to Ethernet firmware (17). The
Ethernet firmware (17) converts received data from First in First Cut
Memory (FIFO)(14) into packets and sends them to Graphical User
Interface (GUI) (3) through 100Mbps Ethernet link (18). If the clock is
present and the clock manager (6) is functional then Mixed Mode Clock
Manager present in the Field Programmable Gate Array (2) issues a lock
status. The lock status 1 indicates the presence of the clock and LMK clock
manager IC (6) is functional.
[023] The Graphical User Interface (GUI) (3) is connected to the single
board computer 880 (1) through Ethernet link (18). The Single Board
Computer SEC (1) data is displayed on GUI only after pressing Attach (24)
button. Provision has been provided on GUI (3) for powering up the FAN in
communication system through FAN ON button (23). All the devices (19)
which are declared ‘OK’ are shown in green color and the device (19)
interface which are ‘NOT OK’ are shown in red color in Graphical User
5 Interface (GUI) (3) running in Personal Computer.
7. Claims
Title: Status display scheme for 'Single Board Computer (SBC) in an
airborne communication system
'
‘
We claim,
1)A Status display scrlene for Single Board Computer(SBC) (1) in an
airborne communication system comprising of:
a Field Programmable Gate Array(FPGA) (2) to collect :status from
onboard device and transfer to GU|(3),
-- a High Speed Analog to Digital Converter(HSADC) (4) to provide status
information of the board,
-- a High Speed Digital to Analog Converter(HSDAC) (5) to provide status
and temperature (22) information of the board,
-- a LMK Clock Manager IC (6) to provide status information of Clock,
-- an Ethernet IC (8) with data rate of 100Mbpsto transfer data to GUI(3)
2) The firmware of Field Programmable Gate Array (FPGA) (2) as per
claim 1 characterized by means of two interfaces namely, a Serial
Peripheral interface(SP|) (15) interface that collects status & temperature
information from the said High speed Digital to Analog Converter (HSDAC)
(5). also collects status information from the High speed Analog to Digital
Converter (4) énd the LM-K Clock manager (6) énd a Processor Local Bus
(PLB) interface (16) from processor that collects the bit stream information‘
(20) and compilation time (21).
3) The information collected by the said Field Programmable Gate Array
(FPGA) (2) as per claim 2 are stored in the respective registers (10-
13)with periodicity of every 1 second in a FIFO (14) and the data coming
out of the said First in First out memory(F|FO)(14) is converted to Ethernet
packets (9) through the said Field Programmable Gate Array (FPGA) (2)
firmware that is further sent to the 100Mbps Ethernet |C(8) through
Ethernet enginé Which is received by a Graphical User |nterface(GU|) (3)
in the Personal Computer wherein decoding of the information is
undertaken for displaying on the Graphical User Interface (3).