Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to seamless emulation of the Electrically Erasable Programmable Read-Only Memory (EEPROM), and more specifically, relates to a system and method for emulating EEPROM to port on any microcontroller.

BACKGROUND
[0002] An example of such a system is recited in a patent US 2005/0055496A1 that provides an efficient emulation of EEPROM employing flash memory which employs a fixed location for an address pointer in flash memory and such that an erase operation is required only once every nth update where n is the number of bits at the fixed location, thus avoiding the need to erase the Sector on every update and avoiding delays associated with linked lists for determining the address of the most up-to-date information. Another example is recited in a US 2010/0250875 A1 in which a device is provided wherein a traditional EEPROM device is emulated by using two or more pages of block-erasable memory and mapping each traditional EEPROM write instruction to an incremented active data sector in a first page of the block-erasable memory while a second page of the block-erasable memory is being partially or fully erased. Then, when the first page of block-erasable memory has had its plurality of data sectors written, changing the active page to the second block-erasable memory and mapping traditional EEPROM writes to incremented data sectors therein while the previously written block-erasable memory is being partially or fully erased. The above-mentioned patents do not provide a solution to configure the size of EEPROM and Flash memory required for emulation based on the target requirements, configure the EEPROM type based on the frequency of use, portability to various hardware platforms, flash memory error correction, flash memory integrity check and the likes.
[0003] During migration from 8-bit microcontrollers to 32-bit microcontrollers, one of the biggest obstacles is the lack of real EEPROM memory in a majority of 32-bit microcontrollers. The only available location for storing the non-volatile variable data is the block-erasable flash memory. The disadvantage of the flash memory is that it cannot be erased or written in single bytes, as is typically done for EEPROM memory as flash memory can only be erased and written in large blocks. A typical erase block size may be 256 to 8192 bytes, and a typical write block is 8 to 512 bytes. Some flash implementations support partial writes, a mode where an erased block may be written multiple times as long as bits only change from “1” (erased state) to “0” (programmed state).
[0004] Some of the flash memories support partial writes, however, they come with further limitations. In some cases, there is a limit on the number of partial writes that may be performed before an erase is necessary. In other cases, writes must happen in some specific alignment and size combinations.
[0005] In some of the microcontrollers, the flash memory allocated for the data storage is often located in the same flash array as the application code. This leads to the need to pause the application execution while data is written. On the other hand, MCU manufacturers recognize this problem, and in many modern MCUs, there is a separate data flash section available for this use. In some cases, the main flash array is split into multiple independent banks, which can be written while other banks are available for reading and code execution.
[0006] Several software emulation solutions exist to address this issue. However, while providing a seamless emulation of the EEPROM interface, they all have significant drawbacks like excessive wear on the underlying flash memory and may result in complete data loss in case of power interruption while the write is on-going.
[0007] Therefore, it is desired to overcome the drawbacks, shortcomings, and limitations associated with existing solutions, and develop a common software-based EEPROM emulation method thereof to port on any microcontroller. This approach requires minor changes to the application flow such as changes required in configuration header file and flash memory interface, but yields a robust EEPROM emulation with minimal wear of the microcontroller flash memory. This approach also provides recovery of corrupted EEPROM data due to power failure during EEPROM write operation by using redundant copies of EEPROM data.
[0008] In opposite to classical EEPROMs, where the data is stored on a fixed address and can always be found in the same location, EEPROM emulation needs to store data on changing locations. Indeed, the physical behaviour of a flash cell does not allow for programming different values to the same cell without erasing before rewriting a value. Furthermore, write and erase granularity differs.

OBJECTS OF THE PRESENT DISCLOSURE
[0009] An object of the present disclosure relates, to the seamless emulation of the EEPROM, and more specifically, relates to a system and method for emulating EEPROM to port on any microcontroller.
[0010] Another object of the present disclosure is to provide a system that offers seamless EEPROM emulation that is easily ported to any microcontroller, regardless of its architecture or the presence of block-erasable Flash memory, whether internal or external.
[0011] Another object of the present disclosure is to provide a system that requires minimal modifications, limited to the configuration header file and block-erasable Flash memory interface, making it adaptable to various microcontrollers with ease.
[0012] Another object of the present disclosure is to provide a system that allows for compile-time configuration of EEPROM size, providing flexibility to tailor the emulation to the specific requirements of different applications.
[0013] Another object of the present disclosure is to provide a system that supports configurable error correction codes, allowing users to enable or disable inbuilt error correction codes in the flash memory as needed.
[0014] Another object of the present disclosure is to provide a system that can configure the size of block-erasable Flash memory circular buffers based on the endurance of the Flash memory, offering adaptability to different memory specifications.
[0015] Another object of the present disclosure is to provide a system that accommodates both frequently modified EEPROMs and less frequently modified EEPROMs, catering to a wide range of application scenarios.
[0016] Another object of the present disclosure is to provide a system that ensures resistance to data corruption resulting from power supply failures during write operations. In the event of a power failure, the system can recover the latest correct data upon power-on.
[0017] Another object of the present disclosure is to provide a system that provides a versatile library that can be utilized in any microcontroller-based bare metal embedded system lacking EEPROM but equipped with only block-erasable Flash memory.
[0018] Yet another object of the present disclosure is to provide a system with a small code footprint of less than 2.5KB, the system minimizes the impact on memory resources, allowing for efficient utilization in resource-constrained environments

SUMMARY
[0019] The present disclosure relates to a seamless emulation of the EEPROM, and more specifically, relates to a system and method for emulating EEPROM to port on any microcontroller. The main objective of the present disclosure is to overcome the drawbacks, limitations, and shortcomings of the existing system and solution, by providing a system and method for emulating EEPROM to port on any microcontroller. The system includes EEPROM emulation using both block-erasable flash memory and RAM to emulate EEPROM.
[0020] The present disclosure can be used in any microcontroller-based bare metal embedded system which is having block-erasable flash memory either internal to the microcontroller or external to the microcontroller. This system uses one buffer in RAM and two circular buffers in block-erasable Flash memory. Whenever EEPROM data is updated, the RAM buffer is updated first then data is copied to both circular buffers one after the other. Two block-erasable flash memory circular buffers are required to recover the correct data on power-on, one circular buffer may always have the correct data in case of power supply failure during write operation. The method performs the integrity of block-erasable flash memory circular buffers on power-on, if the integrity is not OK, recover the latest correct data and update the RAM buffer with data.
[0021] The present disclosure relates to a system for emulating EEPROM, the system includes at least two different memories comprising a flash memory accommodated internal or external to a microcontroller and a RAM accommodated internal to the microcontroller to implement EEPROM emulation. A processing unit is operatively coupled to the microcontroller, the processing unit is configured to initially update a single buffer in the RAM, upon updating EEPROM data, followed by sequential copying of data to at least two circular buffers in the flash memory. Ensure data integrity during power-on recovery, with at least one circular buffer of the flash memory consistently retaining correct data to mitigate potential inconsistencies resulting from power supply failures during write operations. Verify the data integrity of the at least two circular buffers in the flash memory upon each activation of the system. Recover latest correct data from the at least two circular buffers of the flash memory, in an event of compromised data integrity of the at least two circular buffers in the flash memory on each activation and update the single buffer in the RAM with the latest correct data on each activation.
[0022] To provide seamless EEPROM emulation the software shall verify the integrity of Flash memory circular buffers on power-on, on failure of integrity of the flash memory circular buffers on power-on, the software shall recover the latest correct data from one of the circular buffer. After recovering the latest correct data from one of the circular buffer RAM buffer data shall be updated. The present disclosure can be ported on any microcontroller with minimal changes such as change in configuration header file, Flash memory interface. The solution supports two types of EEPROMs such as frequently modified EEPROMs and less frequently modified EEPROMs. In case of power supply failure during the write operation latest correct data can be recovered on power-on. It shall also provide configurable Error Correction Code, in case if flash memory has inbuilt Error Correction Code it can be disabled.
[0023] The present disclosure provides a library which can be used in any microcontroller based bare metal embedded system which does not have EEPROM and have only Flash memory with a small code footprint (less than 2.5 KB).
[0024] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0026] FIG. 1 illustrates an exemplary block diagram of the proposed system, in accordance with an embodiment of the present disclosure.
[0027] FIG. 2 illustrates an exemplary block diagram of the proposed system for emulating EEPROM in block-erasable flash memory in any microcontroller, in accordance with an embodiment of the present disclosure.
[0028] FIG. 3 illustrates an exemplary flow diagram of the proposed system to emulate EEPROM, in accordance with an embodiment of the present disclosure.
[0029] FIG. 4 illustrates an exemplary flow diagram of the method for emulating EEPROM with the help of the RAM buffer and its updating on power-on, in accordance with an embodiment of the present disclosure.
[0030] FIG. 5 illustrates an exemplary flow diagram of a method for emulating EEPROM to write data into EEPROM, in accordance with an embodiment of the present disclosure.
[0031] FIG. 6 illustrates an exemplary flow diagram of a method for emulating EEPROM to read data from EEPROM, in accordance with an embodiment of the present disclosure.
[0032] FIG. 7 illustrates an exemplary flow diagram of a method for emulating EEPROM to erase data of EEPROM, in accordance with an embodiment of the present disclosure.
[0033] FIG. 8 illustrates an exemplary block diagram of inbuilt block-erasable flash memory, in accordance with an embodiment of the present disclosure.
[0034] FIG. 9 illustrates an exemplary block diagram of proposed method for emulating EEPROM, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0035] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0036] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0037] The present disclosure relates, in general, to seamless emulation of the EEPROM, and more specifically, relates to a system and method for emulating EEPROM to port on any microcontroller. The system and method for emulating EEPROM to port on any microcontroller. The system includes EEPROM emulation using both block-erasable flash memory and RAM to emulate EEPROM. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.
[0038] The advantages achieved by the system of the present disclosure can be clear from the embodiments provided herein. The system poised to transform EEPROM emulation. This system provides universal adaptability, seamlessly integrating with any microcontroller regardless of architecture or the presence of block-erasable flash memory, be it internal or external. The system lies in its effortless implementation, requiring minimal modifications limited to the configuration header file and block-erasable Flash memory interface. This simplicity extends to its compile-time configurability, enabling users to tailor the EEPROM size to specific application requirements with unparalleled ease. Moreover, the system supports configurable error correction codes, providing users the flexibility to enable or disable the inbuilt error correction code in the flash memory as needed. Offering dynamic configuration of block-erasable Flash memory circular buffer sizes based on Flash memory endurance, the system optimizes memory resources, enhancing overall efficiency. Accommodating both frequently and less frequently modified EEPROMs, it caters to a diverse range of application scenarios. With robust data integrity mechanisms, the system ensures resistance to corruption resulting from power supply failures during write operations, and in the event of a power failure, it can recover the latest correct data upon power-on. Additionally, the system provides a versatile library tailored for microcontroller-based bare-metal embedded systems lacking EEPROM but equipped solely with block-erasable Flash memory. With a small code footprint of less than 2.5KB, the system's efficiency in memory resource utilization makes it an ideal choice for resource-constrained environments, ensuring optimal performance without compromising functionality. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0039] FIG. 1 illustrates an exemplary block diagram of the proposed system, in accordance with an embodiment of the present disclosure.
[0040] Referring to FIG. 1, bare metal embedded system 100 (also referred to as system 100, herein) for emulating EEPROM in a block-erasable flash memory is disclosed. The system 100 can include a microcontroller 102 with any microcontroller architecture. The system 100 can include a flash memory 104 and RAM 106 internal to the microcontroller.
[0041] The present disclosure pertains to the common method of EEPROM emulation for any bare metal embedded system 100 having any microcontroller 102 with any architecture. The system includes the use of both block-erasable flash memory 104 and RAM 106 to emulate EEPROM. This implementation uses one buffer in RAM 106 and two circular buffers in block-erasable Flash memory 104. Whenever EEPROM data is updated, the RAM buffer is updated first then data copied to both circular buffers one after the other sequentially. Two block-erasable flash memory circular buffers are required to recover the correct data on power-on because one circular buffer may always have the correct data in case of power supply failure during write operation. Initialize all the required variables for EEPROM emulation on power-on in any of the bare metal embedded system that have the microcontroller.
[0042] A processing unit (not shown) is operatively coupled to the microcontroller 102, the processing unit configured to initially update a single buffer in the RAM 106, upon updating EEPROM data, followed by sequential copying of data to at least two circular buffers in the flash memory 104.
[0043] The processing unit is configured to ensure data integrity during power-on recovery, with at least one circular buffer of the flash memory consistently retaining correct data to mitigate potential inconsistencies resulting from power supply failures during write operations. The processing unit is configured to verify the data integrity of at least two circular buffers in the flash memory upon each activation of the system. The processing unit is configured to recover the latest correct data from at least two circular buffers of the flash memory, in the event of compromised data integrity of the at least two circular buffers in flash memory on each activation and the processing unit is configured to update the single buffer in the RAM with the latest correct data on each activation.
[0044] In another embodiment, the system 100 includes a single buffer in RAM 106 and at least two circular buffers in flash memory 104 to perform EEPROM emulation. The flash memory 104 is a block erasable flash memory. The processing unit dynamically configures the EEPROM size during compile time, adapting based on system requirements.
[0045] The processing unit facilitates a configurable Error Correction Code (ECC), providing an option to enable or disable an inbuilt Error Correction Code. In another embodiment, when updating data in the RAM buffer, the system first reads the EEPROM memory sector. If the read memory sector is not okay (indicating an issue with the Error Correction Code), the system sets all indices to invalid. If the read status is okay, it checks the index of the page number. If the page number is 0, it sets the last index of the first sector page to a completed flag and copies the data to the RAM buffer. If the page number is not zero, it copies the data of the last sector to the RAM buffer and sets the page number index, sector number index, and EEPROM status to okay.
[0046] The size of at least two circular buffers within the block-erasable flash memory is configurable, allowing adjustment based on the flash memory endurance requirements of the system.
[0047] In an embodiment, the processing unit supports two types of EEPROMs, that pertain to a frequently modified EEPROM and a less frequently modified EEPROM. The system includes a library utilizing any microcontroller that lacks EEPROM and relies on block-erasable flash memory. Further, the system implements a small amount of code footprint to be less than 2.5KB.
[0048] In an embodiment, the processing unit configured to perform an integrity check of EEPROM block on power-on, initially checks whether the sectors in each block of the corresponding EEPROM are empty or valid, if it is found to be invalid, then an erase operation is performed on the sector.
[0049] In another embodiment, the processing unit checks the validity of the sector numbers in each block of the EEPROM. If the first block sector number is invalid, and the first block sector is not empty, then the erase operation is performed on the first block sector succeeded by the read operation from the second block sector. Eventually, the data read from the second block sector is written to the Flash Memory Block 1 sector. If the second block sector number is invalid, and the second block sector is not empty then the erase operation is performed on the second block sector succeeded by the read operation from first block sector. Eventually, the data read from first block is written to Flash Memory Block 2 sector. If both first block and second block sectors are matching, read data from both block sectors, and then compare and copy data from the first block sector to second block sector. If first block and second block sector numbers are not match, and found to be invalid sector number, erase the EEPROM Block else if found valid sector number erase second block sector and copy data from the first block sector.
[0050] In another embodiment, to write data into EEPROM, get data from RAM buffer and set data to respective field index in RAM buffer along with the data. Check if the current page number index is less than the defined page length for a given sector, starting from index 0. If a page number is found to be in range, then calculate the Error Correction Code for the data in the RAM buffer. Write the data in the current flash memory sector based on the address, page index and sector index values. The data is written to first block sector page first and then to second block sector page. If page number is found to be out of range for a given sector, then page number index is set to 0 and get the data from RAM buffer and calculate Error Correction Code for the data and then computes the address and writes the data in the next sector using the formula (n+1) mod N, where n is current sector index and N is Number of sectors in a block. Before writing to the next sector, the Erase operation is done for both the current sector index and for next sector index of the first block to make sure that only one sector in a block holds the updated data. Then the same operation is continued for the second block sector. In an embodiment, to read the data from the RAM buffer and set to the local buffer field if the EEPROM status is valid or the address of the EEPROM is as per the specified range.
[0051] In an embodiment, the system reads data from the RAM buffer and sets it to the local buffer field if the EEPROM status is valid and if the address of the EEPROM falls within the specified range. In an embodiment, the system erases the flash memory on a sector-wise basis, taking into account the specified address and sector number to be erased. It computes the memory sector, checks the status of the memory to see if it is empty. If the memory is empty, the erase operation is aborted; otherwise, the flash memory is erased.
[0052] Thus, the present invention overcomes the drawbacks, shortcomings, and limitations associated with existing solutions, and provides a system poised to transform EEPROM emulation. This system provides universal adaptability, seamlessly integrating with any microcontroller regardless of architecture or the presence of block-erasable flash memory, be it internal or external. The system lies in its effortless implementation, requiring minimal modifications limited to the configuration header file and block-erasable Flash memory interface. This simplicity extends to its compile-time configurability, enabling users to tailor the EEPROM size to specific application requirements with unparalleled ease. Moreover, the system supports configurable error correction codes, providing users the flexibility to enable or disable the inbuilt error correction code in the flash memory as needed. Offering dynamic configuration of block-erasable Flash memory circular buffer sizes based on Flash memory endurance, the system optimizes memory resources, enhancing overall efficiency. Accommodating both frequently and less frequently modified EEPROMs, it caters to a diverse range of application scenarios. With robust data integrity mechanisms, the system ensures resistance to corruption resulting from power supply failures during write operations, and in the event of a power failure, it can recover the latest correct data upon power-on. Additionally, the system provides a versatile library tailored for microcontroller-based bare-metal embedded systems lacking EEPROM but equipped solely with block-erasable Flash memory. With a small code footprint of less than 2.5KB, the system's efficiency in memory resource utilization makes it an ideal choice for resource-constrained environments, ensuring optimal performance without compromising functionality.
[0053] FIG. 2 illustrates an exemplary block diagram of the proposed system for emulating EEPROM in a block-erasable flash memory in any microcontroller, in accordance with an embodiment of the present disclosure.
[0054] The system is configured for emulating EEPROM in a block-erasable flash memory in any microcontroller-based bare metal embedded system which has block-erasable flash memory either internal to the microcontroller or external to the microcontroller. The system can include a flash memory external to the microcontroller and a RAM internal to the microcontroller. The flash memory external is coupled to the microcontroller through communication interfaces such as SPI/I2C/QSPI.
[0055] The microcontroller 102 is a compact integrated circuit that contains a processor core, RAM 106 and various peripherals. It serves as the central processing unit for the system. RAM 106 is internal to the microcontroller, indicating that it is integrated within the microcontroller chip. RAM is a volatile memory used for the temporary storage of data and program code during the operation of the system. It loses its contents when the power is turned. The flash memory 104 is a non-volatile storage component. Flash memory 104 is often used for storing program code and data that should be retained even when the power is turned off.
[0056] The communication interface 108 connects the microcontroller with external devices, such as the flash memory. The communication interface is selected from the serial peripheral interface (SPI)/ Inter-Integrated Circuit (I2C)/ Quad Serial Peripheral Interface (QSPI).
[0057] The serial peripheral interface is a synchronous serial communication protocol that allows full-duplex communication between the microcontroller and other peripherals. The I2C is a multi-master, multi-slave communication protocol used for connecting various peripherals to the microcontroller. QSPI is similar to SPI but with a faster data transfer rate, often used for high-performance applications.
[0058] FIG. 3 illustrates an exemplary flow diagram of the proposed system to emulate EEPROM, in accordance with an embodiment of the present disclosure.
[0059] In a method for initializing and performing integrity checks for EEPROM emulation on power-on, as illustrated in FIG. 3. At block 302, the required variables, including the number of pages, sectors, blocks, and RAM buffer address range, are initialized. At block 304, an integrity check of the EEPROM block is performed on every power-on. Block 306 involves checking the validity of the EEPROM sector. If the sector is valid, a comparison and copying process of the valid block-erasable Flash memory sector is initiated. If the sector is invalid, the sector of a block is erased before proceeding with the comparison and copying of a valid block-erasable Flash memory sector.
[0060] At block 308, in the case of an invalid sector in block N, a check is made to determine if block N is empty. If block N is empty at block 310, valid Flash memory sector data is copied from the source block to the destination block. If block N is not empty, the sector of block N is erased.
[0061] In block 312, the method checks if the destination block N is empty. If it is not empty, the sector of the destination block N is erased. If it is empty, data is read from the source and written from the source to the destination.
[0062] Returning to block 308, if the EEPROM sector of block N is valid, the method checks if the same number of sectors is available in block N. At block 314, if the same number of sectors is available, a comparison and update of valid Flash Memory Sectors are performed. Data is read from Block 1 and Block 2 sectors, indices are compared, and if valid and identical, data is copied from Block 1 to Block 2. If the same number of sectors is not available, a comparison and update of different valid flash memory sectors are executed.
[0063] In block 316, if it is a valid sector, the sector of block 2 is erased, and valid Flash memory sector data from block 1 is copied to block 2. If it is not a valid sector, the complete block is erased.
[0064] FIG. 4 illustrates an exemplary flow diagram of the method for emulating EEPROM with the help of the RAM buffer and its updation on power-on, in accordance with an embodiment of the present disclosure. In a method for emulating EEPROM with the assistance of a RAM buffer and its update on power-on, as depicted in FIG. 4.
[0065] At block 402, if the EEPROM memory sector read is deemed acceptable ('OK'), the method proceeds to determine if the EEPROM page number index is 0. If, at block 404, the EEPROM page number index is 0, the method advances to at block 406, where the last index of the first sector page is set to a completed flag, and data is copied to the RAM buffer.
[0066] In the event that the EEPROM page number index is not 0, as indicated at block 408, data from the last sector is copied to the RAM buffer. The page index, sector number index, and EEPROM status are then set to the current indices and 'OK', respectively.
[0067] Conversely, at block 402, the EEPROM memory sector read is not deemed acceptable ('not OK'), the method proceeds to block 410, where the index of the page and sector is set to invalid.
[0068] FIG. 5 illustrates an exemplary flow diagram of a method for emulating EEPROM to write data into EEPROM, in accordance with an embodiment of the present disclosure.
[0069] The method for emulating EEPROM to write data, the following steps are outlined. At block 502, data is read from EEPROM. Block 504 involves setting the data to the respective field index in the RAM buffer. At block 506, if the EEPROM page number is less than the range defined for a sector, the method proceeds to Step 508, where the Hamming code for the data in the RAM buffer is calculated.
[0070] Following this, at block 510, the method computes the address to write data to EEPROM, and at block 512, data is written to the first Block sector page and to the second block sector page.
[0071] If the EEPROM page number is not less than the defined range at block 514, the page number index is set to 0. Subsequently, at block 516, data is read from EEPROM using RAM buffer followed by calculation of Hamming code. At block 518, the write operation is done in the next sector address using the formula (n+1) % N. At block 520, EEPROM on first block current and next sector indices are erased, and finally, at block 522, the address is computed, and data is written to the first block sector page and to the second Block sector page.
[0072] FIG. 6 illustrates an exemplary flow diagram of a method for emulating EEPROM to read data from EEPROM, in accordance with an embodiment of the present disclosure. In an exemplary method for emulating EEPROM to retrieve data, as illustrated in FIG. 6. At block 602 involves reading the length of the EEPROM page.
[0073] In block 604, the method determines the validity of the EEPROM status or EEPROM address range. If determined to be acceptable ('ok'), the method proceeds to read data from EEPROM and sets it to the RAM buffer. If the validity check is unsuccessful or the address range is not within acceptable parameters, the RAM buffer is set to empty values.
[0074] Read the length of the EEPROM page and check if the validity of the EEPROM status or EEPROM address range is ok, if ok read data from EEPROM and set to RAM buffer, else set the RAM buffer to empty values.
[0075] FIG. 7 illustrates an exemplary flow diagram of a method for emulating EEPROM to erase data of EEPROM, in accordance with an embodiment of the present disclosure.
[0076] A method for emulating EEPROM to erase data of EEPROM, at block 702 involves computing the address of the memory sector to be erased. Following this, at block 704 entails reading the status of the targeted memory sector. At block 706, if the memory sector is determined to be empty, the erase operation is aborted; otherwise, the Flash memory is subjected to the erase operation.
[0077] FIG. 8 illustrates an exemplary block diagram of inbuilt block-erasable flash memory, in accordance with an embodiment of the present disclosure.
[0078] In the microcontroller 102, the inherent block-erasable flash memory 104 is segmented into distinct partitions, namely used flash 802-1 and unused flash 802-2. The used flash 802-1 is exclusively designated for program execution, data execution and also dedicated block is allocated for EEPROM emulation 804. This EEPROM block 804 is further partitioned into two segments, first EEPROM 806-1 and second EEPROM 806-2, each designed to store redundant copies of identical data. Moreover, each EEPROM segment (806-1, 806-2) is divided into two blocks (808-1 to 808-4), with each block further subdivided into sectors (810-1 to 810-N) and pages (812-1 to 812-N).
[0079] In the scenario where the block-erasable flash memory is external to the microcontroller, the EEPROM block maintains the same structure, with divisions into first EEPROM 806-1 and second EEPROM 806-2 for duplicate data storage. Similar to the internal configuration, each EEPROM block (806-1, 806-2) is divided into two blocks (808-1 to 808-4), and each block is subsequently partitioned into sectors (810-1 to 810-N) and pages (812-1 to 812-N).
[0080] FIG. 9 illustrates an exemplary block diagram of proposed method for emulating EEPROM, in accordance with an embodiment of the present disclosure.
[0081] Referring to FIG.9, the method includes at block 902, utilizing at least two distinct memories, comprising a flash memory accommodated internally or externally to a microcontroller and a RAM accommodated internally to the microcontroller for EEPROM emulation implementation.
[0082] At block 904, initially updated, by a processing unit, a single buffer in the RAM upon modifying EEPROM data, the processing unit operatively coupled to the microcontroller. At block 906, sequentially copy data to at least two circular buffers in the flash memory after updating the RAM buffer. At block 910, ensuring data integrity during power-on recovery by maintaining at least one circular buffer of the flash memory with correct data to address potential inconsistencies from power supply failures during write operations.
[0083] At block 912, verify the data integrity of at least two circular buffers in the flash memory upon each system activation. At block 914, recovering the latest correct data from the at least two circular buffers of the flash memory in the event of compromised data integrity during each system activation and at block 916 updating the single buffer in the RAM with the latest correct data during each system activation.
[0084] It will be apparent to those skilled in the art that the system 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT INVENTION
[0085] The present invention provides a system that offers seamless EEPROM emulation that is easily ported to any microcontroller, regardless of its architecture or the presence of block-erasable Flash memory, whether internal or external.
[0086] The present invention provides a system that requires minimal modifications, limited to the configuration header file and block-erasable Flash memory interface, making it adaptable to various microcontrollers with ease.
[0087] The present invention provides a system that allows for compile-time configuration of EEPROM size, providing flexibility to tailor the emulation to the specific requirements of different applications.
[0088] The present invention provides a system that supports configurable error correction code, allowing users to enable or disable inbuilt error correction codes in the flash memory as needed.
[0089] The present invention provides a system that can configure the size of block-erasable Flash memory circular buffers based on the endurance of the Flash memory, offering adaptability to different memory specifications.
[0090] The present invention provides a system that accommodates both frequently modified EEPROMs and less frequently modified EEPROMs, catering to a wide range of application scenarios.
[0091] The present invention provides a system that ensures resistance to data corruption resulting from power supply failures during write operations. In the event of a power failure, the system can recover the latest correct data upon power-on.
[0092] The present invention provides a system that provides a versatile library that can be utilized in any microcontroller-based bare metal embedded system lacking EEPROM but equipped with only block-erasable Flash memory.
[0093] The present invention provides a system with a small code footprint of less than 2.5KB, the system minimizes the impact on memory resources, allowing for efficient utilization in resource-constrained environments.
, Claims:1. A system (100) for emulating EEPROM, the system comprising:
at least two different memories comprising a flash memory (104) accommodated internal or external to a microcontroller (102) and a RAM (106) accommodated internal to the microcontroller to implement EEPROM emulation;
a processing unit is operatively coupled to the microcontroller, the processing unit is configured to:
initially update a single buffer in the RAM, upon updating EEPROM data, followed by sequential copying of data to at least two circular buffers in the flash memory;
ensure data integrity during power-on recovery, with at least one circular buffer of the flash memory consistently retaining correct data to mitigate potential inconsistencies resulting from power supply failures during write operations;
verify the data integrity of the at least two circular buffers in the flash memory upon each activation of the system;
recover latest correct data from the at least two circular buffers of the flash memory, in an event of compromised data integrity of the at least two circular buffers in the flash memory on each activation; and
update the single buffer in the RAM with the latest correct data on each activation.
2. The system as claimed in claim 1, wherein the system comprises the single buffer in RAM and the at least two circular buffers in flash memory to perform EEPROM emulation.
3. The system as claimed in claim 1, wherein the flash memory is a block erasable flash memory.
4. The system as claimed in claim 1, wherein the processing unit dynamically configures the EEPROM size during compile time, adapting based on system requirements.
5. The system as claimed in claim 1, wherein the processing unit facilitates configurable Error Correction Code (ECC), providing an option to enable or disable an inbuilt Error Correction Code.
6. The system as claimed in claim 1, wherein size of at least two circular buffers within the block-erasable flash memory is configurable, allowing adjustment based on the flash memory endurance requirements of the system.
7. The system as claimed in claim 1, wherein the processing unit supports two types of EEPROMs, that pertains to a frequently modified EEPROM and a less frequently modified EEPROM.
8. The system as claimed in claim 1, wherein the system comprising a library utilizing any microcontroller that lacks EEPROM and relies on the block-erasable flash memory.
9. The system as claimed in claim 1, wherein the system implements a small amount of code footprint to be less than 2.5KB.
10. A method (900) for emulating EEPROM, the method comprising:
utilizing (902) at least two distinct memories, comprising a flash memory accommodated internally or externally to a microcontroller and a RAM accommodated internally to the microcontroller for EEPROM emulation implementation;
initially (904) updating, by a processing unit, a single buffer in the RAM upon modifying EEPROM data, the processing unit operatively coupled to the microcontroller;
sequentially (906) copy data to at least two circular buffers in the flash memory after updating the RAM buffer;
ensuring (908) data integrity during power-on recovery by maintaining at least one circular buffer of the flash memory with correct data to address potential inconsistencies from power supply failures during write operations;
verifying (910) the data integrity of the at least two circular buffers in the flash memory upon each system activation;
recovering (912) the latest correct data from the at least two circular buffers of the flash memory in the event of compromised data integrity during each system activation; and
updating (914) the single buffer in the RAM with the latest correct data during each system activation.