DESC:FORM-2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)

Title: A METHOD TO SECURE DATA WITH TIME STAMPED TAMPER DETECTION IN A SYSTEM ON CHIP

APPLICANT DETAILS:
(a) NAME: Bharat Electronics Limited
(b) NATIONALITY: Indian
(c) ADDRESS: OUTER RING ROAD, NAGAVARA, BANGALORE 560045,
INDIA

PREAMBLE TO THE DESCRIPTION:
The following specification (particularly) describes the nature of the invention (and the manner in which it is to be performed):

A METHOD TO SECURE DATA WITH TIME STAMPED TAMPER DETECTION IN A SYSTEM ON CHIP

FIELD OF INVENTION:
The present disclosure relates generally to system on chip.

BACKGROUND OF THE INVENTION:
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly
This application references to a prior art of U.S Patent Application No. 1163621B2 dated April 2023 for “System and Method for Tamper proof Interaction recording and Time stamping” which relates to tamper proof Interaction recording and Time stamping and its carried out using network connected computer server and an authentication system. Once the processor detects the tamper signal, the authentication system verifies the validity of voice communication. The existing approach involves the detection system automated process along with time stamping. A prior art of U.S Patent Application No 1156630B2 dated Oct 2021 for "Integrated Tamper Detection Systems and Methods" which relates method of tamper detecting via an observed change of surrounding environment associated with an item , object or device of interest.

OBJECTIVES OF THE INVENTION:
The primary object of the present invention is to overcome the problem stated in the prior art.
Another object of the present invention provides a method and system of detecting the tamper signal, obtaining or freezing time at tampered moment, capturing the same in a flash memory & erasing the critical data in the SRAM.

SUMMARY OF THE INVENTION:
The present invention provides a system to secure data with time stamped tamper detection in a system on chip comprising:
a) a microcontroller 101, where the microcontroller is configured to detect the tamper signal and perform countermeasures;
b) a tamper detection module 102 which is backed up by external battery is configured to detect tamper; and
c) a time capture module 103 is configured to capture the tampered time and same is stored in memory a secure memory storage 104;
wherein a tamper detect circuitry with 32-bit free running counter unit 208 to detect valid tamper signal, where the 32-bit free running counter captures the tampered time and the same is stored in the secure memory storage 104.
In an embodiment, the 32-bit free running counter captures the tampered time and the same is stored in the secure memory.
In an embodiment, the tamper detect module is powered up with externally backed up battery and oscillator.
In an embodiment, the tamper detection module detects a valid tamper signal and disables the writing mechanism to secure memory.
The present invention provides a system to secure data with time stamped tamper detection in a system on chip comprising steps of:
a) authenticating a stamping authority on block inside the SoC, where the block is a part of tamper module block inside the SoC;
b) powering the block all the time with the help of external battery and providing clock input to tamper module continuously by an external oscillator continuously;
c) detecting valid tamper signal and stopping the timer counter where, if system a detects a valid tamper signal the module disables the write and functionality of memory and making the memory permanently write disabled.

DETAILED DESCRIPTION OF DRAWINGS:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:
Fig. 1: illustrates a block diagram of System Architecture.
Fig. 2: illustrates a functional Block diagram.
Fig. 3: illustrates a flow chart.
Fig. 4: illustrates a block diagram.

DETAILED DESCRIPTION:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
The terms “comprises”, “comprising”, “includes”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The present disclosure proposes a system on chip platform for Integrated Chip design, wherein the method has given confidence on functionality of designed module with intended specification, where method applied on design plays an important role in meeting those requirements. A novel implementation is on performing secure way for isolating or storing the data from the detection of the tamper signal. For tamper signal detection in a SoC, design needs to be configured in a proposed manner to avoid unauthorized reading or accessing of the data. There is a need for customization of the circuit before using it for intended purpose. A novel implementation is a method of detecting the tamper signal, capturing the time of tamper detection and storing it in Flash Memory device.
The present invention provides a system to secure data with time stamped tamper detection in a system on chip comprising:
a) a microcontroller 101, where the microcontroller is configured to detect the tamper signal and perform countermeasures;
b) a tamper detection module 102 which is backed up by external battery is configured to detect tamper; and
c) a time capture module 103 is configured to capture the tampered time and same is stored in memory a secure memory storage 104;
wherein a tamper detect circuitry with 32-bit free running counter unit 208 to detect valid tamper signal, where the 32-bit free running counter captures the tampered time and the same is stored in the secure memory storage 104.
In an embodiment, the 32-bit free running counter captures the tampered time and the same is stored in the secure memory.
In an embodiment, the tamper detect module is powered up with externally backed up battery and oscillator.
In an embodiment, the tamper detection module detects a valid tamper signal and disables the writing mechanism to secure memory.
The present invention provides a system to secure data with time stamped tamper detection in a system on chip comprising steps of:
a) authenticating a stamping authority on block inside the SoC, where the block is a part of tamper module block inside the SoC;
b) powering the block all the time with the help of external battery and providing clock input to tamper module continuously by an external oscillator continuously;
c) detecting valid tamper signal and stopping the timer counter where, if system a detects a valid tamper signal the module disables the write and functionality of memory and making the memory permanently write disabled.
Figure.1 is a Block diagram of System Architecture according to a first exemplary embodiment of the present invention includes the microcontroller 101 along with the tamper detection module 102 which is backed up by external battery. The architecture also involves system time capture module 103 and secure memory storage 104.
Figure 2 is a functional Block diagram of standard SoC elements with the microcontroller 201 and the tamper detection module 207. The state of art involves the microcontroller unit 201, reset control module unit, RTC unit 202 , tamper detection module 207 and the interfaces along with the secure memory to operate on controllers normal power mode.
Figure 3 illustrates the Flow chart of proposed invention of tamper detection method.
Figure 4 illustrates the Block diagram of the proposed invention tamper detection circuitry with time stamping feature.
In an embodiment, the present disclosure discusses the state of art for the tamper detection using the time stamping method without the microcontroller intervention.
In Fig.2 the microcontroller core 201 here intervenes with the above said units to detect the tamper signal and perform countermeasures. This describes the controller operation in full power up mode of tamper detection module 207. Where the entire system derives power from intended power supply for operation. The proposed tamper detect module works in conjunction with backup battery for running the entire tamper module in the always on mode even when the controller is not fully operational. State of art involves a tamper detect circuitry with 32 bit free running counter unit 208 to detect valid tamper signal. It also involves a secure memory where the critical data is stored to access and perform normal operation of SoC.
The traditional approach of the tamper circuitry Fig.2 involves the reset control module 204 to generate reset on the processor start up and waits for the valid tamper signal to generate and then the counter from RTC block 202 is captured for time of the tamper signal detection. This also requires the entire microcontroller intervention where the processor/controller block intervenes to transact the information from RTC to secure memory through the internal bus. Further to which counter measures are taken care for data security. This prior art process is power hungry process where core of the SoC and the related modules of the chip are in action at a time where tamper signal is detected based on the authentication system. The unauthorised access is time stamped and is stored in a memory.
The proposed invention discuss the method of detecting the tamper signal without the processor or microcontroller intervention. The state of the art involves a 32bit free running counter as a timer stamp authentication. The said stamping authority is under always on block inside the SoC. This particular block is a part of tamper module block inside the SoC. The entire block is powered up all the time with the help of external battery. An external oscillator is providing the clock input to tamper module continuously. Once the module detects the valid tamper signal, module stops the timer counter and the tampered time is captured. Further to which, if system a detects a valid tamper signal the module disables the write and functionality of memory and making the memory permanently write disabled.
Fig 4 The proposed invention involves the 32 bit free running counter block 404, secure memory block 403 and interfaces. This is also a time stamping authority to capture the tampered time and same is stored in memory. The clock to this circuitry is drawn from the external oscillator. Where there is no intervention of microcontroller for operation of a tamper detection module.
In an embodiment, the proposed disclosure explains the method of always on based circuitry of time stamped tamper detection module. The 32 bit free running counter captures the tampered time and the same is stored in the secure memory.
In a preferred embodiment, the present disclosure proposes: a method of time stamping tamper detection using a 32 bit free running counter without microcontroller intervention.
In an embodiment, the tamper detect module is powered up with externally backed up battery and oscillator.
In an embodiment, the SRAM memory is erased making memory permanently write disabled.
In an embodiment, when executed will detect a valid tamper signal and disable the writing mechanism to secure memory.
In an embodiment, when executed will disable the Flash memory by making the memory permanently write disabled.
Abbreviations:
RTL - Register Transfer Level
SoC - System on Chip
ROM - Read Only Memory
RCM - Reset Control Module
RTC - Real Time Clock
GPIO - General Purpose Input Output
The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:We Claim:

1. A system to secure data with time stamped tamper detection in a system on chip comprising:
a) a microcontroller 101, where the microcontroller is configured to detect the tamper signal and perform countermeasures;
b) a tamper detection module 102 which is backed up by external battery is configured to detect tamper; and
c) a time capture module 103 is configured to capture the tampered time and same is stored in memory a secure memory storage 104;
wherein a tamper detect circuitry with 32-bit free running counter unit 208 to detect valid tamper signal, where the 32-bit free running counter captures the tampered time and the same is stored in the secure memory storage 104.
2. The system to secure data with time stamped tamper detection in a system as claimed in claim 1, wherein the 32-bit free running counter captures the tampered time and the same is stored in the secure memory.
3. The system to secure data with time stamped tamper detection in a system as claimed in claim 1, wherein the tamper detect module is powered up with externally backed up battery and oscillator.
4. The system to secure data with time stamped tamper detection in a system as claimed in claim 1, wherein the tamper detection module detects a valid tamper signal and disables the writing mechanism to secure memory.
5. A system to secure data with time stamped tamper detection in a system on chip comprising steps of:
a) authenticating a stamping authority on block inside the SoC, where the block is a part of tamper module block inside the SoC;
b) powering the block all the time with the help of external battery and providing clock input to tamper module continuously by an external oscillator continuously;
c) detecting valid tamper signal and stopping the timer counter where, if system a detects a valid tamper signal the module disables the write and functionality of memory and making the memory permanently write disabled.