DESC:FORM-2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)

Title: A DIGITAL PHASE SHIFTER

APPLICANT DETAILS:
(a) NAME: BHARAT ELECTRONICS LIMITED
(b) NATIONALITY: Indian
(c) ADDRESS: Outer Ring Road, Nagavara, Bangalore-560045, Karnataka, India

PREAMBLE TO THE DESCRIPTION:
The following specification (particularly) describes the nature of the invention (and the manner in which it is to be performed):

A DIGITAL PHASE SHIFTER

FIELD OF INVENTION:
The present disclosure/invention relates in general to phase shifter and more particularly to a digital phase shifter.

BACKGROUND OF THE INVENTION:
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly
Phase shifters are well known in the art which is a critical component in many RF and Microwave communication systems. Generally, the phase shifter is an electronic device which changes the phase of an incoming signal. Digital phase shifters are also well known in the art which is a critical component in microwave communication system and surveillance systems. The digital phase shifter is used to change the phase value of incoming RF signals. For accurate beam forming in T/R (Transmit/Receive) modules, the digital phase shifter must have high resolution and high accuracy. Generally, digital phase shifters are designed using pHEMT switches that have higher switching speed. Hence, it is important to design a digital phase shifter with low RMS Phase error with good input and output return losses.
GaAs based monolithic microwave integrated circuits are vastly used in communication and surveillance systems because of their high yield and reliable performance. GaAs MMICs achieves small size, less weight and high power at lower cost. AESA (Active Electronically Scanned Array) systems are one such area where digital phase shifter MMICs finds its applications. T/R module is the core component of AESA, in which digital phase shifters are used to change the phase of input signals for beam forming and scanning. This digital phase shifter is specially designed for T/R modules used in surveillance systems.
One of the prior art discloses a phase shifter in which, the transmission lines (TL) arranged in a ring with first pair of the TL arranged in series in a first path and second pair of the TL arranged in series in a second path. One of the transmission lines of the first and second pairs include a quarter wave hybrid coupled line with coupled ports and through ports terminated in short circuit. Hybrid coupled line can be a Lange coupler with or without RF crossover. Phase bits 22, 45, 90 and 180 degrees realized and maximum phase error of 5º observed for 180 º phase bit across the frequency band of 14-21.5 GHz. This is a 4-bit phase shifter in the higher frequency range and based on hybrids, TLs. Hence, this prior art phase shifter size will be large for realizing 6-bit phase shifter at required lower frequency band.
Another prior art discloses a 6 bit digital phase shifter MMIC design in 0.38-0.74 GHz Range with insertion loss of less than 6 dB, return loss around 15dB and phase accuracy < 5º. This prior art designs 180, 90 and 45 degree phase bits using All pass networks (APNs) and HPL/LPF sections. 22.5, 11.25 degrees phase bits realized using T-type and 5.625º phase bit designed with switching capacitors networks. MSB phase bits 180, 90 connected at extremes and 45, 11.25, 22.5, 5.625 bits connected in between 180 and 90 bits. This prior art belongs to low frequency of operation.
Another prior art discloses a field of RFIC digital phase shifters, in particular, it relates to a dual-band miniaturized digital phase shifter with variable coupling co-efficient inductor structure. The centre frequencies of the two working frequency bands of the phase shifter are set to 8.5GHz and 15.5GHz. For the 22.5° Phase shift, the phase shift error is less than ±0.37°, insertion loss is 3dB and both input and output return losses are less than -15dB. This prior art has high insertion loss and large chip area due to RFIC process and more number of inductors.
Further prior art discloses a V band miniaturized digital phase shifting network is designed using CMOS switches and LC networks to pass the signals form 108-174MHz. Seven LC networks used to realize the phase shifts from 5.625 to 360 degrees. Control circuit is a programmable circuit based on CPLD framework. The maximum insertion loss 13 dB, phase shift accuracy 2.5°, Maximum CW RF input power greater than 50W. This prior art is based on CMOS switches related to low frequency, high power applications.
Further prior art discloses a lange coupler used having reflective ports that are coupled to artificial transmission lines (ATL). ATL provides a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on / off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter. This prior art belongs to the true time delay network where phase shift varies linearly which is quite opposite.
Therefore, there is a need in the art with a digital phase shifter with high resolution, reduced size, low insertion loss, low RMS phase error and to solve the above-mentioned limitations.

OBJECTIVES OF THE INVENTION:
The primary object of the present invention is to overcome the problem stated in the prior art.
Another object of the present invention provides a digital phase shifter with high resolution, reduced size, low insertion loss, low RMS phase error and to solve the above-mentioned limitations.

SUMMARY OF THE INVENTION:
The present invention provides a digital phase shifter comprising:
a) at least one input matching network (101), where the input matching network (101) is comprises series metal insulator metal (MIM) capacitor (203) and a transmission line to provide 50 Ohm input impedance;
b) at least six individual phase bits (102,103,104,105,106,107), where each phase bit separately to control the phase shift;
c) plurality of TTL driver circuits (109-114), where the TTL driver circuits (109-114) generate required complementary control voltages to make switch pHEMTs ON / OFF on input TTL control voltages (0, 3/5V); and
d) at least output matching network (108), where the output matching networks (101,108) comprises MIM capacitors (203,204) and a transmission lines to establish match I/O match;
where the MIM capacitors present in the matching networks a configured for DC blocking at RF input, output ports, where a scalable round inductors (217) and a gate resistor (218) mounted at gate terminals of all switch pHEMTs to prevent RF, DC leakages and to maintain enough RF to DC isolation.
In an embodiment, the digital phase shifter MMIC is fabricated using 0.25µm InGaAs pseudomorphic high electron mobility transistor (pHEMT) technology, with high resolution and low RMS phase error.
In an embodiment, the phase bits (104,102,107) comprises 11.2, 22.5 and 45 degrees reconfigurable topology and a LSB phase bit 5.6° (105) are designed using switched capacitor/inductor topology, higher order phase bits 90, 180 degrees (106,103) are designed using SPDT based filter topology.
In an embodiment, the cascading order of six phase bits from RF input to Output are 22.5, 180, 11.2, 5.6, 90 and 45 degrees (102, 103, 104, 105, 106, 107) and each phase bit is integrated with separate TTL driver circuit (109-114).
In an embodiment, the LSB phase bit 5.6° (105) is designed using switched capacitor/inductor topology (205) in which a capacitor and inductor switched using pHEMT switches (214) generate the required phase shift.
In an embodiment, one path pHEMT switch is ON by the external DC control voltage, RF input signal passes through the capacitive phase lag path whereas when second pHEMT switch made ON, signal pass through the inductive phase lead path.
In an embodiment, two higher order phase bits 90, 180 degrees (106,103) were designed using SPDT based switched low pass filter and high pass filter topologies (209,210).
In an embodiment, SPDT switches (216) are used to select the low pass and high pass networks alternatively to generate the required phase shift.
In an embodiment, the TTL driver logic circuits (211) designed and integrated with each phase bit separately to control the phase shift.

DETAILED DESCRIPTION OF DRAWINGS:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:
Fig. 1: illustrates an architecture of C band 6-bit digital phase shifter.
Fig. 2: illustrates a layout of C band 6-bit digital phase shifter.
Fig. 3: illustrates a schematic of conventional (300) embedded FET topology of digital phase shifter.
Fig. 4: illustrates a modified (400) embedded FET topology of C band 6-bit digital phase shifter.

DETAILED DESCRIPTION:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
The terms “comprises”, “comprising”, “includes”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The present invention relates to a C band GaAs (Gallium arsenide) technology based 6-bit digital phase shifter MMIC (Monolithic Microwave Integrated Circuit). The C band GaAs technology based 6-bit digital phase shifter MMIC is a single chip having a die size of at 3.4 mm X 1.46 mm fabricated on 0.1mm substrate using 0.25 µm pHEMT process. The digital phase shifter is a monolithic design with single supply voltage of -5V and works on parallel TTL (Transistor-Transistor Logic) control logic input voltages. The design of the digital phase shifter comprises of at least 6-indiviudal phase bits, an input and output matching networks, which are cascaded together along with integrated TTL driver logic circuits. Internal DC blocking capacitors embedded as part of input and output matching circuits. The digital phase shifter operates in the frequency range of 4.8-6.2 GHz with typical Insertion loss of 5.5 dB and RMS phase error of 2.2°.
Figure 1 shows an architecture of C band 6-bit digital phase shifter according to an exemplary implementation of the present disclosure/ invention.
The figure shows an architecture of C band 6-bit digital phase shifter. The C band 6-bit digital phase shifter comprises at least one input matching network (101), at least six Individual phase bits (102,103,104,105,106,107), plurality of TTL driver circuits (109-114) and at least output matching network (108).
The C band 6-bit digital phase shifter MMIC is fabricated using 0.25µm InGaAs pseudomorphic high electron mobility transistor (pHEMT) technology, with high resolution and low RMS phase error. The C band 6-bit digital phase shifter architecture consists of at least six individual phase bits and matching networks as shown figure 1.
In the present invention, phase bits (104,102,107) 11.2, 22.5 and 45 degrees are designed using embedded FET/Reconfigurable topology, LSB phase bit 5.6° (105) are designed using switched capacitor/inductor topology, higher order phase bits 90, 180 degrees (106,103) are designed using SPDT based filter topology.
In the present inevntion, cascading order of six phase bits from RF input to Output are 22.5, 180, 11.2, 5.6, 90 and 45 degrees (102, 103, 104, 105, 106, 107) and each phase bit is integrated with separate TTL driver circuit (109-114).
Figure 2 shows a layout of C band 6-bit digital phase shifter according to an exemplary implementation of the present disclosure/ invention.
The figure shows the extended view of C band 6-bit digital phase shifter layout which consists of all circuit elements, driver circuits, RF input/ output and DC bond pads.
The C band 6-bit digital phase shifter MMIC (200) is with a die size of 3.4mm X 1.46mm in x and y directions fabricated on 0.1 mm InGaAs substrate with 0.25µm gate length Enhancement/Depletion (E/D) mode process.
The Input matching network (101) is designed using series metal insulator metal (MIM) capacitor (203) and lengthy transmission line to provide 50 Ohm input impedance and this matching circuit blocks the DC at RF input port.
In the present invention, LSB phase bit 5.6° (105) is designed using switched capacitor/inductor topology (205) in which a capacitor and inductor switched using pHEMT switches (214) to generate the required phase shift. When one path pHEMT switch is ON by the external DC control voltage, RF input signal passes through the capacitive phase lag path whereas when second pHEMT switch made ON, signal pass through the inductive phase lead path. The phase difference between two paths gives the required phase shift.
Embedded FET or Reconfigurable topology (206, 207) is chosen to design 11.2, 22.5 degrees phase bits (104,102) phase bits as this topology occupies small chip area and provides flat phase shift response with good matching at narrow band frequencies. This topology provides a through path when series switch is ON and phase shifting low pass path to the RF incoming signals when the series switch is OFF and shunt switch is ON.
A modified Embedded FET topology (208) with extra capacitive network (215) is used to realize the 45 degrees phase bit (107) in order to realize higher phase shift with good input, output match in smaller chip area.
The remaining two higher order phase bits 90, 180 degrees (106,103) were designed using SPDT based switched low pass filter and high pass filter topologies (209,210). The SPDT switches (216) are used to select the low pass and high pass networks alternatively to generate the required phase shift. Filter networks are designed for the phase, which is almost half of the required phase shift thus, the difference between the two paths will generate the required phase shift. SPDT switches placed at input and output terminals of LPF / HPF networks.
Input and output matching networks (101,108) realized using MIM capacitors (203,204) and transmission lines to establish the best match I/O match. The MIM capacitors present in the matching networks also served the purpose of DC blocking at RF input, output ports. Scalable round inductors (217) used in the design. A gate resistor of value approx.10K? (218) is used at gate terminals of all switch pHEMTs in the design to prevent RF, DC leakages and to maintain enough RF to DC isolation.
Digital TTL driver logic circuits (211) designed and integrated with each phase bit separately to control the phase shift. Driver circuits (109-114) generate required complementary control voltages to make switch pHEMTs ON / OFF on input TTL control voltages (0, 3/5V). Resistor (219) used across all DC, RF crossovers points in the design to avoid coupling of RF signals into the control lines. All Drain / Source terminals of pHEMT switches connected to ground potential using high value shunt resistors (220). ESD protection diodes (221) incorporated at control and supply voltage lines.
In the present invention, a 100 µm X 150 µm bond pads (201, 202) provided at RF input and output ports and 100 µm X 100 µm bond pads (212, 213) provided for DC supply and control supply inputs. Ground-Signal-Ground (GSG) pitch of RF input and output ports are 175 µm.
Gate Isolation resistors (219) are distributed along the switch control lines near to RF and Control line crossovers to avoid signal cross talk/ interference.
High value shunt grounded resistors 3k? (220) are used across source or drain terminals of all pHEMT switches to maintain ground potentials for perfect switching post to the fabrication.
The figure 3 shows a schematic of conventional (300) embedded field-effect transistor (FET) topology of digital phase shifter. The conventional (300) embedded FET topology of digital phase shifter comprises though state transistor network in one path and phase shifting state low pass filter network with resonator structure in other path.
The figure 4 shows a modified (400) embedded field-effect transistor (FET)/ reconfigurable topologies is used in the C band 6-bit digital phase shifter. The modified (400) embedded FET/ Reconfigurable topologies of C band 6-bit digital phase shifter comprise though state and phase shifting networks same as figure 3. A capacitive switch network included at input to improve the matching and bandwidth.
The modified embedded FET/reconfigurable topology (400) is used in the C band 6-bit digital phase shifter for achieving the required higher phase of 45° in smaller chip area with good Matching. An additional switch capacitive network used at input.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter is fabricated using 0.25µm E/D mode InGaAs pseudomorphic high electron mobility transistor (pHEMT) technology with a die size of 3.4 mm and 1.46 mm in both x and y directions respectively.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has low Insertion loss of 5.5 dB typical across frequency band and across all 64 phases states in frequency range of 4.8-6.2 GHz.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has broadband operating frequency range of 4.8-6.2 GHz in C band.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has low RMS Phase Error of 2.2° typical and peak phase error of 5° across all 64 phase states of the frequency band.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has high Input power for 1 dB compression (P1 dB) is +27 dBm typical.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has fast switching time of phase shifter around 200nS.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has better Return losses less than -10 dB at both input and output ports over the 4.8-6.2 GHz frequency range.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter requires only Single supply voltage of -5V for operation with current consumption of 14mA typical.
In one embodiment, the C-band 6-bit digital phase shifter has TTL control logic levels (0/3V) used for controlling the Phase bits of the digital phase shifter.
In one embodiment of the present invention, the C-band 6-bit digital phase shifter has High Input 1dB compression point of +27dBm and high Input IP3 of 37dBm typical.
In one embodiment of the present invention, novel Modified Embedded FET topology is used for achieving required higher phase of 45° in smaller chip area.
In one embodiment, gate Isolation resistors distributed along the switch control lines near to RF and Control line crossovers to avoid signal cross talk / interference.
In one embodiment, high value shunt grounded Resistive networks used across Drain or Source terminals of switches pHEMTs to maintain ground potential for proper switching functionality post to the fabrication.
The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:We Claim:

1. A digital phase shifter comprising:
a) at least one input matching network (101), where the input matching network (101) comprises series metal insulator metal (MIM) capacitor (203) and a transmission line to provide 50 Ohm input impedance;
b) at least six individual phase bits (102,103,104,105,106,107), where each phase bit separately to control the phase shift;
c) plurality of TTL driver circuits (109-114), where the TTL driver circuits (109-114) generate required complementary control voltages to make switch pHEMTs ON / OFF on input TTL control voltages (0, 3/5V); and
d) at least output matching network (108), where the output matching networks (101,108) comprises MIM capacitors (203,204) and a transmission lines to establish match I/O match;
where the MIM capacitors present in the matching networks a configured for DC blocking at RF input, output ports, where a scalable round inductors (217) and a gate resistor (218) mounted at gate terminals of all switch pHEMTs to prevent RF, DC leakages and to maintain enough RF to DC isolation.
2. The digital phase shifter as claimed in claim 1, wherein the digital phase shifter MMIC is fabricated using 0.25µm InGaAs pseudomorphic high electron mobility transistor (pHEMT) technology, with high resolution and low RMS phase error.
3. The digital phase shifter as claimed in claim 1, wherein the phase bits (104,102,107) comprises 11.2, 22.5 and 45 degrees reconfigurable topology and a LSB phase bit 5.6° (105) are designed using switched capacitor/inductor topology, higher order phase bits 90, 180 degrees (106,103) are designed using SPDT based filter topology.
4. The digital phase shifter as claimed in claim 1, wherein the cascading order of six phase bits from RF input to Output are 22.5, 180, 11.2, 5.6, 90 and 45 degrees (102, 103, 104, 105, 106, 107) and each phase bit is integrated with separate TTL driver circuit (109-114).
5. The digital phase shifter as claimed in claim 1, wherein the LSB phase bit 5.6° (105) is designed using switched capacitor/inductor topology (205) in which a capacitor and inductor switched using pHEMT switches (214) generate the required phase shift.
6. The digital phase shifter as claimed in claim 1, wherein the one path pHEMT switch is ON by the external DC control voltage, RF input signal passes through the capacitive phase lag path whereas when second pHEMT switch made ON, signal pass through the inductive phase lead path.
7. The digital phase shifter as claimed in claim 1, wherein the two higher order phase bits 90, 180 degrees (106,103) were designed using SPDT based switched low pass filter and high pass filter topologies (209,210).
8. The digital phase shifter as claimed in claim 1, wherein the SPDT switches (216) are used to select the low pass and high pass networks alternatively to generate the required phase shift.
9. The digital phase shifter as claimed in claim 1, wherein the TTL driver logic circuits (211) designed and integrated with each phase bit separately to control the phase shift.