DESC:FORM-2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)

Title: SYSTEM AND METHOD OF HIGH ACCURACY SATELLITE TERMINALS TIMING SYNCHRONIZATION FOR HIGH DATA RATE SATCOM NETWORK

APPLICANT DETAILS:
(a) NAME: BHARAT ELECTRONICS LIMITED
(b) NATIONALITY: INDIAN
(c) ADDRESS: Outer Ring Road, Nagavara, Bangalore-560045, Karnataka, India

PREAMBLE TO THE DESCRIPTION:
The following specification (particularly) describes the nature of the invention (and the manner in which it is to be performed):
SYSTEM AND METHOD OF HIGH ACCURACY SATELLITE TERMINALS TIMING SYNCHRONIZATION FOR HIGH DATA RATE SATCOM NETWORK

FIELD OF INVENTION:
The present disclosure relates to satellite communication. The disclosure, more particularly, relates to system and method of high accuracy satellite terminals timing synchronization for high data rate satcom network.

BACKGROUND OF THE INVENTION:
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
In a TDMA satellite communication system with multiple satellites or ground stations, precise timing synchronization is crucial for coordinating communication schedules. Network management relies on accurate timing information to coordinate the timing of transmissions between different nodes, ensuring efficient use of the satellite resources.
In TDMA systems, the available time is divided into discrete slots, and each user or communication channel is assigned a specific time slot. Accurate timing synchronization ensures that each user starts and stops transmission in their allocated time slot precisely. This helps in avoiding collisions and interference between different users, ensuring efficient use of the available bandwidth.
Synchronization helps in mitigating interference between adjacent satellite beams or neighbouring satellite systems. If the timing is not synchronized, signals from different users or satellite systems may overlap in time, leading to interference and degradation of communication quality.
Synchronization is essential at the receiver end to demodulate and decode signals accurately. The receiver needs to know when to expect the transmitted signals and align its sampling and decoding processes accordingly. Without synchronization, there's a risk of signal distortion and loss of information. Synchronization allows for more efficient utilization of available bandwidth and time slots. When each user adheres to their assigned time slot, there is less idle
time, and the overall system throughput is maximized.
Synchronization is not only about aligning time slots but also ensuring that the carrier frequencies are stable. Frequency synchronization is important to prevent signal drift and maintain the integrity of the transmitted information. Synchronization contributes to achieving and maintaining the desired Quality of Service. It ensures that each user experiences minimal interference, low latency, and reliable communication.
US20120122500 A1 discloses a method and apparatus for synchronizing multiple transmitters is disclosed. A global time reference is used to synchronize the arrival of data from a plurality of secondary transmitters in a receiver station. In one embodiment, the global time reference is provided by a GPS satellite and may also be used to synchronize the carriers of the signals received at the receiver station from each of the plurality of transmitters. In one embodiment, a pilot signal used for ATSC applications is added by the secondary transmitters.
US8879536 B2 discloses An apparatus for time synchronization of a femtocell base station receives, via neighbouring macro cell base stations adjacent to a femtocell base station, timing packets generated by timing servers directly connected to the neighbouring macro cell base stations, and if time synchronization using a GPS satellite is impossible, obtains system time information from a timing packet received via one corresponding to a master base station, among the neighbouring macro cell base stations, and performs time synchronization.
US6674730 B1 discloses time alignment of a signal from a remote unit at a hub station of a multiple access system is achieved based upon an initial time indication received from the hub station at the remote unit via a satellite. The remote unit transmits a signal to the satellite, monitors for a re transmission of the signal from the satellite and measures the time difference between the outgoing and incoming signals. The remote unit, then, uses the time difference to more finely adjust the time alignment. Alternatively, the remote unit transmits a first signal advanced with respect to an on-time estimate to the hub station and receives a responsive energy indication from the hub station. The remote unit transmits a second signal delayed with respect to the on-time estimate to the hub station and receives a responsive energy indication from the hub station. The remote unit compares the two energy indications and adjusts the on-time estimate. In another embodiment, the remote unit receives a compensated time indication from the hub station. The remote unit compares the time indication with the time at which the indication was actually received based upon a local, accurate time reference. The remote unit sets a transmission timer equal to the current time indicated by the local reference advanced by the difference between the time indication and the time which the time indication was received.
Therefore, there is a need for a system and method of high accuracy satellite terminals timing synchronization for high data rate satcom network.

OBJECTIVES OF THE INVENTION:
The primary object of the present invention is to overcome the problem stated in the prior art.
Another object of the present invention is to provide a system and method for high accuracy satellite terminals timing synchronization for high data rate satcom network.

SUMMARY OF THE INVENTION:
In an aspect, present invention provides a system for high accuracy satellite terminals timing synchronization for high data rate satcom network comprising:
a) a frequency drift prediction unit comprises a contingency mechanism which activates the frequency drift prediction unit when an 1PPS signal is absent to facilitate accurate frequency drift prediction in its absence;
b) a temperature compensation unit comprises an on-chip temperature sensor to measure environmental conditions;
c) a processor configured to analyse temperature data from the temperature sensor based on a X-Cut lookup table from datasheet; and
d) an adaptive control unit configured to dynamically adjust the frequency based on temperature variations, ensuring stable performance under varying temperature conditions.
In an embodiment, the adaptive control unit adjusts the frequency by implementing counter logic in conjunction with the 1PPS signal for precise frequency correction, ensuring synchronization and accuracy in timekeeping applications.
In an embodiment, the frequency drift prediction unit has an inbuilt linear regression model which re-utilizes past data for pre-emptive adjustments of the frequency.
In an embodiment, the 1PPS signal is absent the contingency mechanism implements a counter logic to count and store (in register) the number of clocks for 1 second to mitigate phase delay.
In an embodiment, the frequency drift prediction unit identifies the phase of clock is delayed /advanced and the stores number of pulses and is compared with an ideal threshold of pulses (781250) which results in clock error.
In an embodiment, the compensator block is configured to compensate for the cloak error by applying precise adjustment to errors, either through addition or subtraction, ensuring optimal synchronization for enhanced communication process.
In an aspect, present invention provides a method for high accuracy satellite terminals timing synchronization for high data rate satcom network comprising steps of:
a) activating a frequency drift prediction unit when an 1PPS signal is absent to facilitate accurate frequency drift prediction;
b) measuring environmental conditions by a temperature compensation unit;
c) analysing temperature data from the temperature sensor based on a X-Cut lookup table from a datasheet by a processor; and
d) dynamically adjusting the frequency based on temperature variations, ensuring stable performance under varying temperature conditions by an adaptive control unit.

DETAILED DESCRIPTION OF DRAWINGS:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:
Fig. 1: illustrates a block diagram of timing synchronization Algorithm implementation method on FPGA.
Fig. 2: illustrates a counter timing diagram with 1PPS.
Fig. 3: illustrates the main program flow for interrupt alarm control.
Fig. 4: illustrates a parabolic curve depicting frequency error versus temperature in ppm or seconds per day.
Fig. 5: illustrates reference system clock-based crystal calibration flow chart.
Fig. 6: illustrates plot of original clock data and predicted clock values.

DETAILED DESCRIPTION:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
The terms “comprises”, “comprising”, “includes”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The present invention provides a system and method for high accuracy satellite terminals timing synchronization for high data rate satcom network.
In an embodiment, present invention provides a system for high accuracy satellite terminals timing synchronization for high data rate satcom network comprising:
a) a frequency drift prediction unit comprises a contingency mechanism which activates the frequency drift prediction unit when an 1PPS signal is absent to facilitate accurate frequency drift prediction in its absence;
b) a temperature compensation unit comprises an on-chip temperature sensor to measure environmental conditions;
c) a processor configured to analyse temperature data from the temperature sensor based on a X-Cut lookup table from datasheet; and
d) an adaptive control unit configured to dynamically adjust the frequency based on temperature variations, ensuring stable performance under varying temperature conditions.
In an embodiment, the adaptive control unit adjusts the frequency by implementing counter logic in conjunction with the 1PPS signal for precise frequency correction, ensuring synchronization and accuracy in timekeeping applications.
In an embodiment, the frequency drift prediction unit has an inbuilt linear regression model which re-utilizes past data for pre-emptive adjustments of the frequency.
In an embodiment, the 1PPS signal is absent the contingency mechanism implements a counter logic to count and store (in register) the number of clocks for 1 second to mitigate phase delay.
In an embodiment, the frequency drift prediction unit identifies the phase of clock is delayed /advanced and the stores number of pulses and is compared with an ideal threshold of pulses (781250) which results in clock error.
In an embodiment, the compensator block is configured to compensate for the cloak error by applying precise adjustment to errors, either through addition or subtraction, ensuring optimal synchronization for enhanced communication process.
In an embodiment, the present invention provides a method for high accuracy satellite terminals timing synchronization for high data rate satcom network comprising steps of:
a) activating a frequency drift prediction unit when an 1PPS signal is absent to facilitate accurate frequency drift prediction;
b) measuring environmental conditions by a temperature compensation unit;
c) analysing temperature data from the temperature sensor based on a X-Cut lookup table from a datasheet by a processor; and
d) dynamically adjusting the frequency based on temperature variations, ensuring stable performance under varying temperature conditions by an adaptive control unit.
The present disclosure is related to novel architecture for timing synchronisation, we will use predictive model like Linear Regression to predict the clock drift based on previous data and add into actual clock. This model will be used in absence of 1PPS signal for accurate timing synchronisation. Clock Drift Prediction: The system predicts the future clock drift based on past behaviour, enabling proactive compensation and improved timing accuracy by adjusting the local clock. Satellite-Assisted Correction: The terminal periodically receives correction data from the satellite, further refining the local clock and mitigating potential errors. Scalability and Flexibility: The system can be easily adapted to work with different time slot duration as minimum up to 1 milli second and making it suitable for various applications.
In one embodiment, the unique concept for achieving exceptionally accurate timing synchronisation in high data rate satellite communication terminals, leveraging advanced baseband hardware. The proposed solution encompasses a comprehensive approach by incorporating a robust drift prediction mechanism to pre-emptively correct timing discrepancies. Additionally, a temperature compensation algorithm addresses deviations caused by environmental factors, ensuring consistent performance. The system is designed with scalability and flexibility in mind, allowing seamless adaptation to varying operational conditions and diverse communication scenarios. By integrating drift prediction, temperature compensation, scalability and flexibility, this patent offers a holistic solution for high-precision satellite terminal timing synchronisation, enhancing the reliability and efficiency of high data rate satellite communication systems.
In another embodiment, The High accuracy satellite terminal timing synchronization on FPGA comprises of following features: Frequency Drift prediction mechanism; Temperature compensation algorithm; Method for Frequency error correction and Low-cost and Efficient timing synchronisation.
In another embodiment, Frequency Drift prediction mechanism is that the predictive model using linear regression model reutilizes past data for preemptive adjustments, and said system further includes a contingency mechanism, activating the predictive model when the 1PPS signal is absent to facilitate accurate frequency drift prediction in its absence.
In another embodiment, temperature compensation algorithm comprises a on chip temperature sensor to measure environmental conditions, a processor configured to analyse temperature data based on X-Cut lookup table from datasheet and an adaptive control mechanism to dynamically adjust the frequency based on temperature variations, ensuring stable performance under varying temperature conditions.
In another embodiment, method for frequency error correction utilizes counter logic in conjunction with a 1PPS signal for precise frequency correction, ensuring synchronisation and accuracy in timekeeping applications.
In another embodiment, Low-cost and efficient timing synchronisation utilizes streamlined processes and optimized resource utilization, ensuring accurate timing synchronisation with minimal resource expenditure.
The block diagram of Timing synchronization Algorithm development on FPGA is shown in Figure 1. As shown in Fig.1; Synchronizing two clocks with different frequencies involves converting one clock domain to the other using a clock domain crossing (CDC) approach. In this case, we want to synchronize a 1 Hz (1 PPS) clock to a 781.25 kHz clock.
For stage-1(S1): If output of CDC i.e., 781.25 KHz is phase synchronized with 1 PPS signal then it will directly be routed to system clock.
In absence of 1PPS signal, the following methods will be used to Compute the frequency drift and provide the accurate time reference system clock which will be used to synchronise the satellite terminal.
For stage-2 (S2): Initially, a reference of 1 Hz (1 PPS) signal is required to synchronise the output of CDC i.e., 781.25 KHz which requires 781250 clock cycles (781.25 X 1000 = 781250). Synchronisation of satellite terminal will not happen accurately if there is a phase delay / advance in due to crystal clock frequency instability. In order to mitigate phase delay / advance, the concept of Counter logic is used to count and store (in register) the number of clocks for 1 second that is 781250 will count. To identify whether the phase of clock is delayed / advanced, the stored number of pulses is compared with ideal number of pulses (781250) which results in clock error.
Counter timing diagram with 1PPS. is shown in Figure 2. The following formula will compute the drift frequency,
Error in Clock = Drift in frequency
Where, Drift in frequency = defined frequency – Actual Measured frequency Defined frequency = 781.25 KHz = 781250 Clock Cycles Actual Measured frequency = delayed / advanced frequency
The Error Counter register will store the difference in counter value.
If its negative value its indicating as crystal clock is running delayed and if the counter value is positive that means crystal clock is running in advance. The calibration block.
After computation of drift frequency, subsequently a compensator block is used to fine-tune the system clock by applying precise adjustment to errors, either through addition or subtraction, ensuring optimal synchronisation for enhanced communication process. This process continues to reduce the errors.
For stage-3(S3): This stage incorporates a temperature sensor on FPGA to monitor environmental conditions, the flow chart for recording temperature values and storing them in memory is as shown 5 in the Figure-3. Subsequently, a X-cut Frequency stability clock for every crystal in the datasheet will be disclosed and the same is captured and prepared the lookup table. Based on the board temperature which is measured in FPGA on die temperature sensor, the Lookup table frequency deviation will loaded from LUT and adding that deviation as well for the computing the frequency deviation of the crystal.
As shown in figure 4 & 5, Methods to Determine Calibration Value for Crystal Clock Error is disclosed.
Temperature vs Crystal error
(Delta f)/f0 (ppm) = –k (T – T0)2 ±10
Where, k = 0.038, T0 = sensor temperature, f0 = ideal frequency and T is the Ambient Temperature
Computation of Total Crystal error (TCE) based on lookup table and parabolic curve cut is given below:
TCE = – ((Total Crystal Error in ppm/1000000) x (Clocks per second in 781.25 kHz))
Error in seconds
Error in 1 Second = Error Clocks per Second x Clock Period
Calculating the error/second for 781.25 KHz crystal for one second having ppm and 1 ppm error, respectively
Error in 1 second for 781.25 kHz crystal with 20 ppm is = (20x781250 /1000000) x 1/781250 = 0.00002 Seconds
Calculate crystal frequency error using the following formula: Error counts = 781250 – TCE
Alarm interrupt controller block:
Alarm interrupt controller will provide the alarm interrupt to stage 2, Stage 3 and stage 4 which is user configurable at which the compensator should update the system clock with computed error it could be from every 1 sec to few hours.
Predicting the frequency drift of a crystal clock involves understanding the factors that contribute to drift and then modelling or measuring those factors, predict frequency drift based on historical data. Linear regression time-series analysis methods can be employed for this purpose. This stage computes the frequency drift and update the memory with error counter Value and if we receive the alarm interrupt from control unit then the linear regression model will be activate and compute the future frequency drift errors and update the calibration register according with computed values then Compensator will update the system clock.
The linear regression model is represented by the equation:
Dependent variable (Clock values) = slope × independent variable + intercept on Time axis + error (e).
The coefficients slope and intercept on time-axis are estimated from the data using methods like the least squares method, which minimizes the sum of the squared differences between the observed and predicted values of dependent variable.
The process of fitting a linear regression model involves estimating the coefficients and using the model for prediction or understanding the relationship between variables. The model assumes that the relationship between the variables is linear and that the errors (e) are normally distributed with a mean of zero. To plot the predicted values based on past values, the following python commands are used and the result is as shown in Fig6.

The graph plotted in Fig6 is being utilised to compensate the drift frequency based on predicted clock values, for this a compensator block is used to fine-tune the system clock by using PLL of a 781.25 KHz clock.
The Crystal frequency stability is depends on following factors along with temperature variation
a. Vibration and Mechanical Stress
b. Power Supply Voltage Variations
c. Electronic Noise
d. External Electromagnetic Interference (EMI)
e. Humidity
f. Component Tolerances
g. Manufacturing Variations
in the stage 4 process considering all above factors frequency deviation is computed and stored in a memory and used the same data for computing the future drift in the frequency in a given hardware and environmental condition. This stage of process is used for high accuracy and low cost optimal solution for the time synchronisation.
The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.

,CLAIMS:We Claim:

1. A system for high accuracy satellite terminals timing synchronization for high data rate satcom network comprising:
a) a frequency drift prediction unit comprises a contingency mechanism which activates the frequency drift prediction unit when an 1PPS signal is absent to facilitate accurate frequency drift prediction in its absence;
b) a temperature compensation unit comprises an on-chip temperature sensor to measure environmental conditions;
c) a processor configured to analyse temperature data from the temperature sensor based on a X-Cut lookup table from datasheet; and
d) an adaptive control unit configured to dynamically adjust the frequency based on temperature variations, ensuring stable performance under varying temperature conditions.
2. The system for high accuracy satellite terminals timing synchronization for high data rate satcom network as claimed in claim 1, wherein adaptive control unit adjusts the frequency by implementing a counter logic in conjunction with the 1PPS signal for precise frequency correction, ensuring synchronization and accuracy in timekeeping applications.
3. The system for high accuracy satellite terminals timing synchronization for high data rate satcom network as claimed in claim 1, wherein the frequency drift prediction unit has an inbuilt linear regression model which re-utilizes past data for pre-emptive adjustments of the frequency.
4. The system for high accuracy satellite terminals timing synchronization for high data rate satcom network as claimed in claim 1, wherein when 1PPS signal is absent the contingency mechanism implements a counter logic to count and store (in register) the number of clocks for 1 second to mitigate phase delay.
5. The system for high accuracy satellite terminals timing synchronization for high data rate satcom network as claimed in claim 1, wherein the frequency drift prediction unit identifies the phase of clock is delayed /advanced and the stores number of pulses and is comparing with an ideal threshold of pulses (781250) which results in clock error.
6. The system for high accuracy satellite terminals timing synchronization for high data rate satcom network as claimed in claim 1, wherein a compensator block is configured to compensate the cloak error by applying precise adjustment to errors, either through addition or subtraction, ensuring optimal synchronization for enhanced communication process.
7. A method for high accuracy satellite terminals timing synchronization for high data rate satcom network comprising steps of:
a) activating a frequency drift prediction unit when an 1PPS signal is absent to facilitate accurate frequency drift prediction;
b) measuring environmental conditions by a temperature compensation unit;
c) analysing temperature data from the temperature sensor based on a X-Cut lookup table from a datasheet by a processor; and
d) dynamically adjusting the frequency based on temperature variations, ensuring stable performance under varying temperature conditions by an adaptive control unit.