DESC:FORM-2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)

Title: A METHOD FOR CALIBRATION AND SYNCHRONIZATION OF SYNTHESIZERS DURING INTER PULSE OPERATION OF SYSTEMS

APPLICANT DETAILS:
(a) NAME: BHARAT ELECTRONICS LIMITED
(b) NATIONALITY: Indian
(c) ADDRESS: OUTER RING ROAD, NAGAVARA, BANGALORE 560045,
KARNATAKA, INDIA

PREAMBLE TO THE DESCRIPTION:
The following specification (particularly) describes the nature of the invention (and the manner in which it is to be performed):

A METHOD FOR CALIBRATION AND SYNCHRONIZATION OF SYNTHESIZERS DURING INTER PULSE OPERATION OF SYSTEMS

FIELD OF INVENTION:
The present disclosure relates in general to the field of electronics, and more particularly, relates to a method for calibration and synchronization of synthesizers during inter pulse operation of systems.

BACKGROUND OF THE INVENTION:
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly referenced is prior art.
In general, an active phased array system is a more advanced and sophisticated technology in which a beam of radio waves can be electronically steered to point in different directions without mechanically steering the antenna. This is usually achieved by using large number of transmit receive elements whose amplitude and phase are continuously varied in analog domain or in digital domain by the beam former module. It usually consists of various sub-modules such as Radiating Structure, Transmit-Receive Modules, Up-down Converters, Synthesizer, Waveform Generator, Digital Beam Former and Signal Processing Unit.
A frequency Synthesizer is an electronic system capable of generating a range of frequencies from a single stable reference frequency source. Synthesizers can be realized using direct, indirect and Direct Digital Synthesizer (DDS) methods. In direct synthesis the reference signal is modified by summing and multiplying with mixers, dividers and multipliers. In indirect synthesis Voltage Controlled Oscillator output is phase locked to a reference frequency. In DDS a signal is digitally constructed and then converted to analog signal. Unlike conventional methods, different kinds of modulated waveforms required for system functionality also be implemented using DDS method. In Active Array System, phase coherency aids in better signal-to-noise ratio and detection of small phase shifts on echo signals. Further in Doppler frequency processing can reduce the influence of fixed clutter. Exciter plays a vital role here by generating the modulated transmit signal as well as calibration signal for active array calibration.
A few of the prior arts relevant to the present invention are mentioned below:-
US20170315211A1 Loopback Techniques For Synchronization Of Oscillator Signal In RADAR: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.
US20200292666A1 Multi-chip Synchronization For Digital RADARS: A multi - chip MIMO radar system includes a plurality of transmitters and a plurality of receivers. Each of the pluralities of transmitters and receivers are arranged across a plurality of chips. The multi-chip MIMO radar system is configured to provide an exemplary chip synchronization such that the transmitters and receivers of each chip of the Radar system are synchronized with the transmitters and receivers of every other chip of the radar system.
US11038511 Apparatus and Methods For System Clock Compensation: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including , but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals , precision timing distribution and recovery, extrapolation of timing events for enhanced PLL update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and / or alignment to phase information lost in decimation.
US7624296 Method And Apparatus Synchronizing Multiple Direct Digital Synthesizers (DDSS) Across Multiple Printed Circuit Assembles: A radio frequency generating system comprises a synchronization board that receives an external clock signal from a clock source and generates multiple copies of the external clock signal. Each of a plurality of signal generation board receives a copy of the external clock signal from the synchronization board. Each signal generation board comprises a plurality of direct digital synthesizers that are synchronized using the external clock signal.
IEEE 2018: An Agile Automatic Frequency Calibration Technique for PLL: An agile automatic frequency calibration (AFC) technique is developed in PLL for the bluetooth low energy (BLE) applications. Instead of searching for an optimal tuning curve for 40 target frequencies in BLE, the tuning curve feature extraction (TCFE) technique is adopted to reduce necessary calibration times. Moreover, the initial value of each target frequency is adjusted dynamically according to previous result to accelerate calibration speed. The calibration is conducted foreground, then the optimal tuning curve is selected directly and the output frequency of PLL hops quickly in operation. The whole PLL was designed and fabricated in 0.18 um CMOS technology. Measurement results show that the time for foreground calibration is about 80 us and the frequency hops without the switch of tuning curves. Synthesizer circuit design. It includes dual loop, one loop is used for initial tuning, while another provides low phase noise performance by removing all frequency dividers from the loop.
IEEE 2021: Clock Distribution and Synchronization Based on DDS for SHINE: Shanghai High repetition rate X-ray Free Electron Lasers and Extreme light facility (SHINE) is expected to be the first hard X-ray FEL facility in China, which has been under construction. Hundreds of devices will be integrated in such kind of accelerators typically, and the perimeter of the SHINE accelerator is about 3.1 km. In order to make sure all the devices work exactly in a uniform manner, a high-precision multi-node clock distribution and synchronization system is required. For the reference clock fed into the clock distribution system is about 9.028 MHz, standard White Rabbit (WR) protocol cannot directly deal with it. A promising solution is that extracting the frequency and phase messages of the input clock by the DDS circuit on the master node, and then recovering the clock in all slave nodes according to the received frequency and phase messages. While the working clocks of both master and slave nodes are synchronized using WR. A prototype electronics is designed, and efforts are devoted to both hardware and Field Programmable Gate Array (FPGA) logic design to achieve high precision clock synchronization, fine phase adjustment, and frequency tuning. Test results show that the prototype can achieve multi-node machine clock distribution and synchronization at several kilometres distance, and the synchronization accuracy is better than 0.7 ns with the skew jitter better than 18 ps RMS within a frequency range from about 1 Hz to 1 MHz Moreover, the temperature drift is less than 2 ps/?.
IEEE 2012: A Coherent Accumulation Technique for Radar Signal with Inter-pulse Waveform Transformation: The inter-pulse multi-parameter joint agile waveform has gradually become one of the main techniques for anti-jamming of missile borne radar because it increases the difficulty of identification and forwarding of the jammer compared with other complex waveforms and improves the anti-jamming capability of the radar.
However, due to the phase discontinuity problem of the inter-pulse waveform, the traditional coherent accumulation method cannot be applied to detect the target.
Therefore, there is a need for techniques and methods for addressing the above-mentioned problems related to calibration and synchronization of synthesizers during inter pulse operation of systems, in addition to providing other technical advantages.

Objectives of the Invention:
The primary object of the present invention is to overcome the problem stated in the prior art.
Another object of the present invention is to provide a method and a system to realize phase synchronization of fast switching multiple DDS outputs and LUT based PLL calibration method to achieve faster spot frequency switching time for DDS-PLL based synthesizers.

SUMMARY OF THE INVENTION:
The present invention provides a system for calibration and synchronization of synthesizers during inter pulse operation of systems comprising:
a) an oven-controlled crystal oscillator OCXO (100) is configured to generate as a reference frequency;
b) a PLL1 (101), where the PLL1 (101) receives the reference frequency from the oven-controlled crystal oscillator OCXO (100);

c) plurality of DDS1& DDS2 (103 & 104), where the PLL1 output serves as clock to both the DDS1 & the DDS2 where the outputs of the DDS1 & the DDS2 are filtered using a band pass filter; and
d) at least two mixers (105 & 106) where the output of the band pass filter is converted to an X-band frequency with the mixers (105 & 106);
where in LO is generated from another PLL2 (102), where the clock for the PLL2 (1020 is coming from the same oven-controlled crystal oscillator OCXO, where PLL2 is operated in fractional mode to have very fine frequency steps which will be an ECCM feature to avoid jammers.
In an embodiment, the output channels are configured of an agile frequency switch between Transmit and receive mode, i.e. LFM in TX mode to IF offset spot frequency for receive mode.
In an embodiment, for normal system transmit mode of operation Tx output from module which has LFM modulation goes to the Transmit Receive chain to the final antenna element.
In an embodiment, during receive mode WGM frequency switches to a spot frequency IF offset which act as LO for Down converter which is used for down conversion of the received echo from the target.
In an embodiment, the DDS1(202) and the DDS2(203) chip comprises an internal RAM register is configured to update the DDS output frequency, amplitude or phase within a few Nano seconds which it decided by the internal system clock of DDS.
In an embodiment, the DDS1 act as master here giving the SYNC_OUT signal which is distributed back to itself and other slave DDS2 uses fan-out buffer circuit (204).
In an embodiment, the frequency switching needs to be done FPGA based control circuitry updates the PLL2 (205) fractional and PLL1 (206) integer registers, where the switching time for PLL2 is sum of analog locking time and internal calibration time.
In an embodiment, in case of wideband synthesizers with internal VCO there is an auto calibration feature where PLL chip will determine the VCO core, bands and bias levels required to lock to the newly loaded frequency.
The present invention provides a method for calibration and synchronization of synthesizers during inter pulse operation of systems comprising:
switching each of the two output channels has independent DDS, mixer, common high frequency PLL, where one of output channels is switched between modulated or unmodulated frequency maintaining phase coherency; and
generating a phase coherent Cal signal for Calibration Other output channel where on board programmable device configures both PLL and DDS using SPI and also loads waveforms in DDS chips and stores PLL calibration data in LUT for fast frequency spot updates.

DETAILED DESCRIPTION OF DRAWINGS:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:
Fig. 1: illustrates a block diagram of waveform generation.
Fig. 2: illustrates a block diagram of waveform synchronization.
Fig. 3: illustrates a flow chart of PLL Calibration data capture.
Fig. 4: illustrates an arrangement of the RF and Digital Circuitry of the multilayer hybrid PCB layout.

DETAILED DESCRIPTION:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
The terms “comprises”, “comprising”, “includes”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The brief objective of the present invention describes a method to realize phase synchronization of fast switching multiple DDS outputs and LUT based PLL calibration method to achieve faster spot frequency switching time for DDS-PLL based synthesizers. Unlike conventional System where in low frequency IF is up/down converted in Transmit and receive chain using Fixed Local Oscillator with dedicated sub modules like Waveform Generator, Local Oscillator module and TX/RX module. Here a novel approach is adopted to generate modulated LO for transmit and IF offset spot for receive mode which reduces overall SWaP of the module. Waveform generator, synthesizer and System calibration is realised in a single module. Synthesizer module generates the Modulated signal for the System transmit mode. During receive frequency need to be switched to new frequency same as the receiver IF frequency. Here pulse to pulse coherence and phase coherence during IF frequency switching need to be ensured. We have used two independent DDS chips here DDS1 for modulated transmit signal & receive LO generation. Similarly DDS2 output which is used for calibration signal generation. DDS2 also needs to have a deterministic phase w.r.t. DDS1 output. This is achieved by resetting the phase of DDS 1 & 2 at starting of every transmit pulse using FPGA based method. The output signals of both DDS are up converted to final frequency by mixing with a high frequency PLL2 output.
To address the problem in the existing system, a new processing process including coherent accumulation is proposed in the present based on pulse synchronous alignment technology and variable DFT factor method. The present invention focuses on the analysis of phase compensation and accumulation methods on the PRI and frequency agile waveform, and does targeted simulation verification. The simulation results prove that the process can complete the coherent accumulation and target detection for the ideal homogeneous point target very well.
The present invention discloses a method to realize Calibration and Synchronization of Synthesizers during inter pulse operation of systems, wherein each of two output channel has independent Digital Synthesizer, frequency converter, common high frequency variable source.
In the present invention, wherein one of the channel output switches between modulated or un-modulated frequency. Other output channel generates a phase coherent signal for system Calibration.
In the present invention, wherein DDS based waveform generation circuitry and method is used to achieve pulse to pulse phase coherence and waveform agility.
In the present invention, wherein a phase coherent frequency output along facilitating System calibration and Built in Test Equipment (BITE).
In the present invention, wherein a Look Up Table based PLL frequency switching is used for achieving Fast locking time in order of microseconds through on board programmable device which loads waveforms in DDS chips and stores PLL calibration.
In the present invention, wherein a single multilayer Hybrid PCB stack up hosts waveform generation, up conversion, down conversion and calibration with minimal interface.
Various embodiments of the present disclosure are further described with reference to FIG. 1 to FIG. 4.
FIG. 1 illustrates a block diagram of waveform generation, in accordance with an embodiment of the present disclosure. FIG. 1 shows the scheme to realize Local oscillator signals using DDS and PLL combination. It has Oven controlled crystal oscillator OCXO (100) as a reference frequency is fed to PLL1 (101). PLL1 output serves as clock to both DDS1& DDS2 (103 & 104). The DDS1 & DDS2 outputs are filtered using band pass filters and up converted to X-band frequency with two more mixers (105 & 106) where in LO is generated from another PLL2 (102). The clock for this PLL2 is coming from the same OCXO. PLL2 is operated in fractional mode to have very fine frequency steps which will be an ECCM feature to avoid jammers.
Both of the output channels are capable of the agile frequency switching between Transmit and receive mode, i.e. LFM in TX mode to IF offset spot frequency for receive mode. RAM based playback of DDS waveform is used here which can be easily re-configured using FPGA to change System Waveforms.
Many filters and amplifiers are used in the path in order to achieve the required level and spurious rejection which is not shown in the figure for the sake of simplicity.
For normal System transmit mode of operation Tx output from module which has LFM modulation goes to the Transmit Receive chain to the final Antenna element. During receive mode WGM frequency switches to a spot frequency IF offset which act as LO for Down converter which is used for down conversion of the received echo from the target.
FIG. 2 illustrates a block diagram of waveform synchronization, in accordance with an embodiment of the present disclosure.
FIG. 3 illustrates a flow chart of PLL Calibration data capture, in accordance with an embodiment of the present disclosure.
Detail of Phase synchronization scheme is shown in FIG. 2. DDS1(202) and DDS2(203) chip comes with internal RAM register which can be used to update the DDS output frequency, amplitude or phase within few Nano seconds which it decided by the internal system clock of DDS. It has greater than thousand locations in RAM memory which can be used to store different waveforms which can be selected using profile pins of the DDS. Once we switch between waveforms DDS phase accumulator can be set to reset the phase in order to maintain the phase coherence between frequency switching using FPGA (201) programming. For the coherency of the CAL signal output synch clock distribution circuit shown in FIG. 2 need to be adopted. DDS1 act as master here giving the SYNC_OUT signal which is distributed back to itself and other slave DDS2 uses fan-out buffer circuit (204). Once the circuit is powered ON the SYNC signal distribution circuit ensures there is a fixed phase relation between DDS outputs. Additionally, FPGA method need to ensure to Issue a simultaneous update of profile pins of both DDS to achieve phase coherency of outputs.
Whenever a frequency switching needs to be done FPGA based control circuitry updates the PLL2 (205) fractional and PLL1 (206) integer registers. The switching time for PLL2 is sum of analog locking time and internal calibration time. In case of wideband synthesizers with internal VCO there is an auto calibration feature where PLL chip will determine the VCO core, bands and bias levels required to lock to the newly loaded frequency. This calibration times usually comes in the order of 3-4 milli seconds. This calibration data is unique to individual chips and it has to be performed for each chip on the board. One advantage is that once it is done we can read back calibration data and Look Up Table (LUT) can be made and use the same data using FPGA for achieving faster switching time in the order of 20-30 microseconds. The method is shown in FIG. 3. During the Power ON this calibration procedure is included in the FPGA code. It initially configures the wide band PLL to all the operating spot frequencies one by one with internal auto calibration enabled. Then FPGA wait for the PLL to Lock and reads back the calibration data such as VCO core, Band, Bias values and stores it in a Look Up Table. Once all spot data is captured and stored, this data will be used for further frequency updates to achieve faster lock time.
FIG. 4 illustrates an arrangement of the RF and Digital Circuitry of the multilayer hybrid PCB layout, in accordance with an embodiment of the present disclosure. FIG. 4 shows the arrangement of the RF and Digital Circuitry (402 & 401) of the multilayer hybrid PCB. 12-layered Composite PCB with RF substrate on top for high frequency RF circuit routing followed with FR4 substrate for routing high speed control and power supply lines. Mechanical Partitions blocks (403) are fixed on top of PCB for channelizing RF & isolating the interference between different frequency sections. Cavity simulation are performed to finalize the channel dimensions depending on the resonant frequency.
The present invention discusses method for Calibration and Synchronization of Synthesizers during inter pulse operation of systems. Each of two output channel has independent DDS, mixer, common high frequency PLL. One of output channel can be switched between modulated or un modulated frequency maintaining phase coherency. Other output channel generates a phase coherent Cal signal for Calibration. On board programmable device configures both PLL and DDS using SPI and also loads waveforms in DDS chips and stores PLL calibration data in LUT for fast frequency spot updates. It is realised on a single PCB wherein multilayer Hybrid PCB stack up is used for realizing both high speed digital circuitry and sensitive X-Band RF circuits with minimal interference resulting in elimination of interconnection cables, improved reliability & hardware complexity.
NOVEL ASPECTS OF THE PRESENT INVENTION
The present invention relates to a method for Calibration and Synchronization of Synthesizers during inter pulse operation of systems.
The Novel aspects of the invention are:
1. Fast Frequency Switching Modulated Waveform Generation during Transmit mode and switching of the same to IF offset during Receive mode in the order of nano seconds enables to minimize hardware compared to conventional architecture which use fixed LOs and waveform generator based IF generation.
2. DDS based waveform generation circuitry and algorithm enables to achieve agile frequency switching between multiple pulse radar waveforms and ensuring phase coherency between them.
3. Look Up Table based PLL frequency switching for Fast locking time through programmable device in order of microseconds to achieve jamming immunity ECCM feature.
4. A phase coherent frequency output facilitating System calibration and Built in Test Equipment (BITE).
5. A single multilayer Hybrid PCB stack up is used for realizing both high speed digital circuitry and sensitive X-Band RF circuits with minimal interference.
The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:We Claim:

1. A system for calibration and synchronization of synthesizers during inter pulse operation of systems comprising:
a) an oven-controlled crystal oscillator OCXO (100) is configured to generate as a reference frequency;
b) a PLL1 (101), where the PLL1 (101) receives the reference frequency from the oven-controlled crystal oscillator OCXO (100);
c) plurality of DDS1& DDS2 (103 & 104), where the PLL1 output serves as clock to both the DDS1 & the DDS2 where the outputs of the DDS1 & the DDS2 are filtered using a band pass filter; and
d) at least two mixers (105 & 106) where the output of the band pass filter is converted to an X-band frequency with the mixers (105 & 106);
where in LO is generated from another PLL2 (102), where the clock for the PLL2 (1020 is coming from the same oven-controlled crystal oscillator OCXO, where PLL2 is operated in fractional mode to have very fine frequency steps which will be an ECCM feature to avoid jammers.
2. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein an output channels is configured of an agile frequency switch between Transmit and receive mode, i.e. LFM in TX mode to IF offset spot frequency for receive mode.
3. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein for normal system transmit mode of operation Tx output from module which has LFM modulation goes to the Transmit Receive chain to the final antenna element.
4. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein during receive mode WGM frequency switches to a spot frequency IF offset which act as LO for Down converter which is used for down conversion of the received echo from the target.
5. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein the DDS1(202) and the DDS2(203) chip comprises an internal RAM register is configured to update the DDS output frequency, amplitude or phase within a few Nano seconds which it decided by the internal system clock of DDS.
6. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein DDS1 act as master here giving the SYNC_OUT signal which is distributed back to itself and other slave DDS2 uses fan-out buffer circuit (204).
7. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein a frequency switching needs to be done FPGA based control circuitry updates the PLL2 (205) fractional and PLL1 (206) integer registers, where the switching time for PLL2 is sum of analog locking time and internal calibration time.
8. The system for calibration and synchronization of synthesizers during inter pulse operation of systems as claimed in claim 1, wherein in case of wideband synthesizers with internal VCO there is an auto calibration feature where PLL chip will determine the VCO core, bands and bias levels required to lock to the newly loaded frequency.
9. A method for calibration and synchronization of synthesizers during inter pulse operation of systems comprising:
switching each of the two output channels has independent DDS, mixer, common high frequency PLL, where one of output channels is switched between modulated or unmodulated frequency maintaining phase coherency; and
generating a phase coherent Cal signal for Calibration Other output channel where on-board programmable device configures both PLL and DDS using SPI and also loads waveforms in DDS chips and stores PLL calibration data in LUT for fast frequency spot updates.