DESC:TECHNICAL FIELD
The present disclosure relates to the field of Field Programmable Gate Arrays (FPGAs). More particularly, the present disclosure relates to a method and apparatus to boot soft core processor of FPGA from external media, ensuring runtime configuration while maintaining data confidentiality.
BACKGROUND
Field Programmable Gate Arrays (FPGAs) are widely used for their flexibility in implementing custom logic and soft-core processors. However, existing systems face significant challenges in securely configuring and booting soft-core processors, especially in applications where confidentiality and runtime flexibility are critical.
Traditionally, FPGA systems depend on non-volatile memory (e.g., flash storage) to store configuration data, and boot files. While this simplifies system startup, it introduces security risks, as sensitive data persists even after the system is powered off. This makes confidential programs and proprietary data vulnerable to unauthorized access, tampering, or reverse engineering.
A further drawback is the lack of runtime flexibility in existing FPGA systems. Dynamically loading or executing new programs often requires reprogramming or overwriting the non-volatile memory, which limits adaptability and operational efficiency. For mission-critical applications such as defence, secure communications, and real-time systems, this inability to perform on-the-fly reconfiguration is a significant limitation.
Existing systems also rely on host devices like microcontrollers or additional FPGAs for initialization, which can only configure the FPGA’s hardware description language (HDL) portion. The soft-core processor still requires configuration data stored in non-volatile memory, preventing a secure, volatile-only execution environment where all data is erased upon power-off.
Another limitation is the constrained On-Chip RAM capacity in FPGAs. While critical regions like reset and exception vectors can reside in On-Chip RAM, larger applications require non-volatile storage, further compromising security and performance.
Prior art such as US5892962, US8341469, and US10394991B2 highlights methods for FPGA configuration but necessitates the presence of pre-stored configuration data in non-volatile memory, creating vulnerabilities where sensitive programs persist after power-off, making them prone to unauthorized access and tampering. Additionally, the paper on “Building Embedded Systems Using Soft IP Cores” emphasizes the use of non-volatile memory to store application data for soft-core processors, limiting the ability to dynamically load or modify programs at runtime. These approaches lack the flexibility to support on-the-fly reconfiguration and prevent the complete erasure of sensitive data, a critical requirement for secure systems handling proprietary information.
These limitations emphasize the need for a secure, efficient solution that eliminates reliance on non-volatile memory, enables dynamic runtime reconfiguration, and ensures complete erasure of sensitive data upon shutdown. Such a system is essential for secure, flexible, and adaptable FPGA-based operations.
SUMMARY
In one aspect of the present disclosure a system for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media is provided.
In some aspects of the present disclosure, a system for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, comprising a host FPGA configured to retrieve configuration data and application logic from an external media device; a target FPGA communicatively coupled with the host FPGA, the target FPGA comprising: an On-Chip RAM configured to store reset vectors, exception vectors, and runtime-critical sections of the application logic; a soft core processor adapted to execute the application logic; an SDRAM configured to store application data, including variables, constants, and runtime sections not stored in the On-Chip RAM; an external media interface enabling the host FPGA to securely retrieve configuration data and application logic from the external media device; a memory allocation engine configured to optimize memory usage by segregating data into On-Chip RAM and SDRAM; a programming engine within the host FPGA, adapted to transmit configuration data and application logic to the target FPGA; and a runtime erasure mechanism configured to securely erase all configuration data and application logic from the On-Chip RAM and SDRAM upon system power-off.
In some aspects of the present disclosure, the external media device stores the configuration data and application logic in a precompiled hexadecimal (.hex) format.
In some aspects of the present disclosure, the host FPGA retrieves the configuration data and application logic via a secure interface, selected from USB, SPI, or Ethernet.
In some aspects of the present disclosure, the On-Chip RAM is configured to store only critical sections of the application logic, including. reset, .exception, and .text segments.
In some aspects of the present disclosure, the SDRAM stores application sections including variables, constants, stack, and heap memory to optimize the use of On-Chip RAM.
In some aspects of the present disclosure, the programming engine within the host FPGA transmits the configuration data in Passive Serial or Slave Serial mode to program the target FPGA.
In some aspects of the present disclosure, the soft-core processor within the target FPGA is adapted to execute programs dynamically without requiring storage in non-volatile memory.
In some aspects of the present disclosure, the runtime erasure mechanism ensures the complete removal of sensitive configuration data upon system power-off, enhancing data security.
In some aspects of the present disclosure, the memory allocation engine dynamically adjusts memory usage between the On-Chip RAM and SDRAM to support large and complex applications.
In some aspects of the present disclosure, a method for configuring a soft core processor of a Field Programmable Gate Array (FPGA) from external media, the method comprising: retrieving, by a host FPGA, configuration data and application logic from an external media device through an external media interface; transmitting, by the host FPGA, the retrieved configuration data and application logic to a target FPGA; initializing an On-Chip RAM of the target FPGA with reset vectors, exception vectors, and runtime-critical sections of the application logic; storing application data, including variables, constants, and runtime sections, in an SDRAM communicatively coupled to the target FPGA; executing the application logic on a soft core processor within the target FPGA; optimizing memory allocation by segregating data into the On-Chip RAM and SDRAM using a memory allocation engine; programming the target FPGA using the transmitted configuration data and application logic; and securely erasing all configuration data and application logic from the On-Chip RAM and SDRAM upon system power-off.
BRIEF DESCRIPTION OF DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, show certain aspects of the subject matter disclosed herein and together with the description, help explain some of the principles associated with the disclosed implementations. In the drawing,
Figure 1 illustrates a system for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, in accordance with an aspect of the present disclosure; and
Figure 2 illustrates a method for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, in accordance with an aspect of the present disclosure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Various embodiments of the disclosure are discussed in detail below. While specific implementations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the disclosure. Thus, the following description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding of the disclosure. However, in certain instances, known details are not described in order to avoid obscuring the description.
References to one or an embodiment in the present disclosure can be references to the same embodiment or any embodiment; and such references mean at least one of the embodiments.
Reference to "one embodiment", "an embodiment", “one aspect”, “some aspects”, “an aspect” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others.
The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Alternative language and synonyms may be used for any one or more of the terms discussed herein, and no special significance should be placed upon whether or not a term is elaborated or discussed herein. In some cases, synonyms for certain terms are provided.
A recital of one or more synonyms does not exclude the use of other synonyms.
The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only and is not intended to further limit the scope and meaning of the disclosure or of any example term. Likewise, the disclosure is not limited to various embodiments given in this specification. Without intent to limit the scope of the disclosure, examples of instruments, apparatus, methods and their related results according to the embodiments of the present disclosure are given below. Note that titles or subtitles may be used in the examples for convenience of a reader, which in no way should limit the scope of the disclosure. Unless otherwise defined, technical and scientific terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In the case of conflict, the present document, including definitions will control.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or can be learned by practice of the herein disclosed principles. The features and advantages of the disclosure can be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the disclosure will become more fully apparent from the following description and appended claims or can be learned by the practice of the principles set forth herein.
As discussed before, the above-mentioned limitations emphasize the need for a secure, efficient solution that eliminates reliance on non-volatile memory, enables dynamic runtime reconfiguration, and ensures complete erasure of sensitive data upon shutdown. Such a system is essential for secure, flexible, and adaptable FPGA-based operations. The present disclosure, therefore, addresses these shortcomings by introduces a system and method for configuring a soft-core processor in a Field Programmable Gate Array (FPGA) using external media. It includes a host FPGA that retrieves and transmits configuration data to a target FPGA, optimizing memory allocation between On-Chip RAM and SDRAM. A soft-core processor executes the application logic, while a runtime erasure mechanism ensures secure data removal upon power-off. The system supports secure data retrieval through interfaces like USB, SPI, or Ethernet.
Figure 1 illustrates a system for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, in accordance with an aspect of the present disclosure. The present disclosure discloses a system and method for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media. The system described in Figure 1 comprises a host FPGA 101, a target FPGA 102, an external media device 103, and various components that optimize memory allocation and enhance data security during configuration and execution.
In some aspects of the present disclosure, the system 100 is designed to configure and execute a soft-core processor within the target FPGA 102 by retrieving configuration data and application logic from an external media device 103. The host FPGA 101 retrieves the necessary data from the external media device 103 and transmits it to the target FPGA 102, where the data is used to initialize a soft-core processor 102-1 for execution. The system 100 also optimizes memory usage, segregating application data between an On-Chip RAM 102-2 and a SDRAM 102-3, ensuring efficient data storage and secure memory management.
In some aspects of the present disclosure, the host FPGA 101 plays a important role in the system 100 by retrieving configuration data and application logic from the external media device 103. This retrieval is accomplished through an external media interface that supports various secure communication protocols, such as USB, SPI, or Ethernet. The host FPGA 101 is programmed to handle the transmission of the retrieved configuration data and application logic to the target FPGA 102 via a secure programming engine. This process allows the system 100 to program the target FPGA 102 with the required configuration and logic, ensuring that the soft-core processor 102-1 is ready for execution.
In some aspects of the present disclosure, the external media device 103 stores the configuration data and application logic in a precompiled hexadecimal (.hex) format. This format is widely used for FPGA configuration due to its simplicity and compatibility with FPGA programming tools. The host FPGA 101 retrieves this data from the external media device 103 and ensures secure data transmission to the target FPGA 102, providing flexibility in configuration while ensuring the integrity and security of the data.
In some aspects of the present disclosure, the target FPGA 102 comprises multiple components that work together to execute the application logic and store necessary data. These components include the soft-core processor 102-1, On-Chip RAM 102-2, and the SDRAM 102-3. The target FPGA 102 is communicatively coupled with the host FPGA 101 and is designed to receive and execute the configuration data and application logic transmitted by the host FPGA 101.
In some aspects of the present disclosure, the soft-core processor 102-1 within the target FPGA 102 is configured to execute the application logic. It operates dynamically without requiring non-volatile memory, relying on the configuration and application logic provided by the host FPGA 101 to perform its tasks. The soft-core processor 102-1 processes instructions, executes programs, and interacts with memory resources such as On-Chip RAM 102-2 and the SDRAM 102-3 during runtime.
In some aspects of the present disclosure, the On-Chip RAM 102-2 is an important component in the target FPGA 102. It is specifically designed to store critical sections of the application logic, such as reset vectors, exception vectors, and runtime-critical sections. These are essential for the proper initialization and execution of the soft-core processor 102-1. By storing only critical sections, the On-Chip RAM 102-2 ensures that the target FPGA 102 operates efficiently while reducing the need for external memory resources. The On-Chip RAM 102-2 enhances the overall performance of the system 100 by providing faster access to critical data.
In some aspects of the present disclosure, the SDRAM 102-3 is another key memory resource within the target FPGA 102. It is used to store larger sections of the application logic, including variables, constants, and runtime sections that are not stored in the On-Chip RAM 102-2. This includes sections such as stack and heap memory, which are essential for dynamic memory allocation during program execution. The SDRAM 102-3 ensures that the target FPGA 102 has ample storage for all application data while optimizing the use of On-Chip RAM 102-2. The memory allocation engine, discussed later, ensures that data is stored in the appropriate memory location based on its criticality and usage during execution.
In some aspects of the present disclosure, a key feature of the system 100 is the memory allocation engine (not shown), which optimizes memory usage by segregating data into On-Chip RAM 102-2 and SDRAM 102-3. The memory allocation engine dynamically allocates and deallocates memory based on the needs of the application. Critical sections of the application logic, such as reset vectors and exception vectors, are allocated to On-Chip RAM 102-2 for fast access and minimal latency. Less critical data, including variables and constants, is stored in the SDRAM 102-3 to ensure efficient memory usage.
In some aspects of the present disclosure, the memory allocation engine adjusts memory usage dynamically based on the runtime needs of the application, ensuring that large and complex applications can be executed efficiently. By segregating data into these two types of memory, the system 100 maximizes the performance of the soft-core processor 102-1 and reduces the likelihood of memory bottlenecks.
In some aspects of the present disclosure, the system 100 also incorporates a secure runtime erasure mechanism (not shown), which is responsible for ensuring the complete removal of sensitive configuration data and application logic upon system power-off. The secure runtime erasure mechanism (mechanism is particularly important for systems that handle sensitive data or are deployed in environments) where data security is paramount. Upon power-off, the runtime erasure mechanism securely clears all data from both the On-Chip RAM 102-2 and SDRAM 102-3, ensuring that no residual data remains that could be exploited or accessed by unauthorized parties. This feature enhances the security of the system 100 and makes it suitable for use in applications where data privacy and protection are critical, such as in military, financial, or healthcare systems.
In some aspects of the present disclosure, the external media interface is an important aspect of the system 100, enabling the host FPGA 101 to securely retrieve configuration data and application logic from the external media device 103. The interface supports various communication protocols, including USB, SPI, and Ethernet, providing flexibility in the types of external media devices that can be used. The system 100 ensures secure data transfer by using encryption and authentication methods to protect the integrity of the data during transmission. This interface allows the system 100 to retrieve configuration data and application logic from external sources, making it adaptable to different use cases and environments.
In some aspects of the present disclosure, the system 100 for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, as depicted in Figure 1, provides a comprehensive and secure solution for programming and executing FPGA-based applications. The system 100 includes the host FPGA 101, which retrieves and transmits configuration data and application logic to the target FPGA 102. The target FPGA 102 efficiently utilizes On-Chip RAM 102-2 and SDRAM 102-3 for data storage, while the memory allocation engine ensures optimal memory usage. The soft-core processor 102-1 executes the application logic, and the runtime erasure mechanism ensures data security. By supporting secure data retrieval and programming, this system 100 offers flexibility, performance, and security for FPGA-based applications in a variety of domains.
Figure 2 illustrates a method for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, in accordance with an aspect of the present disclosure. The present method 200 a process for configuring a soft-core processor in a Field Programmable Gate Array (FPGA) using external media. It involves retrieving configuration data and application logic from an external media device, transmitting this data to a target FPGA, and executing the application logic on a soft-core processor. The method 200 also includes optimizing memory allocation between On-Chip RAM and SDRAM, and securely erasing all data from memory upon power-of.
At step 202, the method 200 involves retrieving, by a host FPGA 101, configuration data and application logic from an external media device 103 through an external media interface.
At step 204, the method 200 involves transmitting, by the host FPGA 101, the retrieved configuration data and application logic to a target FPGA 102.
At step 206, the method 200 involves initializing an On-Chip RAM 102-2 of the target FPGA 102 with reset vectors, exception vectors, and runtime-critical sections of the application logic.
At step 208, the method 200 involves storing application data, including variables, constants, and runtime sections, in an SDRAM 102-3 communicatively coupled to the target FPGA 102.
At step 210, the method 200 involves executing the application logic on a soft-core processor 102-1 within the target FPGA 102.
At step 212, the method 200 involves optimizing memory allocation by segregating data into the On-Chip RAM 102-2 and SDRAM 102-3 using a memory allocation engine.
At step 214, the method 200 involves programming the target FPGA 102 using the transmitted configuration data and application logic.
At step 216, the method 200 involves securely erasing all configuration data and application logic from the On-Chip RAM 102-2 and SDRAM 102-3 upon system power-off.
Advantages:
• The present disclosure provides a system that eliminates the need for non-volatile memory, thereby ensuring enhanced security for sensitive processes.
• The present disclosure provides a system that enables dynamic runtime configuration, allowing for the flexible execution of different processes.
• The present disclosure provides a system that ensures complete erasure of data upon power-off, preventing unauthorized access.
• The present disclosure provides a system that optimizes memory usage by efficiently utilizing both on-chip RAM and SDRAM.
• The present disclosure provides a system that supports secure and adaptable FPGA operation for mission-critical applications.
The implementation set forth in the foregoing description does not represent all implementations consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the described subject matter. Although a few variations have been described in detail above, other modifications or additions are possible. In particular, further features and/or variations can be provided in addition to those set forth herein. For example, the implementation described can be directed to various combinations and sub combinations of the disclosed features and/or combinations and sub combinations of the several further features disclosed above. In addition, the logic flows depicted in the accompanying figures and/or described herein do not necessarily require the particular order shown, or sequential order, to achieve desirable results. Other implementations may be within the scope of the following claims.
,CLAIMS:We claim:
1. A system (100) for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, comprising:
a host FPGA (101) configured to retrieve configuration data and application logic from an external media device (103);
a target FPGA (102) communicatively coupled with the host FPGA (101), the target FPGA (102) comprising:
an On-Chip RAM (102-2) configured to store reset vectors, exception vectors, and runtime-critical sections of the application logic;
a soft-core processor (102-1) adapted to execute the application logic;
an SDRAM (102-3) configured to store application data, including variables, constants, and runtime sections not stored in the On-Chip RAM (102-2);
an external media interface enabling the host FPGA (101) to securely retrieve configuration data and application logic from the external media device (103);
a memory allocation engine onfigured to optimize memory usage by segregating data into On-Chip RAM (102-2) and SDRAM (102-3);
a programming engine within the host FPGA (101), adapted to transmit configuration data and application logic to the target FPGA (102); and
a runtime erasure mechanism configured to securely erase all configuration data and application logic from the On-Chip RAM (102-2) and SDRAM (102-3) upon system power-off.
2. The system (100), as claimed in claim 1, wherein the external media device (103) stores the configuration data and application logic in a precompiled hexadecimal (.hex) format.
3. The system (100), as claimed in claim 1, wherein the host FPGA (101) retrieves the configuration data and application logic via a secure interface, selected from USB, SPI, or Ethernet.
4. The system (100), as claimed in claim 1, wherein the On-Chip RAM (102-2) is configured to store only critical sections of the application logic, including .reset, .exception, and .text segments.
5. The system (100), as claimed in claim 1, wherein the SDRAM (102-3) stores application sections including variables, constants, stack, and heap memory to optimize the use of On-Chip RAM (102-2).
6. The system (100), as claimed in claim 1, wherein the programming engine within the host FPGA (101) transmits the configuration data in Passive Serial or Slave Serial mode to program the target FPGA (102).
7. The system (100), as claimed in claim 1, wherein the soft-core processor (102-1) within the target FPGA (102) is adapted to execute programs dynamically without requiring storage in non-volatile memory.
8. The system (100), as claimed in claim 1, wherein the runtime erasure mechanism ensures the complete removal of sensitive configuration data upon system power-off, enhancing data security.
9. The system (100), as claimed in claim 1, wherein the memory allocation engine dynamically adjusts memory usage between the On-Chip RAM (102-2) and SDRAM (102-3) to support large and complex applications.
10. A method (200) for configuring a soft-core processor of a Field Programmable Gate Array (FPGA) from external media, the method comprising:
retrieving (202), by a host FPGA (101), configuration data and application logic from an external media device (103) through an external media interface;
transmitting (204), by the host FPGA (101), the retrieved configuration data and application logic to a target FPGA (102);
initializing (206)an On-Chip RAM (102-2) of the target FPGA (102) with reset vectors, exception vectors, and runtime-critical sections of the application logic;
storing (208) application data, including variables, constants, and runtime sections, in an SDRAM (102-3) communicatively coupled to the target FPGA (102);
executing (210) the application logic on a soft-core processor (102-1) within the target FPGA (102);
optimizing (212) memory allocation by segregating data into the On-Chip RAM (102-2) and SDRAM (102-3) using a memory allocation engine;
programming (214) the target FPGA (102) using the transmitted configuration data and application logic; and
securely erasing (216) all configuration data and application logic from the On-Chip RAM (102-2) and SDRAM (102-3) upon system power-off.

Dated this 13th day of March 2025

Dr. Sudhir Raja Ravindran [IN/PA-384] Agent for Applicant