DESC:FORM-2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)

Title: A COPROCESSOR SYSTEM

APPLICANT DETAILS:
(a) NAME: BHARAT ELECTRONICS LIMITED
(b) NATIONALITY: Indian
(c) ADDRESS: Outer Ring Road, Nagavara, Bangalore 560045, Karnataka, India

PREAMBLE TO THE DESCRIPTION:
The following specification (particularly) describes the nature of the invention (and the manner in which it is to be performed):
A COPROCESSOR SYSTEM

FIELD OF INVENTION:
The present disclosure/invention relates to a coprocessor system.

BACKGROUND OF THE INVENTION:
The following background discussion includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication expressly or implicitly
Generally, coprocessors are well known in the art which are used to supplement the functions of the primary processor.
One of the prior art discloses systems dedicated to encrypted data processing. In this prior art, an arithmetic logic unit is strategically positioned to receive encrypted data, process it based on the information presented at its inputs, and subsequently produce encrypted data, all without necessitating encryption or decryption within the processor.
Another prior art focuses on enabling processing units to efficiently perform cryptographic operations by utilizing an arithmetic computation unit for discrete binary computations. The coprocessors are tailored for fast, low-power computation of specific cryptographic functions, extending to post-quantum secure operations. Control registers within the coprocessors are writable by a processing unit providing configurability, and the computation of addresses for sources and destinations allows for flexibility in computation.
In the described system of the prior art, the arithmetic logic unit undertakes operation on encrypted data, leading to a streamlined processing approach where the primary processor is relieved of encryption or decryption responsibilities.
Further, technical challenges include ensuring compatibility of the coprocessor's dedicated interface with external devices, maintaining data integrity and security, managing resource allocation for optimal performance, achieving real-time communication, and mitigating interference with other system components. These require careful planning, robust error handling, and continuous optimization to ensure seamless integration without compromising security or performance.
Therefore, there is a need in the art with an improved coprocessor system to solve the above-mentioned limitations.

OBJECTIVES OF THE INVENTION:
The primary object of the present invention is to overcome the problem stated in the prior art.
Another object of the present invention provides specialized coprocessor featuring a dedicated crypto hardware unit. This unit is designed to efficiently process encrypted data and generate output that adheres to the AMBA bus standards.

SUMMARY OF THE INVENTION:
The present invention provides a coprocessor system, the coprocessor system comprising:
a) a coprocessor system (101) where the coprocessor system (101) is configured to process an encrypted data and generate output;
b) a cryptographic operation (102) unit takes input form the coprocessor system to perform cryptographical operation; and
c) a microcontroller system (103) receives the processed data to ensuring seamless communication and data flow within the microcontroller system;
wherein the coprocessor system (101) features a dedicated crypto hardware unit configured for independent and optimized cryptographic processing without burdening the coprocessor system (101).
In an embodiment, the coprocessor (101) is designed to comply with an advanced microcontroller bus (104) architecture (AMBA) standards, ensuring seamless integration into existing microcontroller systems and facilitating interoperability across a wide array of devices.
In an embodiment, the secure key management mechanism configured to share cryptographic keys (206) are confined exclusively within the coprocessor's domain, mitigating the risk of key exposure to peripheral devices.
In an embodiment, the coprocessor system (101) offers a broad spectrum of cryptographic functions (102), where a user has the flexibility to customize operations, supporting both standard and custom cryptographic processes.
In an embodiment, the coprocessor further streamlines cryptographic processing by exclusively handling encryption (203) and decryption (203) tasks, thereby offloading the primary processor from these computationally intensive operations.
The present invention provides a method of operation of coprocessor system, the method comprising steps of:
a) inputting data transactions originate from an external source external world serving as the initial entry point into the coprocessor system;
b) converting the data with AMBA-compliant transactions and ensuring compatibility and standardization within the microcontroller system.
c) formatting the data according to AMBA standards, is presented to the crypto coprocessor for cryptographic operations; and
d) transmitting the processed data from the crypto unit to the control unit of the coprocessor, completing the transaction cycle.

DETAILED DESCRIPTION OF DRAWINGS:
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of their scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings in which:
Fig. 1: illustrates a block diagram illustrating coprocessor system architecture.
Fig. 2: illustrates a functional block diagram of the system.
Fig. 3: illustrates data encryption and decryption pathway facilitated by the crypto coprocessor.
Fig. 4: illustrates a flowchart of working of the present invention's architecture.
Fig. 5: illustrates the steps for executing proposed coprocessor method.

DETAILED DESCRIPTION:
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
The terms “comprises”, “comprising”, “includes”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.
The present invention relates to a specialized coprocessor featuring a dedicated crypto hardware unit. This unit is designed to efficiently process encrypted data and generate output that adheres to the AMBA bus standards. Unlike the prior art, the present innovation focuses on enhancing processing units with a dedicated crypto hardware unit to optimize cryptographic operations, with particular emphasis on ensuring compatibility with the prevalent AMBA bus architecture. This specialized coprocessor offers improved performance and security, further advancing the field of encrypted data processing within microcontroller systems.
In one embodiment, the present invention discloses a specialized coprocessor designed with a dedicated crypto hardware unit, setting it apart from conventional processing units and optimizing cryptographic operations for efficiency. Notably, this coprocessor exhibits a unique capability to process encrypted data and generate output compliant with Advanced Microcontroller Bus Architecture (AMBA) standards, ensuring seamless integration into microcontroller systems and facilitating interoperability across diverse devices. Unlike prior art, the coprocessor exclusively focuses on cryptographic processing, alleviating the primary processor from encryption/decryption tasks and thereby enhancing overall system performance. A distinctive feature lies in its implementation of a secure key management mechanism, safeguarding shared keys within the coprocessor's domain and preventing exposure to peripheral devices, reinforcing system security. Further enhancing versatility, the present invention accommodates a broad spectrum of cryptographic functions, offering customization options for both standard and custom operations. By streamlining processing without burdening the primary processor with encryption/decryption responsibilities, the coprocessor significantly improves computational efficiency. Overall, these novel aspects collectively position the invention as an innovative solution, effectively balancing efficiency, security, and adaptability for microcontroller systems engaged in cryptographic processing.
Abbreviations
SoC: System on Chip
AMBA: Advanced Micro Bus Architecture
AES: Advanced Encryption System
Figure 1 shows a block diagram illustrating coprocessor system architecture according to an exemplary implementation of the present disclosure/ invention.
The figure shows the block diagram illustrating coprocessor system architecture in the initial exemplary embodiment consists of the cryptographic system-on-a-chip (crypto SoC) and a host comprising a CPU core and memory [105]. The present invention pertains to a specialized coprocessor [101] system designed to enhance the efficiency and security of cryptographic operations [102] within microcontroller [103] systems.
In this embodiment, the coprocessor features a dedicated crypto hardware unit that distinguishes it from traditional processing units [304], allowing for independent and optimized cryptographic processing without burdening the primary processor.
The coprocessor [101] is uniquely designed to comply with Advanced Microcontroller Bus [104] Architecture (AMBA) standards, ensuring seamless integration into existing microcontroller systems and facilitating interoperability across a wide array of devices. This capability allows the coprocessor to process encrypted data and generate output [303] in accordance with industry-standard protocols, enhancing its compatibility and versatility.
In one embodiment, a significant aspect of the invention lies in the implementation of a secure key management mechanism. Shared cryptographic keys [206] are confined exclusively within the coprocessor's domain, mitigating the risk of key exposure to peripheral devices. This mechanism contributes to heightened system security, ensuring the confidentiality and integrity of cryptographic information.
In addition to its secure design, the coprocessor system [101] offers a broad spectrum of cryptographic functions [102]. Users have the flexibility to customize operations, supporting both standard and custom cryptographic processes. This adaptability makes the coprocessor a versatile solution capable of meeting the diverse cryptographic requirements of various applications.
Figure 2 shows a functional block diagram of the system according to an exemplary implementation of the present disclosure/ invention.
The figure represents a functional block diagram of the system, illustrating the data flow between various function blocks. The processor sends data to the crypto block with data transmission occurring through the Advanced Micro Bus Architecture (AMBA) shared via system memory. The cryptographic block explicitly configures the private key.
The coprocessor further streamlines cryptographic processing by exclusively handling encryption [203] and decryption [203] tasks, thereby offloading the primary processor from these computationally intensive operations. This streamlined approach significantly improves overall system efficiency, simplifying the computational load on the primary processor and enhancing the coprocessor's performance.
The custom algorithm can be flashed with a firmware to crypto block with the following procedure. The firmware flashing algorithm via a serial debug line involves establishing a connection to the device, initiating programming mode, and transmitting firmware data in chunks over the serial connection. The device acknowledges each frame, and error-checking ensures data integrity. The firmware is written to the device's flash memory, and verification confirms successful flashing. Exiting programming mode is essential, followed by closing the serial connection. Error handling and logging mechanisms enhance the robustness of the process. The specific commands and sequences may vary, necessitating reference to the device's documentation for accurate implementation.
In conclusion, the specialized coprocessor system presented herein represents an innovative solution for microcontroller systems engaged in cryptographic processing. Its unique design, AMBA compliance, secure key [206] management, customizable operations, and streamlined processing collectively contribute to a highly efficient, secure, and adaptable cryptographic coprocessing environment.
Figure 3 illustrates data encryption and decryption pathway facilitated by the crypto coprocessor according to an exemplary implementation of the present disclosure/ invention.
The figure illustrates data encryption and decryption pathway facilitated by the crypto coprocessor. The outcomes of these processes are then returned to the CPU unit, which initiated the cryptographic procedures.
The coprocessor's operation unfolds in four distinct stages as in figure 3 to facilitate encryption/decryption processes seamlessly. Firstly, [301] it acquires input data from external sources or internal memory, preparing it for cryptographic manipulation. In the second stage, [304] the coprocessor routes the data to one of its cryptographic algorithm cores for processing. These cores execute complex computations swiftly and accurately, transforming the input data according to specified cryptographic algorithms. Subsequently, [302] the processed data is presented to the controller, ensuring seamless communication and data flow within the microcontroller system. Finally, [303] in the fourth stage, the coprocessor transmits the output data to its designated destination, whether external devices, memory, or other components within the system. This systematic approach enhances the performance, security, and functionality of microcontroller systems in cryptographic applications, enabling efficient encryption/decryption processes with timely delivery of processed data.
Figure 4 illustrates a flowchart of working of the present invention's architecture according to an exemplary implementation of the present disclosure/ invention.
The entire setup as shown in figure 4 encompasses four pivotal stages to facilitate seamless data processing and transaction flow.
Firstly, [402] input data transactions originate from the external world, serving as the initial entry point into the system. In the second stage, [403] the data undergoes conversion with AMBA-compliant transactions, ensuring compatibility and standardization within the microcontroller system. As the process advances to the third stage, [404] the data, now formatted according to AMBA standards, is presented to the crypto coprocessor for cryptographic operations. This critical stage leverages the coprocessor's specialized capabilities to execute encryption or decryption tasks swiftly and efficiently. Finally, in the fourth stage, [405] the processed data from the crypto unit is seamlessly transmitted to the control unit of the coprocessor, completing the transaction cycle. This systematic approach ensures smooth data flow and synchronization throughout the setup, optimizing performance, security, and functionality within microcontroller systems.
Figure 5 illustrates the steps for executing proposed coprocessor method according to an exemplary implementation of the present disclosure/ invention.
Figure 5 illustrates the sequential steps involved in the cryptographic operation algorithm within the crypto block. Initially, [501] the algorithm begins with the instruction fetch stage, retrieving the next instruction in the sequence. In the instruction decode phase, [502] the fetched instruction is analyzed to determine the operation to be performed.
If the final data is ready, it is presented to the output interface; otherwise, the algorithm proceeds to the execution stage. Here, [503] the instruction is executed, carrying out the specified cryptographic operation. Following execution, the algorithm enters the memory access stage, [504] accessing data from the coprocessor's memory as required. Finally, [505] in the writeback stage, the results of the cryptographic operation are written back to the memory for storage. The algorithm then loops back to the instruction decode stage, continuing the cycle until all cryptographic operations are completed. This systematic approach ensures efficient and structured processing of cryptographic tasks within the crypto block.
The figure illustrates the steps for executing instructions in the proposed co-processor environment. During this process, data already formatted to comply with AMBA standards within the crypto block, is transacted over the AMBA bus.
In one embodiment, the present invention relates to a system of specialized coprocessor design, in which coprocessor system comprising a specialized coprocessor with a dedicated crypto hardware unit, configured to independently perform cryptographic operations without reliance on the primary processor, thereby optimizing computational efficiency and increased security.
In one embodiment, the cryptographic coprocessor system equipped with a unique capability to process encrypted data and generate output compliant with Advanced Microcontroller Bus Architecture (AMBA) standards, facilitating seamless integration with microcontroller systems and ensuring interoperability across a diverse range of processor cores.
In one embodiment of the present invention, a secure key management mechanism involves a coprocessor system featuring a secure key management mechanism, wherein shared cryptographic keys are confined exclusively within the coprocessor's domain, preventing key exposure to peripheral devices and the main CPU cores enhancing overall system security.
In one embodiment of the present invention, the coprocessor includes a dedicated programming interface, such as a serial port, facilitating seamless communication and configuration with external entities. Crucially, this interface operates autonomously, ensuring no interference with the main system and, importantly, without compromising security. The dedicated programming channel enhances coprocessor functionality by allowing secure and independent communication and configuration, providing external entities with a reliable means to interact with the coprocessor without compromising the overall system's security.
In one embodiment, introducing the capability for customizable cryptographic operations through a coprocessor system. This enhancement allows users to tailor cryptographic functions according to their specific requirements, accommodating both standard and custom cryptographic processes. The method emphasizes adaptability and versatility, providing a secure solution for a diverse range of application needs. Importantly, this customization is facilitated through firmware updates, enabling users to seamlessly incorporate new cryptographic functionalities over time.
Streamlined Cryptographic Processing in which coprocessor system designed to streamline cryptographic operations by exclusively handling encryption and decryption tasks, alleviating the computational load on the primary processor, and significantly improving the overall efficiency and performance of microcontroller systems engaged in cryptographic processing.
The present invention pertains to a specialized coprocessor designed to enhance the efficiency of processing units in performing cryptographic operations. The coprocessor features a dedicated crypto unit capable of executing various cryptographic operations, encompassing both standard and custom functions. The present invention facilitates the rapid computation of sophisticated cryptographic processes, significantly improving overall system performance.
The present invention is distinct from conventional approaches, where the coprocessor ensures heightened security by maintaining a private key exclusively within its domain. This private key is inaccessible to any peripherals in the microcontroller system, enhancing the overall robustness of cryptographic operations. The coprocessor's ability to handle a diverse range of cryptographic functions and maintain the confidentiality of shared keys contributes to the creation of a secure and efficient computing environment.
The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:We Claim:

1. A coprocessor system, the coprocessor system comprising:
a) a coprocessor system (101) where the coprocessor system (101) is configured to process an encrypted data and generate output;
b) a cryptographic operation (102) unit takes input form the coprocessor system to perform cryptohraphic operation; and
c) a microcontroller system (103) receives the processed data to ensuring seamless communication and data flow within the microcontroller system;
wherein the coprocessor system (101) features a dedicated crypto hardware unit configured for independent and optimized cryptographic processing without burdening the coprocessor system (101).
2. The coprocessor system as claimed in claim 1, wherein the coprocessor (101) is designed to comply with an advanced microcontroller bus (104) architecture (AMBA) standards, ensuring seamless integration into existing microcontroller systems and facilitating interoperability across a wide array of devices.
3. The coprocessor system as claimed in claim 1, wherein a secure key management mechanism configured to share cryptographic keys (206) are confined exclusively within the coprocessor's domain, mitigating the risk of key exposure to peripheral devices.
4. The coprocessor system as claimed in claim 1, wherein the coprocessor system (101) offers a broad spectrum of cryptographic functions (102), where a user has the flexibility to customize operations, supporting both standard and custom cryptographic processes.
5. The coprocessor system as claimed in claim 1, wherein the coprocessor further streamlines cryptographic processing by exclusively handling encryption (203) and decryption (203) tasks, thereby offloading the primary processor from these computationally intensive operations.
6. A method of operation of coprocessor system, the method comprising steps of:
a) inputting data transactions originate from an external source external world serving as the initial entry point into the coprocessor system;
b) converting the data with AMBA-compliant 5 transactions and ensuring compatibility and standardization within the microcontroller system.
c) formatting the data according to AMBA standards, is presented to the crypto coprocessor for cryptographic operations; and
d) transmitting the processed data from the crypto unit to the control unit of the coprocessor, completing the transaction cycle.