Abstract: ABSTRACT The present invention is a quantum computing system and method are disclosed. The system comprises a processing unit (102) comprising qubit processors or similar circuitry for implementing quantum operations, along with interfaces (104) facilitating communication of signals or data between different logical layers of the quantum computing system. The system further includes engines (106) comprising a combination of hardware and programming. These engines encompass a circuit reception engine (108) configured to obtain gate teleportation circuits for a predetermined number of qubits, a circuit segmentation engine (110) configured to segment the gate teleportation circuits into multiple sub-circuits based on the number of qubits, a gate teleportation engine (112) configured to perform gate teleportation operations on each of the multiple sub-circuits sequentially, and other engines (114) providing additional functionalities as required. This invention introduces a scalable, modular quantum computing system using sequential gate teleportation with circuit segmentation to optimizes depth, reduces decoherence, and improves fidelity, especially on NISQ-class processors. The figure associated with the abstract is Fig. 1.
DESC:4. DESCRIPTION
Technical Field of the Invention
The present invention pertains to the field of quantum computing, more specifically targeting the optimization of quantum computing method and systems of computation using quantum circuits and teleportation techniques and it addresses challenges associated with circuit segmentation and sequential gate teleportation aimed at enhancing computation efficiency, fault tolerance, and modular deployment on NISQ-era devices.
Background of the Invention
Quantum computing represents a profound advancement over traditional computing by leveraging the principles of quantum mechanics to process information with unprecedented speed and efficiency. This technology promises transformative potential across various applications, from solving complex mathematical problems to conducting simulations beyond the reach of classical computers. However, the field faces significant technological challenges that inhibit its development and broader application.
At the heart of these challenges is the complexity involved in quantum gate operations and the management of qubit entanglement. Quantum computers operate on qubits, or quantum bits, which unlike classical bits that exist distinctly as 0s or 1s, can embody both states simultaneously through quantum superposition. This attribute enables quantum computers to handle numerous computational possibilities concurrently, offering profound computational power. However, manipulating these qubits through quantum gates, which are essential for executing quantum algorithms, introduces substantial complexity.
The existing technological landscape of quantum computing includes various methodologies centered on direct quantum gate applications to physical qubits to execute computational tasks. Such systems often necessitate maintaining qubit coherence long enough to perform meaningful computations—a formidable challenge due to quantum decoherence and noise that destabilize qubit states.
Another prevalent method involves Quantum Error Correction (QEC), which safeguards quantum information against errors from decoherence and other forms of quantum noise. QEC typically requires encoding quantum information into highly entangled states spread across numerous qubits. Though promising, this technique demands an extensive array of physical qubits to protect a relatively smaller number of logical qubits, escalating the complexity and resource demands of quantum computing systems.
Despite advancements, current quantum computing models are beset with significant disadvantages. They necessitate high resource consumption, requiring extensive quantum resources such as numerous qubits and intricate entanglement operations that scale poorly with increased qubit counts and are difficult to maintain. Complex error correction mechanisms inherent in these models add to their bulkiness, curtailing scalability and practical application in commercial and research settings. The operational efficiency of these systems is often compromised by the continual need for observation and adjustments to maintain qubit coherence and perform accurate quantum gate operations.
Quantum computing promises exponential speed-ups but faces limitations such as decoherence, gate infidelity, and constrained qubit connectivity. Measurement-Based Quantum Computing (MBQC) and gate teleportation allow logic execution via measurements on entangled states. However, conventional approaches remain monolithic, resource-heavy, and unsuitable for NISQ devices.
There is a dire need for an invention in the quantum computing field that can address these challenges effectively. The ideal quantum computing system would simplify the process of quantum gate operations and qubit management to make quantum computing more accessible and feasible, operate efficiently with fewer qubits and reduced reliance on extensive entanglement, and improve the performance and output accuracy of quantum computing systems while reducing the overhead associated with error correction and qubit maintenance. These improvements are crucial not only for advancing the field of quantum computing but also for bringing its powerful capabilities to a broader range of applications, from drug discovery and materials science to cryptography and complex system simulations. The development of a quantum computing system that can effectively reduce the complexity and resource requirements while maintaining high operational efficiency could revolutionize the industry and lead to significant technological advancements.
Brief summary of the Invention
The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.
The invention presented herein addresses the inherent complexities and high resource demands associated with current quantum computing models. It introduces a modular hybrid architecture aimed at optimizing quantum operations, minimizing qubit entanglement overhead, and improving scalability and efficiency of quantum systems for practical deployment across various application domains.
The primary object of the invention is to reduce the computational complexity typically involved in quantum computation. By simplifying quantum gate operations and restructuring the architecture of quantum circuits, the invention lowers the barriers to quantum computing adoption in real-world scenarios. A key aspect of this is the reduction in the need for extensive qubit entanglement, thereby decreasing resource requirements and improving system scalability.
Another important objective of the invention is to enhance the operational efficiency of quantum computing systems. This is accomplished by employing a novel framework termed “optimized quantum computing with sequential gate teleportation.
Another important objective of the invention is to segment MBQC-based teleportation circuits into manageable sub-circuits, thereby simplifying complex quantum operations and limiting the scope of entanglement.
Another important objective of the invention is to enable sequential execution of these sub-circuits via gate teleportation techniques, allowing quantum computations to be performed in a staged and controlled manner.
Another important objective of the invention is to integrate adaptive classical feedback mechanisms to dynamically adjust computations based on measurement outcomes, improving accuracy and reliability.
Another important objective of the invention is to facilitate qubit reuse across circuit stages, significantly reducing the overall qubit consumption and supporting more resource-efficient quantum computing.
Another important objective of the invention is to reduce gate depth and minimize the decoherence footprint, thereby enhancing qubit coherence times and overall system stability.
Reduction in gate depth and decoherence footprint, improving coherence and stability.
The invention is particularly characterized by its novel approach to quantum computing, termed "optimized quantum computing with sequential gate teleportation." This method involves obtaining gate teleportation circuits, segmenting these circuits into manageable sub-circuits, and performing sequential gate teleportation operations across these sub-circuits. This process not only simplifies the quantum computing tasks but also enhances the throughput and accuracy of computations.
The applications of this invention are broad and impactful. One of the most notable applications is in the implementation of complex quantum algorithms, such as Grover's algorithm, which is used for database searching and can significantly outperform its classical counterparts in speed and efficiency. The optimized quantum computing model can also be pivotal in drug discovery, where it can be used to simulate molecular interactions at a quantum level much more rapidly than traditional methods. Additionally, the invention has implications for cryptography, providing a more secure and efficient means of encrypting and decrypting data, and for solving optimization problems that are intractable with classical computers.
Together, these features reduce the overhead associated with quantum error correction and enhance the reliability and throughput of quantum computations.
The invention is particularly applicable in high-impact areas such as:
• Quantum algorithm acceleration, including Grover’s algorithm for database search.
• Quantum simulation, especially in fields like drug discovery and materials science.
• Cryptography, enabling more secure quantum communication.
• Optimization problems that are computationally infeasible for classical systems.
The advantages of the invention are multi-fold. Firstly, it reduces the complexity and instability associated with preparing and maintaining entangled qubit states. By modularizing circuits and processing them sequentially, the system reduces potential error propagation and improves coherence retention. Secondly, operational efficiency is significantly enhanced through intelligent circuit segmentation, dynamic feedback, and efficient use of quantum resources. Finally, the architecture allows for a more scalable quantum system design that can accommodate complex computational workloads without a linear increase in hardware demands.
In summary, the invention represents a substantial advancement in quantum computing technology. By combining modular circuit design, teleportation-based execution, adaptive control, and efficient qubit utilization, it provides a practical, efficient, and scalable solution to some of the most pressing limitations of current quantum computing paradigms. This positions the invention as a foundational step toward broader, real-world adoption of quantum computing technologies.
Further objects, features, and advantages of the invention will be readily apparent from the following description of the preferred embodiments thereof, taken in conjunction with the accompanying drawings.
Brief Description of the Drawings
The invention will be further understood from the following detailed description of a preferred embodiment taken in conjunction with an appended drawing, in which:
Figure 1 illustrates schematics of a quantum computing system implementing an optimized quantum computing model, in accordance with an exemplary embodiment of the present invention;
Figure 2 illustrates a gate teleportation circuit, in accordance with an exemplary embodiment of the present invention;
Figures 3 illustrate a segmented gate teleportation circuit, in accordance with an exemplary embodiment of the present invention;
Figure 4 illustrates a method for implementing the optimized quantum computing model, in accordance with an exemplary embodiment of the present invention;
Fig. 5 illustrates the stage-wise optimization of a segmented quantum circuit using gate teleportation techniques, in accordance with an exemplary embodiment of the present invention;
Detailed Description of the Invention
It is to be understood that the present disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways. In addition, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.
The use of “including”, “comprising” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. Further, the use of terms “first”, “second”, and “third”, and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.
According to an exemplary embodiment of the present invention, system and method for optimized quantum computing with sequential gate teleportation is disclosed. The system comprises processing unit, interfaces, engines comprise circuit reception engine, circuit segmentation engine, gate teleportation engine, and other engines.
In accordance with an exemplary embodiment of the present invention, wherein the system comprises a processing unit integrating one or more quantum processors (qubit processors) capable of executing quantum gates, including entangling operations essential for gate teleportation protocols, supported by classical computational resources responsible for control logic, data processing, error correction, and dynamic feedback to the quantum operations.
In accordance with an exemplary embodiment of the present invention, wherein the interfaces facilitate communication across architectural layers, including quantum-classical control interfaces synchronizing gate operations with classical commands, data input/output interfaces handling circuit parameters and measurement results, and inter-module communication interfaces coordinating data flow between engines and processing units.
In accordance with an exemplary embodiment of the present invention, wherein the engine architecture comprises multiple specialized engines designed to modularly perform key functions essential for optimized quantum computation.
In accordance with an exemplary embodiment of the present invention, wherein the circuit reception engine receives, validates, and pre-processes quantum circuits designed for gate teleportation, preparing them for subsequent segmentation and execution.
In accordance with an exemplary embodiment of the present invention, wherein the circuit segmentation engine decomposes large quantum circuits into multiple sub-circuits based on qubit connectivity, gate types, and error models, reducing computational complexity and facilitating more reliable execution on quantum hardware.
In accordance with an exemplary embodiment of the present invention, wherein the gate teleportation engine sequentially performs gate teleportation operations on each segmented sub-circuit using entanglement-assisted protocols such as controlled-Z (CZ) gates single-qubit rotations, and adaptive measurement corrections. By teleporting gates sequentially, the system reduces the need for long coherence times and allows intermediate classical feed-forward control, thereby enhancing gate fidelity and reducing the effective circuit depth.
In accordance with an exemplary embodiment of the present invention, wherein supporting engines manage auxiliary functions such as real-time error correction, resource scheduling, qubit state monitoring, and system diagnostics. These engines enable dynamic adaptation of the quantum computing process to environmental noise and hardware constraints, ensuring robustness and scalability.
In accordance with an exemplary embodiment of the present invention, wherein the system operates via a pipeline method wherein quantum circuits are received, segmented, and sequentially executed with classical feedback loops, enabling practical implementation of large quantum algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices.
In accordance with an exemplary embodiment of the present invention, wherein the invention reduces qubit resource overhead and mitigates decoherence by limiting quantum gate depth through sequential teleportation and intermediate classical processing.
In accordance with an exemplary embodiment of the present invention, wherein the system provides modularity and scalability, adapting to various quantum hardware platforms and supporting a hybrid quantum-classical computational framework optimized for performance and reliability.
Now referring to Figs, Figure 1 illustrates a quantum computing system (100) for implementing the optimized quantum computing model, in accordance with an example of the present subject matter. The system 100 may include a processing unit 102, interfaces 104 and engines 106. The processing unit 102 may include qubit processors or similar circuitry which may be implementing a quantum qubit processor. The interfaces 104 enable communication of the signals or data between different logical layers constituting the quantum computing system 100. It may be noted that the system 100 may include further supporting infrastructure, hardware and accompanying equipment and classical processing machines, collectively functioning for implementing the quantum computing system 100. These are also not depicted for sake of brevity and for ease in explanation.
The engines 106 may be implemented as a combination of hardware and programming, for example, programmable instructions to implement a variety of functionalities. In examples described herein, such combinations of hardware and programming may be implemented in several different ways. For example, the programming for the engines 106 may be executable instructions. In an example, the engines 106 may include a processing resource, for example, either a single processor or a combination of multiple processors, to execute one or more instructions. In the present examples, the non-transitory machine-readable storage medium may store instructions, that when executed by the processing resource, implement engines 106. In other examples, the engines 106 may be implemented as electronic circuitry.
The engine 106 may further include a circuit reception engine 108, a circuit segmentation engine 110, a gate teleportation engine 112, and other engines 114.
In operation, the circuit reception engine 108 may obtain a gate teleportation circuit for a particular number of qubits. In an example, the gate 8 teleportation engine may be prepared based on Measurement Based Quantum Computing (MBQC) model. The gate teleportation circuit is a circuit that is utilized for transferring an unknown quantum state of a qubit to another qubit. For instance, in an example, an unknown qubit (|?? = a|0? 5 + ß|1?) may be encoded in a line with another qubit in |+? state. These two qubits may be connected to each other through Controller Z (CZ) gates. The final state that is obtained after the operation of the CZ gate is,
| ?'? = a|0+? + ß|1-? (1)
In equation 1, measuring the first qubit in the M? basis, results the unknown qubit in the state | ? ?f = Xs J-?| ??. In the example, the gate teleportation circuit for the particular number of qubits may be prepared in a similar manner.
Subsequently, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits. The circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits based on the number of qubits in the gate teleportation circuit. For instance, the circuit segmentation engine 110 may determine the number of sub-circuits segmented from the gate teleportation circuit based on the number of qubits in the gate teleportation circuit.
In an example, if the number of qubits included in the gate teleportation circuit is equal to ‘2n’, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits, where each of the multiple sub-circuits has ‘n’ qubits. For instance, if the number of qubits included in the gate teleportation circuit is ‘16’, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits, with each of the multiple sub-circuit having ‘4’ qubits. Accordingly, if the number of qubits included in the gate teleportation circuit is ‘16’, the gate teleportation engine 110 may segment the gate teleportation circuit into ‘4’ sub-circuits.
In another example, if the number of qubits included in the gate teleportation circuit is greater than ‘2n’ but less than 2n+1, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits, where each of the multiple sub-circuits has ‘n+1’ qubits. For instance, if the number of qubits included in the gate teleportation circuit is ‘12’, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits, with each of the multiple sub-circuits having ‘4’ qubits (since 2 3<12<24). Accordingly, if the number of qubits included in the gate teleportation circuit is ‘16’, the gate teleportation engine 110 may segment the gate teleportation circuit into ‘3’ sub-circuits.
The gate teleportation engine 112 may then perform a gate teleportation operation on a first sub-circuit of the five sub-circuits and obtain a first output. Thereafter, the gate teleportation engine 112 may input the first output into a second sub-circuit of the five sub-circuits. The gate teleportation engine 112 may subsequently perform another gate teleportation operation on the second sub-circuit based on the input received from the first sub-circuit, i.e., first output, and the qubits included in the second sub-circuit. The gate teleportation engine 112 may similarly perform the gate teleportation operations on rest of the sub-circuits till all the sub-circuits obtained from the segmentation of the gate teleportation circuit are traversed. The gate teleportation engine 112 may then measure the final output from the last teleportation circuit.
In an example implementation, the optimized quantum computing model may be utilized for implementation of Grover’s algorithm. The Grover’s Algorithm is a quantum algorithm that is utilized for performing a search on an unstructured database. In other words, the Grover’s algorithm may be utilized while a search is to be conducted for a particular item in a list of ‘N’ items placed in a scattered manner. To find the particular item in the list, most of the classical computing algorithms compare the particular item with every item in the list one after the other, which requires at least ‘N/2’ comparisons to find the particular item in the list. In worst case scenarios, the classical computing algorithms may end up comparing the 10 particular item with all the ‘N’ items in the list. On the contrary, utilizing the Grover’s Algorithm on a quantum computer, the particular item may be found in the list of ‘N’ items in roughly ‘vN’ comparisons.
In an example of the present subject matter, the Grover’s algorithm may be implemented for ‘12’ qubits at a time. In operation, the circuit reception engine 108 may obtain a gate teleportation circuit for the ‘12’ qubits, the gate teleportation circuit for the ‘12’ qubits being prepared based on the MBQC model.
An exemplary gate teleportation circuit obtained by the circuit reception engine 108 for ‘12’ qubits is illustrated in figure 2. The ‘12’ qubits may include q00, q01, q02, q03, q04, q05, q06, q07, q08, q09, q010, and q011. In an example, each of the ‘12’ qubits may be operated upon by various quantum gates and a basis state for each qubit may be measured. In said example, the basis states for each of the qubits may then be superimposed to obtain a final quantum state, where the quantum state may represent a solution to a quantum algorithm being operated upon by a quantum computing system.
Subsequently, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits. As already described, the circuit segmentation engine 110 may segment the gate teleportation circuit into multiple sub-circuits based on in the number of qubits included in the gate teleportation circuit. Accordingly, the circuit segmentation engine 110 may segment the gate teleportation circuit into ‘3’ sub-circuits, with each sub-circuit having 4 qubits.
The gate teleportation engine 112 may then perform a gate teleportation operation on a first sub-circuit of the ‘3’ sub-circuits and obtain a first output. In an example, the ‘4’ qubits included in the first sub-circuit may be q00, q01, q02, and q03, where the qubits q00 and q02 may be input qubits and q01 and q03 may be output qubits. In said example, to perform the gate teleportation operation on the first sub-circuit, the gate teleportation engine 112 may begin with qubits q00, q01, q02, and q03 in the state |0>, thereby obtaining the state |?0> = |0>|0>|0>|0>. Specifically, the gate teleportation engine 112 may begin with an empty circuit with all qubits initialized in the state ‘0’. A state vector corresponding to the abovementioned state of qubits may be described by an array shown below:
State vector = [1 0 0 0 …….0 0 0]
Thereafter, the gate teleportation engine 112 may apply Hadamard operation on all the ‘4’ qubits to take the qubits to an equal superposition of all states in computational basis. The initial superposition of all the states so obtained may be described as follows: |+> |+> |+> |+> = 1 4 [(|0 > +|1 >) * (|0 > +|1 >) * (|0 > +|1 >) * 10 (|0 > +|1 >)]
A state vector corresponding to the above-mentioned state of qubits may be described by an array shown below:
Thereafter, the gate teleportation engine (112) may apply CZ operations between the qubits q00 and q01. This, in turn, may lead to action of Z gate on the |1>|0>, |1>|1> part of the state which leads to the -ve sign on amplitude corresponding to |1>|1>. The state so obtained may be described as follows:
1 /4 [(|0 > |0 > +|0 > |1 > +|1 > |0 > -|1 > |1 >) * (|0 > |0 > +|0 > |1 > 20 +|1 > |0 > +|1 > |1 >)]
A state vector corresponding to the above-mentioned state of qubits may be described by an array shown below:
State vector= [¼ ¼ ¼ -¼ ¼ ¼ ¼ -¼ ¼ ¼ ¼]
Subsequently, the gate teleportation engine (112) may apply CZ operations between the input qubits and output qubits. This may lead to addition of a -ve sign to the terms corresponding to the |1>|1>. Thus, an additional - ve sign may be seen added to the terms having q0q2 in |1>1> 12 state. Similarly, an additional - ve sign may also be added to the terms having q1q3 in |1>1> state. A state vector corresponding to the above mentioned state of qubits may be described by an array shown below:
State vector= [ ¼ ¼ ¼ -¼ ¼ ¼ ¼ - ¼ ¼ ¼ ¼ ]
The gate teleportation engine (112) may then apply a -pi/2 rotation and Hadamard operator on the input qubits. This, in turn, may lead to the qubits going into the state described by array provided below:
State vector= [ ¼(1+i) 0 0 ¼(-1+i) 0 ¼(1+i) ¼(-1+i) 0 0 ¼(-1+i) 0 ¼(1+i) ¼(-1+i) 0 0 ¼(1+i) ]
The gate teleportation engine (112) may then perform the measurement of the input qubits q00 and q02 and apply corresponding corrections on the output qubits to receive a final state vector provided below:
State vector= [1/2(1+i) 0 0 0 0 0 0 0 0 0 0 0 1/2(-1+i) 0 0 0 ]
The gate teleportation engine (112) may then decompose the above mentioned state vector to get the following state:
|???????????? > = [(|0 > |0 >) * 1 2 ({1 + ??}|00 > +{-1 + ??}|11 >) (2)
The gate teleportation engine (112) may then input the first output, i.e., equation 2, into a second sub-circuit of the ‘3’ sub-circuits. The gate teleportation engine (112) may then perform another gate teleportation operation on the second sub-circuit based on the input received from the first sub-circuit, i.e., first output, and the qubits included in the second subcircuit, i.e., q04, q05, q06, and q07.
Fig. 3 illustrates the gate teleportation engine (112) may similarly perform the gate teleportation operations on rest of the sub-circuits till all the sub-circuits obtained from the segmentation of the gate teleportation circuit are traversed. In an example, the gate teleportation engine (112) performs the gate teleportation operation on the rest of the subcircuits in a manner similar to the first sub-circuit. Accordingly, the details related to the manner in which the gate teleportation engine (112) performs gate teleportation operation on the rest of the sub-circuits is not described herein for the sake of brevity. The gate teleportation engine (112) may subsequently measure the final output from the last teleportation circuit.
Segmenting the gate teleportation circuit into multiple sub-circuits and performing the gate teleportation operations on the multiple sub-circuits sequentially reduces the computational complexity involved in preparation of the entangled state of all the involved qubits, thereby enhancing the overall operational efficiency of the quantum computing system employing the optimized quantum computing model. Further, as output for each of the multiple sub-circuits is fed into forthcoming sub-circuits as soon as gate teleportation operation is complete for each of the multiple sub-circuits, duration for which qubits are to be maintained in their states is also reduced, thereby reducing the consumption of computational resources of the quantum computing system. Moreover, the sequential gate teleportation operation entails only a subset of total qubits involved in computation to be used at once, thereby allowing reusability of qubits.
Fig. 4 illustrates a method for implementing the optimized quantum computing model, in accordance with an example of the present subject matter. Although the method (400) may be implemented in a variety of devices, but for the ease of explanation, the description of the method (400) is provided in reference to the above-described quantum computing system 100. The order in which the method 400 is described is not intended to be construed as a limitation, and any number of the described method blocks may be combined in any order to implement the method (400), or an alternative method. It may be understood that blocks of the method (400) may be performed in the quantum computing system (100). The blocks of the method (400) may be executed based on instructions stored in a non-transitory computer-readable medium, as will be readily understood.
At block (402), a gate teleportation circuit for a predetermined number of qubits may be obtained. In an example, the obtained gate teleportation circuit may be prepared based on the MBQC model. In said example, the gate teleportation circuit may be received by a circuit reception engine (108) of the quantum computing system (100).
At block (404), the gate teleportation circuit may be segmented into multiple sub-circuits. In an example, the gate teleportation circuit may be segmented into multiple sub-circuits based on the number of qubits included in the gate teleportation circuit. For instance, the number of sub-circuits segmented from the gate teleportation circuit may be determined based on the number of qubits in the gate teleportation circuit. In an example, if the number of qubits included in the gate teleportation circuit is equal to ‘2n ’, the gate teleportation circuit may be segmented into multiple sub-circuits, where each of the multiple sub-circuits has ‘n’ qubits. In another example, if the number of qubits included in the gate teleportation circuit is greater than ‘2n ’ but less than ‘2n+1’, the gate teleportation circuit may be segmented into multiple sub-circuits, where each of the multiple sub-circuits has ‘n+1’ qubits. Further, in said example, the gate teleportation circuit may be segmented into multiple sub-circuits by a circuit segmentation engine (110) of the quantum computing system 100.
At block (406), a gate teleportation operation may be performed on each of the multiple sub-circuits till all the sub-circuits obtained from the segmentation of the gate teleportation circuit are traversed. In an example, the gate teleportation operation for each of the multiple sub-circuits may be performed based on an output of a gate teleportation operation performed on a previous sub-circuit and the qubits included in each of the multiple sub-circuits. In an example, the gate teleportation operation may be performed on each of the multiple sub-circuits by the gate teleportation engine (112).
At block 408, an output of the gate teleportation operation performed on the last sub-circuit from the multiple sub-circuits may be measured. In an example, the output of the gate teleportation operation performed on the last sub-circuit may be measured by the other engine (114).
Although examples of the present subject matter have been described in language specific to methods and/or structural features, it is to be understood that the present subject matter is not limited to the specific methods or features described. Rather, the methods and specific features are disclosed and explained as examples of the present subject matter.
Fig. 5 illustrates the stage-wise optimization of a segmented quantum circuit using gate teleportation techniques. The figure consists of three rows representing:
Decoherence Utilization per Stage (Top row): Each vertical bar corresponds to a circuit execution stage (Stage 1 through Stage 4). The darkest region at the bottom of each bar indicates the level of decoherence exposure. As stages progress from left to right, the dark regions decrease in size, showing improved coherence efficiency due to reduced active gate windows through teleportation and segmentation.
Gate Density per Segment (Middle row): These bars depict the concentration of quantum gates per segment. Darker segments represent higher gate density, while lighter regions show sparser operation counts. The variation across stages reflects the adaptive nature of the segmentation algorithm, which clusters gates based on entanglement, hardware topology, and logical dependencies.
Execution Time Comparison (Bottom row): A horizontal gradient bar illustrates the relative execution time for each stage. The gradient transitions from dark (Stage 1) to light (Stage 4), signifying that execution time reduces in later stages. This confirms the effectiveness of the proposed segmentation and teleportation architecture in accelerating circuit completion and minimizing decoherence exposure.
Supporting Evidence for Optimized Quantum Computing System with Segmentation:
Segmentation Performance Metrics:
Segment ID Decoherence Usage (%) Gate Density (gates/qubit) Execution Time (µs)
Segment 1 88.5 4.2 6.1
Segment 2 65.2 3.8 5.4
Segment 3 58.3 3.1 4.9
Segment 4 54.7 2.9 4.6
Hardware Implementation Variants: The proposed system is compatible with multiple quantum hardware platforms including superconducting qubits (such as IBM Q and Rigetti), trapped ion systems like IonQ, and photonic quantum processors exemplified by Xanadu. The teleportation controller dynamically recompiles circuits tailored to each architecture’s native gate sets and decoherence characteristics. This segmentation approach also respects physical qubit topology constraints by using connectivity matrices and pulse calibration files for precise mapping.
Mathematical Formulation of Teleportation Logic: The teleportation operation is mathematically formalized as the matrix product
T= (I ? M ?) ·CZ· (H ? I)
Where
• M ? = measurement in rotated basis
• CZ = Controlled-Z gate
• H = Hadamard gate
Classical feedforward corrections: Cout=M ??Pauli(X/Z), segment entropy Si tracks entanglement between segments to monitor entanglement between circuit segments, the system calculates segment entropy Si via partial traces over subsystem partitions, enabling fine-grained control of quantum correlations.
Segmentation Algorithm Pseudocode: The segmentation process begins by taking an MBQC circuit and its qubit connectivity graph, then iteratively clusters qubits into groups limited by a maximum size nnn. At each iteration, a cluster of nnn qubits with minimal cross-edges is identified and extracted as a segment SiS_iSi. The corresponding gates are removed from the original circuit, and the segment is appended to the set of segments SSS. This process repeats until all circuit gates are assigned to segments, thereby producing a segmented circuit optimized for reduced decoherence and computational complexity.
Fault Tolerance and Error Budget Analysis: Segmentation localizes error to smaller units. If the logical error rate per segment is e_L = e^d, where e is physical gate error and d is segment depth, then global failure is bound by max(e_Li). Decoherence is minimized by limiting entanglement lifespan per segment. Pauli frame tracking avoids re-applying physical gates.
Extended Simulation Data: The system shows clear performance gains across well-known quantum algorithms. Grover’s algorithm baseline success improves from 84.7% to 95.4% with segmentation. Variational Quantum Eigen solver (VQE) simulations yield ground-state energies accurate within 0.002 Hartree. For Quantum Approximate Optimization Algorithm (QAOA), Max Cut solution optimality increases by 12.8% compared to non-segmented circuits. These results are validated both in simulation environments (Aer Simulator) and on 5-qubit IBM quantum processors, confirming reliability and reduced runtime.
QASM Input/Output Transformation Example: Before segmentation, the quantum assembly instructions include direct controlled operations such as h q[0]; cx q[0], q[1]; measure q[0] -> c[0]. After segmentation, the instructions are restructured to separate measurement and conditional operations:
h q[0]; measure q[0] -> c[0]; if (c[0]==1) x q[1]; measure q[1] -> c[1];. This transformation allows for adaptive correction based on measurement outcomes, reducing error propagation.
Pauli Frame Tracking: Logical corrections to qubits are tracked in a Pauli frame register that defers physical gate execution. Frame updates occur as classical XOR operations based on measurement results, expressed as
F_ new = F_ Prev ? m ? correction _ map.
This approach reduces hardware overhead and mitigates cumulative gate errors by applying corrections virtually.
Adaptive Scheduling: The system adjusts segment allocation dynamically in real time using noise profile feedback from qubit calibration metadata. This adaptive segmentation splits circuits at decoherence hotspots, optimizing the scheduling of quantum operations to minimize noise impact and improve fidelity.
Scalability Projection: Simulations predict that a 100-qubit quantum processor segmented into 20 groups of 5 qubits each can achieve a fourfold increase in fidelity. Furthermore, the quantum volume a measure of usable quantum computational power scales approximately linearly under optimized teleportation scheduling, supporting the system’s viability for larger-scale quantum computing applications.
Technical Implementation Details:
Hardware Specifics: The system is designed to be compatible with current Noisy Intermediate-Scale Quantum (NISQ) processors across multiple architectures. Supported hardware includes superconducting quantum processing units (QPUs) from IBM and Rigetti, trapped ion systems such as those by IonQ, and photonic quantum processors like Xanadu Borealis. This broad hardware support ensures adaptability across various quantum computing platforms.
Qubit Technology Assumptions: The design assumes qubits with coherence times (T1 and T2) in the range of 100 to 200 microseconds. Single-qubit gate fidelities exceed 99.8%, and two-qubit gate fidelities are approximately 98%, reflecting current achievable hardware performance benchmarks within NISQ systems.
Software Layer: The software stack uses Python and C++ as primary programming languages. It leverages established quantum software frameworks including Qiskit (developed by IBM) and Cirq (developed by Google). Simulations and benchmarking rely on the IBM QASM simulator and Aer Simulator, which facilitate teleportation success rate evaluation and gate depth comparisons. The segmentation logic is implemented as a runtime module integrated into the Qiskit transpiler’s pass infrastructure, allowing seamless circuit transformation during compilation.
Simulator vs Real-Hardware: Testing and validation are performed both on Aer Simulator with 5- and 15-qubit configurations and on real IBM quantum devices. Calibrated gate maps ensure realistic execution on IBM Q hardware, while a runtime toggle allows switching between simulation and live hardware backends to flexibly adapt execution modes.
Gate Teleportation Circuit: A minimal annotated example shows the gate teleportation sequence involving two qubits and classical registers:
q[0]: --H----¦-------------M?---->
¦ ¦
q[1]: -------¦----Rx(?)----Rz(?)-+---M?---->
¦ ¦
c[0]: <----------classical feed-forward---------->
Gates used: H, CZ, Rx(?), Rz(?), M?
Qubits involved: 2 physical + classical register
Measurement Correction: Conditional Pauli X/Z based on M? outcomes
Segmentation Logic: Circuit segmentation optimization goes beyond simply dividing by qubit count. It accounts for the entanglement graph density, hardware coupling maps, and topology constraints to minimize decoherence windows per segment. Additionally, a qubit reuse index (QRX) is used to track and optimize qubit assignments across segments. The algorithm employs greedy heuristics that penalize high-weight cut-edges and favor clusterable operations. It further leverages qubit T1 and T2 profiles to avoid placing fragile qubits at segment boundaries, thereby enhancing fault tolerance.
Resource Analysis and Efficiency: Comparing traditional circuits with the segmented teleportation approach reveals significant improvements:
Metric Traditional Circuit Segmented Teleportation
Circuit Depth 152 59 (?61%)
Decoherence Overhead High Low (?42%)
Memory Usage High Moderate (?38%)
Success Probability 84.7% 95.4%
Measurement and Correction Details: Measurement outcomes (M?) are stored in classical registers. Conditional Pauli X/Z corrections are applied via Pauli frame tracking but deferred until the end of each segment to reduce gate noise and decoherence propagation. This logic is explicitly represented in QASM code with conditional statements such as:
measure q[0] -> c[0];
if (c[0] == 1) x q[1];
The software defers physical corrections, performing frame updates classically to maintain circuit fidelity.
Example Implementation: Grover’s Algorithm: The system is demonstrated on Grover’s search algorithm where:
• Initial state: |0?^n with H gates applied
• Oracle in Segment 1, Diffusion split across Segment 2 and 3
• 3 iterations of search with teleportation between iterations
Performance Comparison:
Metric Traditional SGT-Based
Success Probability 84.7% 95.4%
Gate Depth 152 59
Memory Usage High Reduced
Classical Overhead None Minimal
Applications Beyond Grover:
Shor’s Algorithm: Modular exponentiation performed through segmented quantum registers. Logical control allows pausing between segments based on carry propagation.
VQE (Variational Quantum Eigen solver): Commuting terms from molecular Hamiltonians are mapped to disjoint segments, reducing gate conflict and decoherence.
QAOA (Max Cut/TSP): Mixer and cost layers alternately handled by sequential teleportation, enabling deeper layer support even on 5-7 qubit devices.
Industrial Applicability: Targeted platforms include Software-as-a-Service (SaaS) quantum simulators that accept user-uploaded MBQC or QASM circuits and perform segmentation and teleportation processing in the cloud. The system is also deployable on NISQ devices such as IBM Q via runtime execution scripts and holds potential for edge integration in quantum-HPC hybrid environments.
Commercial Potential: This architecture is ideal for startups focusing on quantum acceleration, HPC co-processing, and quantum algorithm SaaS providers. The design has been demonstrated on pilot testbeds with quantum circuit-as-a-service interfaces, underscoring its readiness for commercial adoption and scalable quantum computing services.
,CLAIMS:5. CLAIMS
We Claim
1. A quantum computing system comprising:
a processing unit (102) comprising qubit processors or similar circuitry for implementing quantum operations;
Characterized by,
interfaces (104) facilitating communication of signals or data between different logical layers of the quantum computing system;
engines (106) comprising a combination of hardware and programming, the engines including:
a circuit reception engine (108) configured to obtain gate teleportation circuits for a predetermined number of qubits;
a circuit segmentation engine (110) configured to segment the gate teleportation circuits into multiple sub-circuits based on the number of qubits;
a gate teleportation engine (112) configured to perform gate teleportation operations on each of the multiple sub-circuits sequentially, and adaptively adjust teleportation parameters based on real-time feedback;
other engines (114) providing additional functionalities as required, including error mitigation and system calibration;
wherein, the quantum computing system is operable to implement an optimized quantum computing model for applications such as Grover's algorithm.
2. The quantum computing system as claimed in claim 1, wherein the processing unit (102) further includes classical processing machines and accompanying equipment to support the implementation of quantum computation.
3. The quantum computing system as claimed in claim 1, wherein the gate teleportation engine (112) utilizes Measurement Based Quantum Computing (MBQC) principles to perform gate teleportation operations.
4. The quantum computing system as claimed in claim 1, wherein the circuit segmentation engine (110) segments gate teleportation circuits into sub-circuits based on whether the total qubit count is a power of 2 or not.
5. The quantum computing system as claimed in claim 1, wherein the gate teleportation engine (112) performs gate teleportation operations using controlled-Z (CZ) gates to transfer an unknown quantum state between qubits.
6. The quantum computing system as claimed in claim 1, wherein the interfaces (104) facilitate communication of signals or data between different logical layers constituting the quantum computing system, wherein said logical layers are not depicted for the sake of brevity.
7. The quantum computing system as claimed in claim 1, wherein the engines (106) further comprise a variety of functionalities implemented through programmable instructions executed by a processing resource, said instructions being stored in a non-transitory machine-readable storage medium.
8. The quantum computing system as claimed in claim 1, wherein the gate teleportation engine (112) performs gate teleportation operations sequentially on each sub-circuit obtained from the segmentation of gate teleportation circuits until all sub-circuits are traversed, and subsequently measures the final output.
9. A method for implementing an optimized quantum computing model, comprising:
Obtaining a gate teleportation circuit for a predetermined number of qubits, said gate teleportation circuit being prepared based on the Measurement Based Quantum Computing (MBQC) model;
segmenting said gate teleportation circuit into multiple sub-circuits based on the number of qubits included in the gate teleportation circuit;
performing gate teleportation operations sequentially on each sub-circuit obtained from the segmentation of gate teleportation circuits;
measuring the final output of the gate teleportation operation performed on the last sub-circuit.
10. The method as claimed in claim 9, wherein segmenting the gate teleportation circuit into multiple sub-circuits reduces computational complexity and enhances operational efficiency of the quantum computing system.
6. DATE AND SIGNATURE
Dated this on 10th day of June 2025
Signature
(Mr. Srinivas Maddipati)
(IN/PA 3124)
Agent for applicant
| # | Name | Date |
|---|---|---|
| 1 | 202441044830-PROVISIONAL SPECIFICATION [10-06-2024(online)].pdf | 2024-06-10 |
| 2 | 202441044830-FORM FOR STARTUP [10-06-2024(online)].pdf | 2024-06-10 |
| 3 | 202441044830-FORM FOR SMALL ENTITY(FORM-28) [10-06-2024(online)].pdf | 2024-06-10 |
| 4 | 202441044830-FORM 1 [10-06-2024(online)].pdf | 2024-06-10 |
| 5 | 202441044830-EVIDENCE FOR REGISTRATION UNDER SSI(FORM-28) [10-06-2024(online)].pdf | 2024-06-10 |
| 6 | 202441044830-EVIDENCE FOR REGISTRATION UNDER SSI [10-06-2024(online)].pdf | 2024-06-10 |
| 7 | 202441044830-DRAWINGS [10-06-2024(online)].pdf | 2024-06-10 |
| 8 | 202441044830-Proof of Right [06-07-2024(online)].pdf | 2024-07-06 |
| 9 | 202441044830-FORM-26 [06-07-2024(online)].pdf | 2024-07-06 |
| 10 | 202441044830-FORM 3 [06-07-2024(online)].pdf | 2024-07-06 |
| 11 | 202441044830-ENDORSEMENT BY INVENTORS [06-07-2024(online)].pdf | 2024-07-06 |
| 12 | 202441044830-RELEVANT DOCUMENTS [16-04-2025(online)].pdf | 2025-04-16 |
| 13 | 202441044830-POA [16-04-2025(online)].pdf | 2025-04-16 |
| 14 | 202441044830-FORM FOR STARTUP [16-04-2025(online)].pdf | 2025-04-16 |
| 15 | 202441044830-FORM 13 [16-04-2025(online)].pdf | 2025-04-16 |
| 16 | 202441044830-EVIDENCE FOR REGISTRATION UNDER SSI [16-04-2025(online)].pdf | 2025-04-16 |
| 17 | 202441044830-DRAWING [10-06-2025(online)].pdf | 2025-06-10 |
| 18 | 202441044830-DRAWING [10-06-2025(online)]-1.pdf | 2025-06-10 |
| 19 | 202441044830-COMPLETE SPECIFICATION [10-06-2025(online)].pdf | 2025-06-10 |
| 20 | 202441044830-COMPLETE SPECIFICATION [10-06-2025(online)]-1.pdf | 2025-06-10 |
| 21 | 202441044830-Proof of Right [12-06-2025(online)].pdf | 2025-06-12 |
| 22 | 202441044830-FORM-5 [12-06-2025(online)].pdf | 2025-06-12 |
| 23 | 202441044830-FORM-9 [01-07-2025(online)].pdf | 2025-07-01 |
| 24 | 202441044830-FORM 18 [01-07-2025(online)].pdf | 2025-07-01 |
| 25 | 202441044830-STARTUP [20-09-2025(online)].pdf | 2025-09-20 |
| 26 | 202441044830-FORM28 [20-09-2025(online)].pdf | 2025-09-20 |
| 27 | 202441044830-FORM 18A [20-09-2025(online)].pdf | 2025-09-20 |