DESC:PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which it is to be performed.
CROSS REFERENCE
This Application is based upon and derives the benefit of Indian Provisional Application Number 202441045170 filed on June 11, 2024, the contents of which are incorporated herein by reference.
FIELD OF INVENTION
[0001] The present disclosure generally relates to doping of semiconductor materials, and more particularly relates to a semiconductor device fabricated using n-type doping of a gallium oxide (Ga2O3) semiconductor material and a method thereof.
BACKGROUND
[0002] Generally, a semiconductor device plays a crucial role in modern electronic and power systems, which enables a wide range of applications. The wide range of applications includes power conversion, high-frequency switching, radio frequency (RF) electronics, and optoelectronic devices. Traditionally, Silicon (Si) has been a material of choice for various semiconductor applications due to a mature fabrication technology and cost-effectiveness of Silicon. However, with increasing demands for higher power density, thermal stability, and efficiency, alternative materials with superior intrinsic properties are being explored.
[0003] Additionally, a wide bandgap semiconductor material such as a Silicon Carbide (SiC) and a Gallium Nitride (GaN) have been widely adopted in high-power and high-frequency applications due to a higher breakdown voltage, a faster switching speed, and a better thermal conductivity as compared to silicon. Nonetheless, even the wide bandgap semiconductor material has limitations in an ultra-high voltage application and a harsh environment.
[0004] Recently, a gallium oxide (Ga2O3), particularly in monoclinic ß-phase, has emerged as an ultra-wide band gap semiconductor material. Further, the gallium oxide has a bandgap, approximately lying in the range of 4.8 electron-volt (eV) to 4.9 electron-volt (eV), which is significantly higher than that of the Silicon Carbide (SiC), which is around 3.3 eV and the Gallium Nitride (GaN), which is around 3.4 eV. The ultra-wide band gap of the gallium oxide enables fabrication of devices with extremely high breakdown voltages. Thus, the wide bandgap of the gallium Oxide is highly suitable for power electronics, especially for applications exceeding the bandgap of 1.2 kilovolt (kV). In addition, the gallium oxide offers numerous advantages, including, a low-cost melt growth method, which allows production of a large-area native substrate.
[0005] Although, the gallium oxide has potential, however, the development of a high-performance gallium oxide (Ga2O3)-based semiconductor device faces numerous challenges. One key challenge is control and implementation of a negative (n)-type doping in the gallium oxide. Since, the gallium oxide is inherently a negative (n)-type material due to presence of native defects, such as oxygen vacancies. Therefore, an intentional doping with donor species such as a tin (Sn), a silicon (Si) and a germanium (Ge) is required to achieve the desired electrical properties such as a higher carrier concentration and an improved conductivity. However, achieving a uniform and a controllable doping while maintaining a material quality is a complex process, especially during a bulk crystal growth and a thin-film deposition.
[0006] Moreover, a realization of functional devices, such as, a Schottky Barrier Diode (SBD), a Field-Effect Transistors (FET), and a Junction Barrier Schottky (JBS) diode based on the gallium oxide, necessitates precise control over a plurality of doping profiles, a junction formation, and a thermal stability. Further, the thermal conductivity of the gallium oxide is relatively low, which adds further complexity in a thermal management and a device packaging.
[0007] Additionally, conventional methods of doping the gallium oxide and fabricating semiconductor devices suffer from various issues, such as, a non-uniform doping, a limited scalability, a poor crystal quality, and a low carrier mobility. Further, a reproducibility and an industrial compatibility of the conventional methods remain areas of active research and development.
[0008] Generally, a doping is an intentional addition of an impurity into an intrinsic, which is pure, semiconductor for a purpose of modulating electrical properties of the semiconductor. During the creation of the semiconductor device, selective area doping is a crucial method for placing dopant atoms precisely where the dopant atoms are needed within a semiconductor material. Unlike, a uniform doping, which introduces dopants throughout the semiconductor, the selective area doping includes doping in predefined areas of the semiconductor material.
[0009] Additionally, an ultra-wide band gap semiconductor material may be used for high-power applications. The ultra-wide band gap semiconductor material enables power transistors and diodes, which have a very high voltage handling capability due to a high critical electric field. However, certain device topologies for the high-power applications require a high n-type doped layer at a top surface of the ultra-wide band gap semiconductor material. Furthermore, the high n-type doped layer at the top surface of the ultra-wide band gap semiconductor material is required to form an appropriate Ohmic contact with a reduced contact resistance. Furthermore, the selective area doping is essential to isolate a source region and a drain region in, for example, a Field Effect Transistor (FET) from a drift region, such as, a lightly doped region.
[0010] Conventionally, an ion implantation technique is used to obtain a thin negative (n)-type doped layer at a top surface of the semiconductor material. Irrespective of controllability of the thin n-type doped layer in terms of depth of the doping, the ion implantation technique requires precise optimization of energy and a dose of dopant ions to achieve a desired doping profile. Further, the selective area doping using the ion implantation technique requires activation in which a high-temperature treatment allows the dopant atoms to move into desired positions respectively. Furthermore, the dopant atoms become electrically active, influencing the conductivity of the semiconductor material. Furthermore, the ion implantation technique requires a damage anneal step involving a high-temperature treatment. Furthermore, the high temperature treatment helps to repair the damage in the crystal structure of the semiconductor material due to ion implantation and to restore the properties of the semiconductor material.
[0011] Consequently, the ion implantation technique introduces significant crystal damage to the host material, which necessitates a damage annealing step. Further, the damage annealing step repairs crystalline defects in the semiconductor material and restore semiconductor properties. Furthermore, a post-implantation thermal treatment may complicate a process flow due to an increase in manufacturing costs, and a potential degradation of quality of the semiconductor material, especially in a delicate ultrawide bandgap semiconductor material, such as, the gallium oxide.
[0012] Consequently, there is a need for an improved, efficient, reliable semiconductor devices and methods in the art to address at least the issues of the prior arts, by providing a semiconductor device fabricated using n-type doping of a gallium oxide (Ga2O3) semiconductor material and a method thereof with a reduced thermal budget, an enhanced dopant activation, and a minimal lattice damage.
SUMMARY
[0013] This section is provided to introduce certain objects and aspects of the present disclosure in a simplified form that are further described below in the detailed description. This summary is not intended to identify the key features or the scope of the claimed subject matter.
[0014] In an aspect, the present disclosure relates to a semiconductor device fabricated using n-type doping of a gallium oxide (Ga2O3) semiconductor material. The semiconductor device includes a gallium oxide (Ga2O3) substrate and a selective n-type doped region formed at a surface of the gallium oxide substrate. Further, the selective n-type doped region is formed by depositing a dopant source layer including amorphous silicon on the gallium oxide substrate. Furthermore, the selective n-type doped region is formed by depositing a protective capping layer over the dopant source layer. Furthermore, the selective n-type doped region is formed by thermally treating the gallium oxide substrate with the dopant source layer and the protective capping layer to diffuse dopant atoms from the dopant source layer into the gallium oxide substrate. Furthermore, the selective n-type doped region is formed by etching the protective capping layer and the dopant source layer to expose the selective n-type doped region.
[0015] In another aspect, the present disclosure relates to a method for n-type doping of a gallium oxide (Ga2O3) semiconductor material in a semiconductor device. The method includes preparing a surface of a gallium oxide (Ga2O3) substrate to remove contaminants. Further, the method includes depositing a dopant source layer on the prepared surface of the gallium oxide substrate. Furthermore, the dopant source layer includes amorphous silicon. Furthermore, the method includes depositing a protective capping layer over the dopant source layer. Furthermore, the protective capping layer is configured to supress oxidation of the dopant source layer during thermal processing. Furthermore, the method includes thermally treating the semiconductor device including the gallium oxide substrate, the dopant source layer, and the protective capping layer. Furthermore, the semiconductor device is treated to diffuse dopant atoms from the dopant source layer into the gallium oxide substrate. Furthermore, the method includes forming a selective n-type doped region at the surface of the gallium oxide substrate. Furthermore, the method includes etching the protective capping layer and the dopant source layer to expose the selective n-type doped region.
[0016] To further clarify the advantages and features of the present disclosure, a more particular description of the disclosure will follow by reference to specific embodiments thereof, which are illustrated in the appended figures. It is to be appreciated that these figures depict only typical embodiments of the disclosure and are therefore not to be considered limiting in scope. The disclosure will be described and explained with additional specificity and detail with the appended figures.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
[0017] The accompanying drawings, which are incorporated herein, and constitute a part of this invention, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that invention of such drawings include the invention of electrical components, electronic components or circuitry commonly used to implement such components.
[0018] FIG. 1 illustrates an exemplary block diagram representation of a semiconductor device fabricated using n-type doping of a gallium oxide (Ga2O3) semiconductor material, according to an example;
[0019] FIG. 2 illustrates an exemplary flow diagram representation of a selective n-type doping of the gallium oxide semiconductor material in the semiconductor device, according to an example;
[0020] FIG. 3 illustrates an exemplary cross-sectional view of a gallium oxide (Ga2O3) substrate after deposition of a dopant source layer, according to an example;
[0021] FIG. 4 illustrates an exemplary cross-sectional view of the gallium oxide substrate after deposition of a protective capping layer over the dopant source layer, according to an example;
[0022] FIG. 5 illustrates an exemplary cross-sectional view of the gallium oxide substrate after thermally treating the gallium oxide substrate with the dopant source layer and the protective capping layer, according to an example;
[0023] FIG. 6 illustrates an exemplary cross-sectional view of the gallium oxide substrate after removal of the protective capping layer over the dopant source layer, according to an example;
[0024] FIG. 7 illustrates an exemplary cross-sectional view of the gallium oxide substrate after removal of the dopant source layer, according to an example;
[0025] FIG. 8 illustrates an exemplary cross-sectional view of the semiconductor device with a selective area patterning and doping of the gallium oxide substrate after selective removal of the protective capping layer over the dopant source layer, according to an example; and
[0026] FIG. 9 illustrates an exemplary flow chart depicting an example method for n-type doping of the gallium oxide (Ga2O3) semiconductor material in the semiconductor device, according to an example.
[0027] The foregoing shall be more apparent from the following more detailed description of the disclosure.
DETAILED DESCRIPTION
[0028] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, that embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter can each be used independently of one another or with any combination of other features. An individual feature may not address all of the problems discussed above or might address only some of the problems discussed above. Some of the problems discussed above might not be fully addressed by any of the features described herein.
[0029] The ensuing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention as set forth.
[0030] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.
[0031] Also, it is noted that individual embodiments may be described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.
[0032] The word “exemplary” and/or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent that the terms “includes”,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive—in a manner similar to the term “comprising” as an open transition word—without precluding any additional or other elements.
[0033] Reference throughout this specification to “one embodiment” or “an embodiment” or “an instance” or “one instance” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
[0035] Examples of the present disclosure provides a semiconductor device fabricated using n-type doping of a gallium oxide (Ga2O3) semiconductor material and a method thereof. The semiconductor device includes a gallium oxide (Ga2O3) substrate and a selective n-type doped region formed at a surface of the gallium oxide substrate. Further, the selective n-type doped region is formed by depositing a dopant source layer including amorphous silicon on the gallium oxide substrate. Furthermore, the selective n-type doped region is formed by depositing a protective capping layer over the dopant source layer. Furthermore, the selective n-type doped region is formed by thermally treating the gallium oxide substrate with the dopant source layer and the protective capping layer to diffuse dopant atoms from the dopant source layer into the gallium oxide substrate. Furthermore, the selective n-type doped region is formed by etching the protective capping layer and the dopant source layer to expose the selective n-type doped region.
[0036] Referring now to the drawings, and more particularly to FIGs. 1 through FIG. 9, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments and these embodiments are described in the context of the following exemplary system and/or method.
[0037] FIG. 1 illustrates an exemplary block diagram representation of a semiconductor device 100 fabricated using n-type doping of a gallium oxide (Ga2O3) semiconductor material, according to an example. The semiconductor device 100 includes a gallium oxide (Ga2O3) substrate102 and a selective n-type doped region 108 formed at a surface of the gallium oxide substrate 102. Further, the selective n-type doped region 108 is formed by depositing a dopant source layer 104. Furthermore, the dopant source layer 104 includes amorphous silicon on the gallium oxide substrate 102. Furthermore, the selective n-type doped region 108 is formed by depositing a protective capping layer 106 over the dopant source layer 104. Furthermore, the selective n-type doped region 108 is formed by thermally treating the gallium oxide substrate 102 with the dopant source layer 104 and the protective capping layer 106 to diffuse dopant atoms from the dopant source layer 104 into the gallium oxide substrate 102. Furthermore, the selective n-type doped region 108 is formed by etching the protective capping layer 106 and the dopant source layer 104 to expose the selective n-type doped region 108.
[0038] In an exemplary embodiment, the selective n-type doped region 108 is configured to form an ohmic contact with reduced contact resistance.
[0039] In another exemplary embodiment, the selective n-type doped region 108 includes patterned source and drain regions for at least one of a Field-Effect Transistor (FET) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Further, the FET is a type of transistor, which controls a flow of electrical current by applying an electric field to a semiconductor channel. Furthermore, the current flows from a source terminal to a drain terminal. Furthermore, the amount of current is regulated by the voltage applied to a gate terminal. Furthermore, a gate voltage modulates conductivity of the semiconductor channel between the source terminal and the drain terminal. Furthermore, the gate voltage allows the FET to act as at least one of a switch and an amplifier. Furthermore, the FET is characterized by a high input impedance and a low power consumption. Furthermore, the FET is suitable for a wide range of analog and digital applications. Furthermore, the MOSFET is a specific type of the FET. Furthermore, in the MOSFET, the gate terminal is electrically insulated from the semiconductor channel by a thin layer of insulating material. Furthermore, the thin layer of insulating material is generally made up of at least one of a silicon dioxide (SiO2) and materials with high dielectric constants. Furthermore, the MOSFET includes four terminals including the gate terminal, a source terminal, the drain terminal, and a substrate terminal. Furthermore, when a voltage is applied to the gate terminal, an electric field is created. Furthermore, the electric field modulates conductivity of the semiconductor channel formed in the gallium oxide semiconductor material between the source terminal and the drain terminal. Furthermore, MOSFET is widely used in modern electronic circuits, including, but not limited to, processors, memory devices, and power electronics, due to scalability, low power consumption, and high switching speeds of the MOSFET.
[0040] Additionally, the patterned source and the drain regions refer to specifically defined and fabricated areas within a semiconductor substrate, for example, but not limited to, the gallium oxide substrate 102. Further, the patterned source and the drain regions for at least one of the FET and the MOSFET are formed using, for example, but not limited to, a photolithography and doping techniques. Furthermore, the patterned source and drain regions are localized, precisely shaped, and doped areas of the semiconductor device 100. Furthermore, a plurality of electrical carriers enters the semiconductor device 100 through the patterned source and exit through the drain regions of the semiconductor channel. Furthermore, the patterned sources and the drain regions are formed through a plurality of patterning processes. Furthermore, the plurality of patterning processes may include, but not limited to, the photolithography and an ion implantation. Furthermore, the photolithography defines exact regions on the semiconductor substrate, for example, but not limited to, the gallium oxide substrate 102. Furthermore, the ion implantation introduces dopants, for example, but not limited to phosphorus and boron. Furthermore, the ion implantation creates at least one of a n-type region and a p-type region.
[0041] In yet another exemplary embodiment, the protective capping layer 106 includes a material selected from the group consisting at least one of, a silicon dioxide (SiO2), a silicon nitride (Si3N4), and an aluminium oxide (Al2O3).
[0042] In yet another exemplary embodiment, the selective n-type doped region 108 is configured to form at least one of a source contact, a drain contact, and the ohmic contact for the semiconductor device 100. Further, the source contact is a terminal through which carriers, such as, a plurality of electrons and a plurality of holes enter the semiconductor device 100. Furthermore, the source contact serves as an origin of current flow in at least one of the FET and the MOSFET, when the semiconductor device 100 is conducting. Furthermore, the drain contact is a terminal through which carriers exit the semiconductor device 100. Furthermore, the drain contact is positioned opposite to the source contact. Furthermore, the drain contact collects current after the current flows through the semiconductor channel. Furthermore, the ohmic contact is a metal-semiconductor interface. Furthermore, the ohmic contact allows current to flow freely in both directions with negligible resistance and no rectification. Furthermore, the ohmic contact behaves like a resistor and not a diode. Furthermore, the ohmic contact may be used for both the source terminal and the drain terminal to ensure efficient carrier injection and carrier extraction.
[0043] FIG. 2 illustrates an exemplary flow diagram representation 200 of a selective n-type doping of the gallium oxide semiconductor material in the semiconductor device 100, according to an example. According to FIG. 2, the gallium oxide (Ga2O3) semiconductor material using amorphous silicon as a solid doping source in the dopant source layer 104, the protective capping layer 106 using a silicon dioxide (SiO2), and the selective n-type doped region 108 for the semiconductor device 100 (hereinafter interchangeably referred to as the semiconductor structure 100) is depicted. Further, designs of the semiconductor device 100 is fabricated according to a type of a transistor device. Further, a first semiconductor layer such as the gallium oxide substrate 102 may be implemented as a bulk substrate. Furthermore, the first semiconductor layer such as the gallium oxide substrate 102 may be appropriately doped to provide negative (n)-type electron carriers.
[0044] In an exemplary embodiment, the gallium oxide substrate 102 may include samples of one or more wafers of the gallium oxide semiconductor material. Initially, at step 202, a surface of the gallium oxide substrate 102 is prepared to remove contaminants. Further, a doping process of the semiconductor structure 100 may include cleaning of one or more wafers of the gallium oxide semiconductor material. Furthermore, the samples are cleaned with, for example but not limited to, a piranha solution to avoid a surface contamination of the samples. Furthermore, the piranha solution may include a mixture of, for example but not limited to, three parts of sulfuric acid and one part of hydrogen peroxide, which may be represented as a ratio of sulfuric acid to hydrogen peroxide, which is 3 is to 1 (3:1 H2SO4: H2O2). Furthermore, the samples of the one or more wafers of the gallium oxide substrate 102 may be passed through a solution of, for example, one part of Hydrofluoric (HF) acid and for example, fifty parts of Deionized water, which may be represented as a ratio of Hydrofluoric acid to Deionized water, which is 1 is to 50 (1:50 HF: DI water) for, a time duration of, including but not limited to, 10 seconds.
[0045] Additionally, at step 204, the dopant source layer 104 including amorphous silicon is deposited on the prepared surface of the gallium oxide substrate 102. Further, at step 206, the protective capping layer 106 is deposited over the dopant source layer 104. Furthermore, the protective capping layer 106 is configured to supress oxidation of the dopant source layer 104 during thermal processing. Furthermore, at step 208, the semiconductor device 100 including the gallium oxide substrate 102, the dopant source layer 104 and the protective capping layer 106 is thermally treated to diffuse dopant atoms from the dopant source layer 104 into the gallium oxide substrate 102. Furthermore, the selective n-type doped region 108 is formed at the surface of the gallium oxide substrate 102. Furthermore, at step 210 and at step 212, the protective capping layer 106 and the dopant source layer 104 are etched to expose the selective n-type doped region 108. Furthermore, at step 210, the protective capping layer 106 may be etched with the help of a Buffered Oxide Etchant (BOE). Furthermore, the BOE includes a high etch rate and a good selectivity towards silicon. Furthermore, etching of the protective capping layer 106 may be confirmed using, such as, but not limited to, an optical microscope. Furthermore, at step 212, the dopant source layer 104 is etched on the gallium oxide substrate 102 using a Tetramethylammonium Hydroxide (TMAH) treatment. Furthermore, a Tetramethylammonium Hydroxide (TMAH) solution may include, for example, but not limited to, thirty parts of TMAH and one hundred and twenty parts of deionised (DI) water, which may be represented by a ratio of TMAH to Deionized water, which is 30 is to 120 (30:120 TMAH: DI water). Furthermore, the TMAH solution may then be heated at, for example, but not limited to, 75°C. Furthermore, the gallium oxide substrate 102 may be processed by dipping the samples in the TMAH solution for a time duration of, such as but not limited to, 10 seconds to ensure complete removal of the dopant source layer 104 from the surface of the gallium oxide substrate 102.
[0046] FIG. 3 illustrates an exemplary cross-sectional view 300 of the gallium oxide substrate 102 after deposition of the dopant source layer 104, according to an example. According to FIG. 2 and FIG. 3, at step 204, the dopant source layer 104 including amorphous silicon is deposited on the prepared surface of the gallium oxide substrate 102 is depicted. Further, amorphous silicon, for example, but not limited to, in the range of 20 to 30 nano-meter (nm) may be deposited by a Plasma Enhanced Chemical Vapour Deposition (PECVD) method. Furthermore, the dopant source layer 104 including amorphous silicon is deposited on a top surface of the one or more samples of wafers of the gallium oxide substrate 102. Furthermore, the dopant source layer 104 may be deposited on the top surface of the gallium oxide substrate 102, at a temperature lying, for example, but not limited to, within the range of 250o C to 350oC at a pressure, such as, but not limited to, 1000 or less than 1000 millitorr (mTorr) under a high-frequency plasma.
[0047] FIG. 4 illustrates an exemplary cross-sectional view 400 of the gallium oxide substrate 102 after deposition of the protective capping layer 106 over the dopant source layer 104, according to an example. Further, at step 206, the protective capping layer 106 is deposited over the dopant source layer 104. Furthermore, the protective capping layer 106 is configured to supress oxidation of the dopant source layer 104 during thermal processing. Furthermore, at step 206, a layer of the silicon dioxide coated over amorphous silicon (a-Si) is deposited on the one or more samples of wafers of the gallium oxide substrate 102, as shown in FIG. 2. Furthermore, the layer of the silicon dioxide may act as the protective capping layer 106 on amorphous silicon so deposited. Furthermore, the layer of the silicon dioxide may also be deposited using the PECVD method. Furthermore, the deposition using the PECVD is done at a temperature lying, for example, but not limited to, within the range of 250o C to 350o C at a pressure, such as, but not limited to, 1000 or less than 1000 millitorr (mTorr) under a high-frequency plasma. Furthermore, the use of amorphous silicon as the n-type dopant and the layer of the silicon dioxide on the gallium oxide substrate 102 allows the selective n-type doping. Furthermore, the selective n-type doping provides a very thin layer, which is for example, less than 20 nano meter (nm), of the gallium oxide substrate 102 at the top surface of the semiconductor structure 100. Furthermore, the layer of the silicon dioxide as the protective capping layer 106 is provided to prevent the oxidization at the top of amorphous silicon in the form of the dopant source layer 104 during high temperature anneal.
[0048] FIG. 5 illustrates an exemplary cross-sectional view 500 of the gallium oxide substrate 102 after thermally treating the gallium oxide substrate 102 with the dopant source layer 104 and the protective capping layer 106, according to an example. Further, at step 208, the semiconductor device 100 is thermally treated to diffuse dopant atoms from the dopant source layer 104 into the gallium oxide substrate 102 for forming the selective n-type doped region 108 at the surface of the gallium oxide substrate 102. Furthermore, the semiconductor device includes the gallium oxide substrate 102, the dopant source layer 104 and the protective capping layer 106. Furthermore, at step 208, a high-temperature annealing of the semiconductor structure 100 including coating of the gallium oxide substrate 102 with amorphous silicon as the dopant source layer 104 and the layer of the SiO2 as the protective capping layer 106 is done using a Rapid Thermal Annealing (RTA) technique. Furthermore, the RTA technique with a single ramp of, for example, but not limited to, 10°C/s ramp rate is used. Furthermore, the RTA technique provides a rapid thermal shock to the semiconductor structure 100. Furthermore, the rapid thermal shock facilitates the dissociation of silicon bonds and fusion of silicon bonds into the gallium oxide substrate layer 102 within the semiconductor structure 100. Furthermore, the process of the RTA technique may be carried out at a temperature lying, for example but not limited to, within the range of 900°C to 1050 °C for a time duration at least 5 minutes in a Nitrogen (N2) gas ambient atmosphere. Furthermore, the time duration and the temperature may decide a depth of the dopant source layer 104 so diffused. Furthermore, the semiconductor structure 100 may then be subjected to furnace anneal at a temperature lying, for example, but not limited to, within the range of 900°C to 1050 °C for a time duration of at least 30 minutes in the N2 ambient atmosphere, as illustrated in FIG. 2. Furthermore, the process of annealing may enable slow diffusion of the dopant source layer 104 including amorphous silicon into the layer of the gallium oxide substrate 102 detrimental in determining the depth of doping.
[0049] FIG. 6 illustrates an exemplary cross-sectional view 600 of the gallium oxide substrate 102 after removal of the protective capping layer 106 over the dopant source layer 104, according to an example. Further, at step 210, the protective capping layer 106 and the dopant source layer 104 is etched to expose the selective n-type doped region 108. Furthermore, at step 210, the protective capping layer 106 may be etched with the help of the Buffered Oxide Etchant (BOE). Furthermore, after diffusion of the dopant source layer 104 into the layer of the gallium oxide substrate 102, at step 210, etching of the dopant source layer 104 including amorphous silicon and the protective capping layer 106 of the silicon dioxide is done until the layer of the gallium oxide substrate 102 is formed as shown in FIG. 2. Furthermore, the protective capping layer 106 of the silicon dioxide may be etched with the help of the BOE. Furthermore, the BOE includes a high etch rate and a good selectivity towards silicon. Furthermore, the etching of the protective capping layer 106 may be confirmed using, such as, but not limited to, an optical microscope.
[0050] FIG. 7 illustrates an exemplary cross-sectional view 700 of the gallium oxide substrate 102 after removal of the dopant source layer 104, according to an example. Further, at step 212, the protective capping layer 106 and the dopant source layer 104 is etched to expose the selective n-type doped region 108. Furthermore, at step 212, the dopant source layer 104 is etched on the gallium oxide substrate 102 using a Tetramethylammonium Hydroxide (TMAH) treatment. According to FIG. 2 and FIG. 7, at step 212, the TMAH treatment is illustrated. Further, the TMAH treatment is done to etch the dopant source layer 104 including amorphous silicon on the gallium oxide substrate 102. Furthermore, the TMAH treatment is done using a Tetramethylammonium Hydroxide (TMAH) solution. Furthermore, the TMAH solution, includes, such as, but not limited to, thirty parts of TMAH solution and one hundred and twenty parts of deionised (DI) water, thereby forming a ratio of TMAH solution to DI water, which is 30 is to 120 (TMAH:DI 30:120). Furthermore, the TMAH solution may then be heated at a temperature of, for example, but not limited to, 75°C. Furthermore, the gallium oxide substrate 102 is processed by dipping the sample of the gallium oxide substrate 102 in the TMAH solution for, a time duration of, such as but not limited to, 10 seconds. Furthermore, the gallium oxide substrate 102 is processed to ensure complete removal of the dopant source layer 104 including amorphous silicon from the surface of the gallium oxide substrate 102.
[0051] FIG. 8 illustrates an exemplary cross-sectional view 800 of the semiconductor device 100 with a selective area patterning and doping of the gallium oxide substrate 102 after selective removal of the protective capping layer 106 over the dopant source layer 104, according to an example. According to FIG. 8, the wet etching method using the TMAH solution is illustrated. Further, the wet etching method may be used for at least one of the selective patterning and the selective etching step 802 at the surface of the gallium oxide substrate 102 before the high-temperature anneal step. Furthermore, the selective patterning of the surface of the gallium oxide substrate 102 may include a selective area doping. Furthermore, the selective area doping may be essential in developing the source contact and the drain contact for the transistor device, such as, but not limited to, the Field Effect Transistor (FET). Furthermore, an electrical characterization may be carried out to determine the efficacy of the selective area doping. Furthermore, the electrical characterization may include, for example, a current-voltage (IV) and a transfer length method (TLM) measurement to estimate enhancement in a sheet resistance and a contact resistivity. Furthermore, a depth and a profile of the selective area doping may be validated using a Secondary-Ion Mass Spectrometry (SIMS) technique. Furthermore, SIMS technique is an analytical technique, which may detect the composition of surface of a material by sputtering the surface of the material with a focused Ion beam. Furthermore, SIMS technique analyses the ejected secondary ions based on respective mass-to-charge ratio.
[0052] Additionally, FIG. 2 to FIG. 8 illustrates a process for forming the semiconductor structure 100. Further, the process may be carried out by the process of a chemical vapor deposition (CVD), a Plasma Enhanced Chemical Vapour Deposition (PECVD), a metal organic chemical vapor deposition (MOCVD), a migration enhanced epitaxy (MEE), an atomic layer epitaxy (ALE), or the like (as described in FIG. 9)
[0053] FIG. 9 illustrates an exemplary flow chart depicting an example method 900 for n-type doping of a gallium oxide (Ga2O3) semiconductor material in a semiconductor device 100, according to an example.
[0054] At block 902, the method 900 may include preparing a surface of a gallium oxide (Ga2O3) substrate 102 to remove contaminants.
[0055] At block 904, the method 900 may include depositing a dopant source layer 104 on the prepared surface of the gallium oxide substrate 102. Further, the dopant source layer 104 includes amorphous silicon.
[0056] At block 906, the method 900 may include depositing a protective capping layer 106 over the dopant source layer 104. Further, the protective capping layer 106 is configured to supress oxidation of the dopant source layer 104 during thermal processing
[0057] At block 908, the method 900 may include thermally treating the semiconductor device 100 including the gallium oxide substrate 102, the dopant source layer 104, and the protective capping layer 106. Further, the semiconductor 100 is thermally treated to diffuse dopant atoms from the dopant source layer 104 into the gallium oxide substrate 102 for forming a selective n-type doped region 108 at the surface of the gallium oxide substrate 102.
[0058] At block 910, the method 900 may include etching the protective capping layer 106 and the dopant source layer 104 to expose the selective n-type doped region 108.
[0059] In an exemplary embodiment, the method 900 may include patterning the dopant source layer 104 prior to thermally treating to define specific regions for n-type doping. Further, patterning the dopant source layer 104 includes at least one of a wet etching process and a dry etching process. In an example, the wet etching process is a semiconductor fabrication technique, where liquid chemical solutions are used to remove material from the surface of the dopant source layer 104. Furthermore, a wet etchant selectively reacts with specific materials to dissolve the specific materials to achieve a desired pattern. Furthermore, the wet etchant, includes, but not limited to, a hydrofluoric acid (HF) for silicon dioxide (SiO2) and a phosphoric acid for aluminum (Al). Furthermore, a dry etching process uses at least one of a plasma and a plurality of reactive gases in a vacuum chamber to remove materials from the dopant source layer 104. Furthermore, the dry etching process offers anisotropic etching, which is preferred for creating at least one of a fine feature and a vertical feature.
[0060] In another exemplary embodiment, the method 900 may include depositing the dopant source layer 104. Further, deposition includes a chemical vapor deposition process.
[0061] In yet another exemplary embodiment, the method 900 may include the chemical vapor deposition process. Further, the chemical vapor deposition process includes at least one of a plasma-enhanced chemical vapor deposition (PECVD), a metal-organic chemical vapor deposition (MOCVD), and an atomic layer deposition (ALD). Furthermore, the PECVD is a thin-film deposition technique in which plasma energy is used to enhance the chemical reaction of a plurality of precursor gases at relatively low substrate temperatures. Furthermore, the plasma decomposes the gases, which allows the desired material, such as, but not limited to, silicon nitride and silicon dioxide to deposit on the surface of the gallium oxide substrate 102 with good step coverage and uniformity. Furthermore, the PECVD is used for low-temperature deposition of at least one of dielectric layers and passivation layers in the semiconductor device 100. Furthermore, the MOCVD is a type of chemical vapor deposition process, where metal-organic compounds serve as the plurality of precursor gases. Furthermore, the plurality of precursor gases decomposes thermally to form thin films of compound semiconductors, such as, but not limited to Gallium Nitride (GaN), Indium Phosphide (InP), and Aluminum Gallium Arsenide (AlGaAs). Furthermore, the MOCVD is conducted under controlled temperature and pressure conditions. Furthermore, MOCVD is commonly used for fabricating optoelectronic devices, including, but not limited to Light Emitting Diodes (LEDs) and high-frequency transistors. Furthermore, the ALD is a thin-film deposition method, which is based on alternating and self-limiting surface reactions of a plurality of gaseous precursors. Furthermore, each cycle deposits a single atomic layer. Furthermore, the single atomic layer has a precise thickness control and a conformal coating even on a plurality of complex 3D structures. Furthermore, the ALD is ideal for high dielectrics constants, gate oxides, and barrier layers in advanced semiconductor nodes.
[0062] In yet another exemplary embodiment, the method 900 may include the protective capping layer 106. Further, the protective capping layer 106 includes a material selected from the group of at least one of a silicon dioxide (SiO2), a silicon nitride (Si3N4), and an aluminium oxide (Al2O3).
[0063] In yet another exemplary embodiment, the method 900 may include preparing the surface of the gallium oxide substrate 102. Further, the preparation includes applying a chemical cleaning process to remove surface impurities.
[0064] In yet another exemplary embodiment, the method 900 may include thermally treating. Further, the thermally treating includes at least one of rapid thermal annealing, furnace annealing, and laser annealing in at least one of an inert and a controlled atmosphere. Furthermore, the rapid thermal annealing is a short-duration and a high-temperature process, where the surface of the gallium oxide substrate 102 is heated rapidly, generally in seconds. Furthermore, the rapid thermal annealing uses a plurality of high-intensity lamps. Furthermore, the rapid thermal annealing is used for dopant activation and interface improvement with minimal diffusion. Furthermore, the furnace annealing is a longer-duration annealing process. Furthermore, the furnace annealing is performed in a conventional furnace at elevated temperatures. Furthermore, the furnace annealing is suitable for batch processing and bulk dopant diffusion. Furthermore, the laser annealing is a highly localized and an ultra-fast annealing method. Furthermore, the laser annealing uses a plurality of laser pulses to heat specific regions of the surface of the gallium oxide substrate 102. Furthermore, the laser annealing process enables precise thermal treatment with minimal thermal budget. Furthermore, the thermal treatment including at least one of the rapid thermal annealing, the furnace annealing, and the laser annealing improve electrical and structural properties of the semiconductor material along with preserving integrity of the semiconductor device 100.
[0065] In yet another exemplary embodiment, the method 900 may include etching the protective capping layer 106 and the dopant source layer 104. Further, etching includes a chemical etching process selective to the gallium oxide substrate 102. Further, the chemical etching process selective to the gallium oxide substrate 102 uses a plurality of specific wet chemical etchants. Further, the plurality of specific wet chemical etchants removes at least one of a layer and a material without significantly attacking and damaging the gallium oxide substrate 102. Furthermore, at least one of the layer and the material, includes but not limited to, photoresist, dielectric films, and metals. Furthermore, the selectivity is based on the difference in chemical reactivity between the materials to be etched and the gallium oxide substrate 102. Furthermore, the plurality of specific wet chemical etchants includes a Buffered Oxide Etch (BOE) and a Dilute Hydrofluoric Acid (HF). Furthermore, the plurality of specific wet chemical etchants may remove the silicon dioxide and a plurality of dielectric layers, while exhibiting low etch rates for the gallium oxide substrate 102. Therefore, the plurality of specific wet chemical etchants offers good selectivity. Further, the plurality of specific wet chemical etchants may include at least one of an acidic solution and a basic solution, for example, but not limited to Hydrochloric Acid (HCl), Sulphuric Acid (H2SO4), and Ammonium Hydroxide (NH4OH). Furthermore, certain acidic solution and basic solution may etch metals and oxides depending on a surface chemistry and an etching target while having minimal impact on the gallium oxide substrate 102. Furthermore, the chemical etching process is typically carried out in at least one of a room temperature and a slightly elevated temperature. Furthermore, the etch rate and selectivity are controlled by solution concentration, temperature, and time. Furthermore, the selective chemical etching process is crucial for patterning layers on the gallium oxide substrate 102 without degrading structural properties and electrical properties of the semiconductor material.
[0066] The present disclosure provides a semiconductor device 100 fabricated using n-type doping of the gallium oxide (Ga2O3) semiconductor material and a method 900 thereof, which enables a high-precision fabrication of gallium oxide (Ga2O3)-based electronic device and an optoelectronic device. Further, the semiconductor device 100 provides a thin, selective and surface-level doping of the gallium oxide (Ga2O3). Furthermore, the semiconductor device 100 uses amorphous silicon as a solid dopant source. Furthermore, the semiconductor device 100 uses a silicon dioxide capping layer to prevent an oxidization of a top amorphous layer. Furthermore, the semiconductor device 100 uses a silicon dioxide capping layer to protect the dopant source during high temperature anneal. Furthermore, the semiconductor device 100 provides a damage-free surface post-doping and dopant source removal using a plurality of wet etch methods as opposed to a conventional ion-implantation process.
[0067] Additionally, the semiconductor device 100 enables a slow diffusion of dopant into the gallium oxide (Ga2O3) layer. Furthermore, the slow diffusion of dopant into gallium oxide layer is detrimental in determining a depth of doping, using a high-temperature annealing method. Furthermore, the semiconductor device 100 uses a layer of amorphous silicon as the n-type dopant for gallium oxide (Ga2O3). Furthermore, the semiconductor device 100 subsequently uses the silicon dioxide capping layer to cap the gallium oxide (Ga2O3) substrate 102. Further, the semiconductor device 100 allows the use of minimally thick layers of amorphous silicon and silicon dioxide. Furthermore, a set of unit process parameters, such as, deposition and annealing temperatures, along with a specific wet etch chemistry are optimized to achieve the desired n-type doping without damaging the layer of the gallium oxide substrate 102. Furthermore, the layer of amorphous silicon is used as a solid doping source in the semiconductor device 100.
[0068] The present disclosure provides a method 900 for selective n-type doping of the gallium oxide (Ga2O3) semiconductor material in the semiconductor device 100. Further, the method 900 includes creating a thin layer of high n-type conductivity on a surface of the gallium oxide substrate 102. Furthermore, the method 900 uses a sacrificial layer of amorphous silicon deposited on the gallium oxide substrate 102. Furthermore, the method 900 uses the layer of amorphous silicon, which acts as a source of dopant atoms, for diffusion into the gallium oxide substrate 102. Furthermore, on top of the layer of amorphous silicon may lie a protective layer of the silicon dioxide to safeguard the layer of amorphous silicon during high-temperature processing. Furthermore, the method 900 provides a two-step thermal treatment. Furthermore, the two-step thermal treatment allows dopant atoms to effectively diffuse from the layer of amorphous silicon into the gallium oxide substrate 102. Furthermore, the two-step thermal treatment which may form a shallow and a highly conductive n-doped region at surface of the gallium oxide substrate 102. Furthermore, the method 900 provides that the layer of amorphous silicon and the layer of the silicon dioxide is removed through the chemical etching, which may reveal the gallium oxide substrate 102 with deposited n-type conductivity. Furthermore, the method 900 provides an appropriate introduction of a thin layer of n-doping critical for various gallium oxide-based semiconductor devices.
[0069] The present systems and methods may provide the semiconductor device 100 such as a transistor, which includes the Field-Effect Transistor (FET) and the Metal-oxide-Semiconductor Field-Effect Transistor (MOSFET). Further, when the FET is an n-type FET, the doped regions and a semiconductor layer are also n-type doped. Furthermore, the heavier doped (N) regions may allow ohmic contacts to be made to the semiconductor layer. Furthermore, a plurality of active devices may be formed within an integrated circuit. Furthermore, the embodiments herein include, for example, the n-type FET, a NPN (Negative-Positive-Negative) bipolar transistor, a planar n-channel Metal-Oxide-Semiconductor (MOS) transistor, and the like. Although, an illustrative structure has been described as a structure formed on one type of substrate and at least two type of layers, similar semiconductor devices may be fabricated using other substrates, a plurality of monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure.
[0070] The present systems and methods may provide a gallium oxide based-semiconductor device. Further, the gallium oxide based-semiconductor device may be an emerging technology for high-voltage and high-power electronics. Further, a wide range of power electronics applications requiring high voltage, may include, such as, but not limited to, a plurality of traction inverters, a plurality of electric trucks, a plurality of locomotives, a plurality of Electric Vehicle (EV) charging infrastructures, and the like. Furthermore, at commercial scale, a Silicon Carbide (SiC), a plurality of Field Effect transistors (FETs) and a plurality of silicon Insulated Gate Bipolar Transistors (IGBTs) may be used for high-voltage and high-power electronics. Furthermore, with the advent of the gallium oxide, high-voltage and high-power electronics may benefit from the use of the gallium oxide based-semiconductor devices.
[0071] The written description describes the subject matter herein to enable any person skilled in the art to make and use the embodiments. The scope of the subject matter embodiments is defined by the claims and may include other modifications that occur to those skilled in the art. Such other modifications are intended to be within the scope of the claims if they have similar elements that do not differ from the literal language of the claims or if they include equivalent elements with insubstantial differences from the literal language of the claims.
[0072] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary, a variety of optional components are described to illustrate the wide variety of possible embodiments of the invention. When a single device or article is described herein, it will be apparent that more than one device/article (whether they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the invention need not include the device itself.
[0073] The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the disclosed embodiments. Also, the words “comprising”, “having”, “containing”, and “including”, and other similar forms are intended to be equivalent in meaning and be open-ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise.
[0074] Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the embodiments of the present invention are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.
,CLAIMS:CLAIMS
We claim:
1. A semiconductor device (100) fabricated using selective n-type doping of a gallium oxide (Ga2O3) semiconductor material, the semiconductor device (100) comprising:
a gallium oxide (Ga2O3) substrate (102); and
a selective n-type doped region (108) formed at a surface of the gallium oxide substrate (102), wherein the selective n-type doped region (108) is formed by:
depositing a dopant source layer (104) comprising amorphous silicon on the gallium oxide substrate (102);
depositing a protective capping layer (106) over the dopant source layer (104);
thermally treating the gallium oxide substrate (102) with the dopant source layer (104) and the protective capping layer (106) to diffuse dopant atoms from the dopant source layer (104) into the gallium oxide substrate (102); and
etching the protective capping layer (106) and the dopant source layer (104) to expose the selective n-type doped region (108).
2. The semiconductor device (100) as claimed in claim 1, wherein the selective n-type doped region (108) is configured to form an ohmic contact with reduced contact resistance.
3. The semiconductor device (100) as claimed in claim 1, wherein the selective n-type doped region (108) comprises patterned source and drain regions for at least one of a Field-Effect Transistor (FET) and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

4. The semiconductor device (100) as claimed in claim 1, wherein the protective capping layer (106) comprises a material selected from the group consisting at least one of, a silicon dioxide (SiO2), a silicon nitride (Si3N4), and an aluminium oxide (Al2O3).
5. The semiconductor device (100) as claimed in claim 1, wherein the selective n-type doped region (108) is configured to form at least one of a source contact, a drain contact, and the ohmic contact for the semiconductor device (100).
6. A method (900) for n-type doping of a gallium oxide (Ga2O3) semiconductor material in a semiconductor device (100), the method (900) comprising:
preparing a surface of a gallium oxide (Ga2O3) substrate (102) to remove contaminants;
depositing a dopant source layer (104) on the prepared surface of the gallium oxide substrate (102), wherein the dopant source layer (104) comprises amorphous silicon;
depositing a protective capping layer (106) over the dopant source layer (104), wherein the protective capping layer (106) is configured to supress oxidation of the dopant source layer (104) during thermal processing;
thermally treating the semiconductor device (100) comprising the gallium oxide substrate (102), the dopant source layer (104), and the protective capping layer (106), to diffuse dopant atoms from the dopant source layer (104) into the gallium oxide substrate (102), for forming a selective n-type doped region (108) at the surface of the gallium oxide substrate (102); and
etching the protective capping layer (106) and the dopant source layer (104) to expose the selective n-type doped region (108).
7. The method (900) as claimed in claim 6, further comprising patterning the dopant source layer (104) prior to thermally treating to define specific regions for n-type doping, wherein patterning the dopant source layer (104) comprises a wet etching process or a dry etching process.
8. The method (900) as claimed in claim 6, wherein depositing the dopant source layer (104) comprises a chemical vapor deposition process.
9. The method (900) as claimed in claim 7, wherein the chemical vapor deposition process comprises at least one of a plasma-enhanced chemical vapor deposition (PECVD), a metal-organic chemical vapor deposition (MOCVD), and an atomic layer deposition (ALD).
10. The method (900) as claimed in claim 6, wherein the protective capping layer (106) comprises a material selected from the group of at least one of a silicon dioxide (SiO2), a silicon nitride (Si3N4), and an aluminium oxide (Al2O3).
11. The method (900) as claimed in claim 6, wherein preparing the surface of the gallium oxide substrate (102) comprises applying a chemical cleaning process to remove surface impurities.
12. The method (900) as claimed in claim 6, wherein thermally treating comprises at least one of rapid thermal annealing, furnace annealing, or laser annealing in an inert or controlled atmosphere.

13. The method (900) as claimed in claim 6, wherein etching the protective capping layer (106) and the dopant source layer (104) comprises a chemical etching process selective to the gallium oxide substrate (102).