Description:REUSABLE GENERAL-PURPOSE INPUT -OUTPUT BANK OF FPGA WITH AUTO VOLTAGE DETECTION AND CONFIGURATION
CROSS-REFERENCES TO RELATED APPLICATION
[0001] None.
FIELD OF THE INVENTION
[0002] The invention belongs to the field of embedded hardware design and in particular to reusable General Purpose Input Output (GPIO) bank of Field Programmable Gate Arrays (FPGA).
DESCRIPTION OF THE RELATED ART
[0003] Field programmable gate arrays (FPGAs) have evolved over several decades and have always been at the forefront of performance. As the most powerful form of standard IC available to developers, FPGAs can be used to accelerate the most time-critical functions. FPGAs are the silicon devices that can be dynamically reprogrammed with a hardware design and data path that exactly matches a user workload. FPGAs are particularly useful for prototyping application-specific integrated circuits (ASICs) or processors. An FPGA can be reprogrammed until the ASIC or processor design is final and bug-free and the actual manufacturing of the final ASIC begins. General Purpose Input and output (GPIO) resources on an FPGA target are physical structures that allow connecting an FPGA target to other devices in a system. I/O resources translate analog or digital signals to or from a digital value so as to process the signals using an FPGA target. FPGA GPIO block supports wide range of signaling standard and speed. As per these standards, these IO’s are interfaced to 3rd party ASIC’s or interfaced boards (Ethernet, High Speed ADC’s, etc.) in testing and prototype building.
[0004] To enable the designers to accelerate their application development or prototype testing, engineers need hardware platform which is completely reusable. To increase the hardware reusability, FPGA Mezzanine Card (FMC) was developed and ratified by a consortium of FPGA vendors and end-user members of the VITA 57 working group. FMC are ANSI Standards which define a compact electro-mechanical expansion interface for a child card to an FPGA baseboard or other device with re-configurable I/O capability. Here, user data, GPIO from the FPGA is extended to connector so that it can be reused. Before the IO is used, signaling voltage standard has to be predefined by the parent board and this voltage supply has to be extended to FMC standard card through power pins. User application will be defined (hardware design) on the FMC card. The FMC card will be interfaced to FPGA parent board. If application is changed, then user should redesign the card and plug to the same FPGA parent board. In time of application change, the user has to look into I/O voltage standard available on the main board.
[0005] Many FPGA parent designs are available where the user needs to rework on the parent board by seeing the board instruction manual to set the FPGA I/O bank to particular standard voltage. However, they need to have prior knowledge on power modules used in the design and hands on experience surface mount device soldering. US patent application 20090251867A1 proposes a reusable modular daughter card to provide application-specific functionality as required to comply with industry specifications. The application defined on the child card decides the voltage required by FPGA IO bank. Here, the end-user needs to architect the child card based on their specific application and selectively connect it to the FPGA IO bank, ensuring that all voltage rails match the IO bank specification.
[0006] US patent 20210064804A1 proposes a system and method for adaptive operating voltage in a field programmable gate array (FPGA). In the proposed system FPGA are embedded into single die or multi die processors for specific logic control. The processors and FPGA have associated integrated voltage regulator (IVR) for powering up. These IVR’s are monitored and controlled by a power management controller in the processors. Chinese patent 111198527B addresses the technical issue where the GPIO output state of the FPGA in existing programmable logic devices cannot be effectively controlled during power-on configuration, leading to unstable output states that affect the controlled load. A hardware interfacing to GPIO of FPGA is developed to overcome the unknown state during power up and FPGA configuration.
[0007] The primary concern is the development of a reusable FPGA I/O block system that is cost-effective and adaptable to different voltage requirements and application scenarios without necessitating significant hardware changes. This flexibility facilitates easier integration of various child boards with different specifications. However, traditional FPGA systems often lack the requisite flexibility to accommodate varying voltage requirements and application scenarios, necessitating substantial hardware alterations for compatibility with different configurations. Additionally, integrating diverse child boards with distinct specifications poses significant challenges, often resulting in increased complexity and costs. By addressing the limitations of traditional FPGA systems, the present invention paves the way for the development of more efficient and scalable electronic designs.
SUMMARY OF THE INVENTION
[0008] The invention discloses a system (100) for providing reusability of a Field Programmable Gate Array (FPGA) device, the system comprising a FPGA Mezzanine Card (FMC) specification compliant parent board (110) detachably coupled with one or more child boards (150).
[0009] In various embodiments the parent board (110) comprises an FPGA IO block (120) configured to perform input-output functions. An FPGA bank IO power module (114) comprising a second predefined resistor network for reconfiguring a voltage to be supplied. The parent board (110) further comprises the power sensing and decision making module (112) configured to sense the type of signalling standard required by the child board and reconfiguring the FPGA bank IO power module (114) with the required voltage and the IO header (116) configured for connecting with the child board (150).
[0010] In various embodiments the child board (150) comprises the on-board FLASH memory (152) configured to store information of an application and the operating voltage required therefor. The child board (150) further comprises the load sensing module (154) having a first predefined resistor divider network configured to define a voltage requirement of the child board (150) and the IO header (156) configured for connecting with the parent board (110).
[0011] In various embodiments the the application-specific hardware module (158) configured for interfacing hardware according to user specific.
[0012] In various embodiments the FPGA IO block (120) on the parent board (110) is configurable to the required voltage either through reprogramming of the on-board FLASH memory (152) on the child board, or by altering the resistor divider network (154) on the child board to the required voltage.
[0013] In various embodiments the on-board FLASH memory (152) in the child board (150) is an EEPROM with storage of 256 KB or more.
[0014] In various embodiments the power sensing and decision making module (112) is configured to read the onboard FLASH memory (152) on the child board (150) or communicate with the load sending module (154) to configure the FPGA bank voltage accordingly.
[0015] In various embodiments the power sensing and decision making module (112) is configured to monitor power to detect a fluctuation therein.
[0016] In various embodiments the signalling standard is one of CMOS1.2V, CMOS1.8V, CMOS2.5V, CMOS3.3, LVDS, Differential IO or single ended IO.
[0017] In various embodiments the load sensing module (154) comprises a resistor divider including the plurality of resistors R1-Rn connected in parallel and connectable to the module using a series of switches P1 to Pn, where R1 has a base value, and R2 – Rn have decreasing values of resistance. the voltage is divided by closing one or more of the switches and keeping the remaining circuit open.
[0018] In various embodiments the divided voltage from the load sensing module (154) of the child board (150) is given to the power sensing and decision making module (112) to detect the voltage required by the child board (150).
[0019] In various embodiments the power sensing and decision making module (112) is configured for powering the FPGA bank IO power module (114), comprises the plurality of resistors R16/R18/R20/R22/R24 where the resistors have increasing values of resistance are connected in parallel and connectable to the module using a series of switches Q1 to Qn to form R3, at the feedback path is responsible for setting the desired output voltage. The controller (112) opens the appropriate switch based on the type of signaling required by the child board (150).
[0020] This and other aspects are described herein.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The invention has other advantages and features, which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:
[0022] FIG. 1 shows the block representation of interfacing child board to parent board with auto voltage sensing and bank voltage configuring capability.
[0023] FIG. 2 shows the schematic view of the load sensing module.
[0024] FIG. 3 shows the schematic of LM2596 power controller regulator.
[0025] FIG. 4 shows the schematic design of the LM2596 power module.
[0026] FIG. 5 illustrates the detailed block representation of the FPGA parent board.
[0027] FIG. 6 illustrates the FPGA power sequencing of the parent board.
[0028] FIG. 7 shows the power connector on the parent board.
[0029] FIG. 8 shows on-board power indicators.
[0030] FIG. 9 shows the schematic of FPGA power enabling.
[0031] FIG. 10 shows the schematic section of the parent board controller.
[0032] FIG. 11 shows interfacing of the parent-child board GPIO controller.
[0033] FIG. 12 represents the schematic view of EEPROM 24LC256.
[0034] FIG. 13 shows the GPIO header schematic of the child board.
[0035] FIG. 14 shows simulation results of LM2596 for 2.5 and 3.3 output voltages.
[0036] FIG. 15 shows efficiency simulation result of 3.3 and 2.5 output voltages.
[0037] FIG. 16 shows LM2596 power module temperature profile test result.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0038] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope.
[0039] Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on.” Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein.
[0040] The present subject matter in various embodiments describes a system for reusable FPGA (Field-Programmable Gate Array) I/O block adaptable to different voltage requirements and application scenarios without necessitating significant hardware changes. The system comprises an ASIC (Application-Specific Integrated Circuit) unit, referred to as the child board, interfaced with the FPGA, or parent board. The child board includes techniques to record the voltage standard required and the application information, and a resistor network configured in such a way to define the required voltage by the child board. The FPGA module carries out power monitoring and takes appropriate decision at the time of power fluctuation.
[0041] As illustrated in FIG. 1, the system 100 for providing reusability of a Field Programmable Gate Array (FPGA) device wherein the child board 150 is interfaced to parent board 110 with auto voltage sensing and bank voltage configuring capability. The parent board 110 comprises a power sensing and decision making module 112, FPGA IO block 120, an FPGA bank IO power module 114 and an IO header 116. The child board 150 includes an on-board FLASH memory 152, a load sensing module 154 an IO header 156 and application-specific hardware module 158.
[0042] As illustrated in FIG. 1, DDR3(122), SPI FLASH(123), FTDI (124), JTAG (125), FPGA (126) and POWER, VCCINT, VCCBRAM, VCCAUX, VCCDR3L (121) connected to form the FPGA IO block 120 configured to perform input-output functions of the system. The FPGA bank IO power module 114 comprising a second predefined resistor network reconfigures the voltage to be supplied. The power sensing and decision making module 112 configured to sense the type of signalling standard required by the child board and reconfiguring the FPGA bank IO power module 114 with the required voltage. The IO header 116 configured for connecting with the child board 150.
[0043] As illustrated in FIG. 1, the on-board FLASH memory 152 configured to store information of an application and the operating voltage required for the application. The load sensing module 154 having the first predefined resistor divider network configured to define a voltage requirement decides the type of signaling standard required of the child board 150. The IO header 156 configured for connecting with the parent board 110. The application-specific hardware module 158 configured for interfacing hardware according to user specific.
[0044] In various embodiments, power sensing and decision making module (112) reads the child board information for the configuration of IO bank voltage for specific application. Along with bank voltage configuration, power monitoring is carried out, and appropriate decisions are taken during power fluctuation. This load sensing module 154 of child board design technique solves IO voltage reconfiguring on an FPGA parent board 110 and is easily reconfigured in real-time.
[0045] In various embodiments, the on-board FLASH memory 152 in the child board 150 is an EEPROM with storage of 256 KB or more. In the present invention, EEPROM stores the 32 bytes of information of the child board, like manufacturer, date of manufacture, and IO signalling voltage. The design data of the child board 150 is stored in the EEPROM. The EEPROM makes use of standard I2C protocol to communicate with the I/O header 116 using two-wire serial communication (I2C) protocol via a serial data line (SDA) and a serial clock line (SCL). If, the I/O header 116 fails to find the EEPROM or data on the EEPROM, it will prioritize the load sensing module 154 and read the resistor configuration to configure the FPGA bank voltage accordingly.
[0046] In various embodiments, the FPGA IO block 120 on the parent board 110 is configurable to the required voltage either through reprogramming of the on-board FLASH memory 152 on the child board, or by altering the resistor divider network 154 on the child board to the required voltage.
[0047] The algorithm used for child board detection and auto bank IO voltage configuration is as follows,
STEP 1: Initialize the pins of Pi Pico. Here, the input and output pins are defined, and the logic 0 status is written to all the initialized pins.
STEP 2: Initialize I2C pins SDA and SCL for EEPROM communication. The address of the EEPROM is 50h (hex).
STEP 3: Read the EEPROM 32 bytes of data and detect the kind of signaling required by the child board.
STEP 4: Read the ADC value of the VSENSE net, which is the resistor jumper network defined on the child board. After reading the ADC value, store the required bank voltage configuration.
STEP 5: Compare the voltage standard from EEPROM data and ADC data; if it matches, configure the respective voltage to the power module.
STEP 6: If EEPROM data and the ADC data are not matching, then ignore EEPROM data and take the ADC value, and set the required voltage to the power module.
STEP 7: After configuring the power module, enable the FPGA power.
STEP 8: Once the Power is UP, monitor the bank voltage, and if any fluctuation is found, shut down the Power of FPGA.
[0048] As illustrated in FIG. 2, the load sensing module 154 defines the voltage required by the child board wherein plurality of resistors R1-R6 connected in parallel and connectable to the module using a series of switches P1 to P5. Here R1 is 2K ohms, and the value of R3, R4, R5, and R6 are3.9K,2.7K, 2K, and 1.2K ohms, respectively. R2 is not populated debug and development purpose. P1 to P5 are solder jumper headers. Shorting one of the headers and keeping the remaining open circuit will cause to form a basic voltage divider. The divided voltage is provided to the VSENSE pin of the I/O header 156 and transferred to the sense pin of the I/O header 116 for the detection of the voltage required by the child board 150. The sense pin of power sensing and decision making module 112 (pi-Pico) is the ADC pin which converts the analog voltage to digital for processing and configures to require voltage. The GPIO 27 of Pi-Pico is configured to read ADC value.
[0049] As illustrated in FIG.3, the power sensing and decision making module 112 LM2596 is designed for powering FPGA bank IO power module 114 comprises a plurality of resistors R16/R18/R20/R22/R24 where the resistors have increasing values of resistance are connected in parallel and connectable to the module using a series of switches Q1 to Q5 to form R3. The output voltage is programmed to be 1V2/1V5/1V8/2V5/3V3. The required voltage of the child board 150 is sensed and set by the controller (112). The combination of R3 with R16/R18/R20/R22/R24 at the feedback path of the power module is responsible for setting the desired output voltage through switching appropriate N-channel 2N70002 MOSFET. This design is capable of giving five output voltages that are 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. The controller 112 senses the type of signaling standard required by the child board and switches the appropriate transistor (Q1 to Q5) by pulling the gate signal to high, and other gate singles will be pulled low by the controller through which the required feedback path of the power module is closed and required output voltage is met. Here the turn-on-resistance of the MOSFET is approximately 5 ohm which is negligible compared to the feedback path resistance. Here the value of R3 is chosen to be 1.2K ohms, and values of R16, R18, R20, R22, and R24 are to be 22 ohms, 270 ohms, 560 ohms, 1.2K ohm, and 2K ohm, respectively. All the resistors are SMD 1206 packages with 1% tolerance. Once the power is on the FPGA IO power rail is monitored real-time. The configured power rail in monitored with tolerance of 5%. FPGA IO bank voltage can expect 5% of tolerance in their power rails.
[0001] The invention has multiple advantages as set forth herein. The system can adapt to different voltage requirements and application scenarios without requiring significant hardware changes by utilizing an ASIC unit with on-board FLASH memory 152 and a load sensing module 154. This flexibility allows for easier integration of various child boards with different specifications. The use of reusable components and the load sensing module can reduce overall system costs by minimizing the need for custom hardware designs for each application. The ability to reconfigure the FPGA bank voltage based on power requirements helps optimize power consumption, potentially leading to cost savings in power usage. The system offers ease of use and automation, reducing the need for manual intervention and configuration. The modular design of the system allows for scalability, enabling the addition of more child boards and expansion of functionalities as needed, without significant redesign efforts. The system can ensure stable operation even in environments with fluctuating power conditions, enhancing overall reliability and robustness.
[0002] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material the teachings of the invention without departing from its scope, which should be as delineated in the claims appended herewith.
EXAMPLES
Example 1: Design and analysis of the FPGA I/O block system
Power Module
[0003] To power the Bank IO, the Texas Instrument LM2596 regulator is used. LM2596 is a step-down switching regulator fabricated on a monolithic integrated circuit. The regulator is capable of driving a 3A current load with quite a good load line regulation. LM2596 IC has an internal frequency oscillator with frequency compensation. LM2596 requires minimal external components to meet its functionality. The operating or switching frequency of LM2596 is 150 kHz; this low switching frequency uses small-sized filter components, thus making the overall size of the circuit layout small. IC is available in a standard 5-pin TO-220 package with several lead bend options and a 5-pin TO-263 surface-mount package. For initial testing, the TO-220 package is used, and the test results are summarized. The circuit is designed, and the Ti WEBENCH Power designer has simulated functionality. Once the simulation is met, the design is transferred to the schematic by the Altium designer. Once the schematic is captured, the PCB layout is designed with the Altium designer. FIG. 4 shows the schematic design of the LM2596 power module.
[0004] LM2596 is a 5-pin power module. Pin-1 is power in a pin where the input voltage of 5V is fed in. Pin-2 is a power out where regulated output voltage is received. The output voltages vary from 1.23V to 3.3V. Pin-3 is the power ground pin. Pin-4 is feedback; here, the output voltage is tapped through the resistor divider network (R1 and R2 form schematic) and fed back to the power module to make sure the output voltages are in desired power rails. By varying the resistance in a combination of R1 and R3, the output voltage can be varied. These resistors are metal-film resistors with high precision and 1% tolerance. Equations 1 and 2 for setting the output voltage with respect to the feedback resistor.
(1)

[0005] Or select a value for R1 between 240 Ω and 1.5 kΩ. The lower resistor values minimize noise pickup in the sensitive feedback pin.
(2)

[0006] Once the schematic design is frozen, the same design is transferred to the Ti power web-bench simulator to verify the design. After verifying the design and meeting the expected results, the schematic design is further transferred to the PCB layout. Verifying the layout against the design rule check (DRC) and proceeding with Gerber generation for getting the board manufactured. After receiving the manufactured board, components are soldered and test the board before using it in an FPGA parent board. The test procedure followed here is as follows, as
Step 1. Take the LM2596 test board and connect it to a known DC source of 5V. Along with this, we need to connect the ammeter in series and the voltmeter in parallel with the test board. This is to measure the input voltage and current drawn by the test board from the known DC source.
Step 2. The next step is to set the required output voltage from the LM2596 test board. The required voltage can be set by varying the resistance of R1 and R2 from the schematic, and this is achieved by equations 1 and 2.
Step 3. After setting the voltage, connect the resistance dummy load to check the current drawn and the voltage at the output. Similar to the input, we need to connect the output terminal to the voltmeter in parallel to the load and ammeter series with the load for capturing power out parameters.
[0007] After doing the required setup, results are noted for the input power, output power, and efficiency are calculated and compared with simulating results.
FPGA Parent Board
[0008] FIG. 5 illustrates the detailed block representation of the FPGA parent board. FPGA parent board makes use of Mimas Mini A7-FPGA Development board from Numato systems. Mimas A7 Mini board featuring Artix 7 FPGA (XC7A35T – FTG256C package) with FTDI’s FT2232H Dual-Channel USB device. Mimas A7 board stack up on the FPGA parent board. To make the Mimas A7 board compatible with the FPAG parent board for multi-voltage bank IO voltage configuration, on board GPIO bank power supply on the Mimas A7 board has been removed by de-soldering, and power good signal from the FPGA core supply has been tapped from the Mimas A7 development board.
[0009] The tapped power good signal from the Mimas A7 board is taken out to the FPGA parent board to power on the FPGA IO bank power module in time of power sequencing. FIG. 6 illustrates the FPGA power sequencing of the parent board. The GPIO header on Mimas A7 has power pins that directly get connected to Artix-7 GPIO bank power pins; indirectly, these power pins are used to feed the power to the FPGA IO bank on Mimas A7 from the parent board. Basically, Mimas A7 bank IO power supply is bypassed, and power for the IO bank is taken from the parent board.
[0010] The parent board consists of two power supplies; one is capable of powering 3V3 for all the peripherals like RGB debug LED, FPGA power switching circuit, power good sensing circuit, and Pi Pico controller. Another power supply power the FPGA IO bank; the supply output voltage is set by the onboard controller through a resistor network logic switch. Here both the power supplies used are LM2596 power modules by Ti. The onboard Pi Pico controller is responsible for sensing the child board and getting the required information like signaling standard supported by the child board and configuring the power module to the required voltage needed by the child board for application-specific.
[0011] The complete schematic design will be divided into subsections; the 3V3 power section, the FPGA bank IO power section, the FPGA power switching section, Pi Pico controller section, GPIO header and connector section, and on board power and debug LEDs section.
[0012] FIG. 7 shows the power connector on the parent board. J1 is a 2.5mm DC barrel jack forward biased with an SS24 Scotty diode and SMD 1206 0.1uf filter capacitor. The diode protects the board with reverse polarity input power. The required input voltage is 5V.
[0013] FIG. 8 shows onboard power indicators. One LED is connected to the input 5V, and another indicated power output from a 3V3 power supply. R12 and R13 are 1K SMD 1206 package resistors. D4 and D5 are the SMD1206 green LEDs.
[0014] FIG. 3 shows the schematic of LM2596. The output voltage is fixed to 3V3 to power the parent board controller and other peripherals. The R4 value is 1.2K, and the R1 value is 2K.
[0015] FIG. 9 shows the schematic of FPGA power enabling, after sensing the voltage requirement of the child board by the controller, the configuration of the power module will be applied, and later Power to FPGA will be enabled. The FPGA power enables net will be driven high by the controller, through which the input power 5V will be switched and given to Mimas A7 board through the power connector on the parent board. The optocoupler PC817 here drives the MOSFET to switch the relay and close the 5V power rail. Once the relay is switched, the FPGA core and auxiliary supply will power on and send the Power good signal to the parent board to switch on the bank IO power supply; by this, power sequencing is met. Figure 3.12 shows the schematic of onboard LEDs. Here one RGB led is connected to FPGA GPIO, and another RGB LED is connected to the parent controller. Along with RGB LEDs, there are four LEDs connected to FPGA GPIO. The LEDs connected to FPGA GPIO are for user purposes. The one RGB led connected to the controller is for debugging purposes.
[0016] FIG. 10 shows the schematic section of the parent board controller. Here Pi Pico controller has been used for child board sensing and FPGA power switching, followed by FPGA IO bank power module configuring and power monitoring. Pi Pico is a credit-card-sized single-board computer created by the Raspberry Pi Foundation. It is the smallest and cheapest Raspberry Pi model and is designed for educational use. The Pi Pico has a Broadcom BCM2835 Arm Cortex-M0+ CPU, 512KB of SRAM, and 2MB of flash memory. It is powered by a micro USB port or through onboard power pins and can be used with a wide range of accessories, including a camera and display for automation purposes. Here, GPIO0 to GPIO3 is connected to FPGA GPIO for communication purposes, but here these pins are not in function. GPIO4 to GPIO5 is connected to FPGA bank IO power modules feedback switching and FPGA power switching. GPIO10 to GPIO15 are connected to the child board GPIO header. GPIO14 and GPIO15 are the I2C pins that connect to the EEPROM flash memory on the child board. GPIO27 is the ADC pin that is connected to the child boards resistor network configuration through the child board GPIO header. GPIO26 is another ADC pin connected to the parent board FPGA bank IO power module for power monitoring. GPIO20 to GPIO22 connected to parent board RGB LED for debugging and status indicator. GPIO16 to GPIUO19 are connected to the FPGA JTAG header for debugging; in this project, these pins are unfunctional.
[0017] FIG. 11 shows the 2X25 2.54mm pitch right-angled GPIO header schematic. This connector has 36 single-ended and 18 differential pair GPIO that is routed from the Mimas A7 GPIO header. Here the power pins are VCC3V3 and VCCIO and ground. GPIO_1 to GPIO_3 are the GPIO that connect from the parent controller to the child board that can be used for debugging. The SDA and SCL pins are connected to the I2C pin of the controller to the child board EEPROM flash memory. The VSENSE is connected to the ADC pin of the controller on the parent, and the same is connected to the resistor network configuration on the child board.
FPGA Child Board
[0018] The child board mainly consists of EEPROM, resistor configuration network, and supporting hardware for user application-specific, as shown in FIG. 1. The application defined on the board is to generate a clock and observe the output on an oscilloscope, so there has been provided a BNC connector that directly connects the child board to the oscilloscope with a Female to Female BNC connector cable. The onboard EEPROM is from Microchip Technology. 24LC256 is a 256Kb (32K x 8) EEPROM. The EEPROM stores the 32 bytes of information of the child board, like manufacturer, date of manufacture, and IO signaling voltage required by the child board. The predefined resistor configuration network defines the IO voltage requirement by the child board.
[0019] FIG. 12 represents the schematic view of EEPROM 24LC256. I2C pins SCL and SDA are connected to the child board IO header. WP here is write protect pin. If this pin is tied to VCC, then write operations are inhibited but read operations are not affected. If the pin is tied to the ground, then write operations are enabled. Initial to write the board information, these pins are tied to the ground; later, it is tied to VCC by the onboard P8 jumper header.
[0020] FIG. 2 represents the schematic view of the resistor configuration network. This network defines the voltage required by the child board. Here R1 is 2K ohms, and the value of R3, R4, R5, and R6 are3.9K,2.7K, 2K, and 1.2K ohms, respectively. R2 is not populated. P1 to P5 are solder jumper headers. Shorting one of the headers and keeping the remaining open circuit will cause to form a basic voltage divider, and this divided voltage is given to the VSENSE pin of the child board controller. This pin on the header gets connected to the controller sense pin on the parent board and detects the required voltage needed by the child board. FIG. 13 shows the 2X25 2.54mm pitch right-angled GPIO header schematic of the child board. This header is pin-compatible with the parent board controller.
Results
[0021] Initially made use of Altium designer to capture the LM2596 power module design and later transferred the design to TI WEBENCH Power design for verifying and simulation the design. The circuit simulation was carried out for 2.5V and 3.3V of 1A load. The WEBEBCH didn't support 1.2V, 1.5V, and 1.8V output voltage as there are no supporting libraries, but the LM2596 IC support these voltages also, which is clarified from the LM2596 TI datasheet. FIG. 14 shows the 2.5V and 3.3V simulation results. Here the input voltage parameter is DC 5V0; from the graph, we can see that the output voltage is reaching its 90% nominal voltage in 1msec of power on. To conclude here, the output voltage is reaching 90% of output voltage in 1 msec of power input.
[0022] FIG. 15 shows the efficiency of Power module LM2596 for 3V3 output and 2V5 output voltages. The requirement here is of 1A current load at 5V2 input voltage; for these parameters, the achieved efficiency observed from the graph is 75.5% for 3V3 output and 72.8% for 2V5 output voltage. This is quite acceptable.
[0023] Once simulation results are observed, the LM2596 schematic and PCB are developed, required components are soldered, and a test of IC is carried out on the test board. Below table 1 summarizes the test result.
Table 1: LM2596 Test Board - summary of test results.

Iin Vin Vr Ir RL (req) RL Vb Va Ia Vd Pin Pout Ef
0.4 4.97 1.2 1 1.2 1.2 (5%) 1.22 1.19 0.96 0.03 1.96 1.14 58%
0.42 4.97 1.5 1 1.5 1.66(5%) 1.57 1.47 0.94 0.1 2.08 1.38 66.35%
0.53 4.89 1.8 1 1.8 1.83(5%) 1.83 1.76 0.99 0.07 2.59 1.74 67.27%
0.68 4.89 2.5 1 2.5 2.5(5%) 2.54 2.47 1.01 0.07 3.32 2.49 75.14%
1.14 4.9 3.3 1 3.3 3.5(5%) 3.35 3.2 1.29 0.15 5.58 4.2 75%
[0024] The abbreviation used in the table are as follows,
• Iin: Input current is drawn from the known DC source.
•Vin: Input Voltage set at known DC source.
• Vr and Ir: Required output voltage and current, respectively.
• RL (req) : Required Load resistor for testing.
• RL: Standard Load Resistor available with its tolerance value.
• Vb: Output voltage without load.
• Va: Output voltage after load.
• Ia: Output current through the load resistor.
• Vd: Vb – Va
• Pin: Input power (Vin * Iin)
• Pout: Output power (Va * Ia)
• Ef: Pin/ Pout
[0025] To summarize here, the efficiency achieved here for output 3V3 is 75%, and for 2V5, the output is 75.14%. These match the simulation result. The efficiency achieved for other voltage ranges is below 70%, and this is not good for the long run as it consumes more power. Another important parameter to be taken into consideration is the LM2596 temperature profile at a given load. This data is summarized on the temperature vs. time graph in FIG. 16. It is seen clearly that the maximum temperature of IC for 1V2 and 1V5 output voltage has reached 44oC. Similarly, for 1V8, the temperature has reached 48oC; for 2V5, the temperature has reached 50oC; for 3V3, the temperature has reached 77oC. The run has carried out for about 30 mins, and we can see that the temperature has reached a constant value after 15 mins of the run. This can be concluded that for a given constant load of 1A, the temperature does not shoot up to 150oC. The 150oC is the maximum temperature that LM2596 can withstand. In this case, the IC is at a safe operating temperature.
, C , Claims:We claim:
1. A system for providing reusability of a Field Programmable Gate Array (FPGA) device, the system comprising a FPGA Mezzanine Card (FMC) specification compliant parent board (110) detachably coupled with one or more child boards (150), comprising:
a child board (150) including:
an on-board FLASH memory (152) configured to store information of an application and the operating voltage required therefor;
a load sensing module (154) having a first predefined resistor divider network configured to define a voltage requirement of the child board (150); and
an IO header (156) configured for connecting with the parent board (110);and
a parent board (110) comprising:
an FPGA IO block (120) configured to perform input-output functions;
an FPGA bank IO power module (114) comprising a second predefined resistor network for reconfiguring a voltage to be supplied;
a power sensing and decision making module (112) configured to sense the type of signalling standard required by the child board and reconfiguring the FPGA bank IO power module (114) with the required voltage; and
an IO header (116) configured for connecting with the child board (150).

2. The system as claimed in claim 1, wherein an application-specific hardware module (158) configured for interfacing hardware according to user specific.

3. The system as claimed in claim 1, wherein the FPGA IO block (120) on the parent board (110) is configurable to the required voltage either through reprogramming of the on-board FLASH memory (152) on the child board, or by altering the resistor divider network (154) on the child board to the required voltage.

4. The system as claimed in claim 1, the on-board FLASH memory (152) in the child board (150) is an EEPROM with storage of 256 KB or more.

5. The system as claimed in claim 1, wherein the power sensing and decision making module (112) is configured to read the onboard FLASH memory (152) on the child board (150) or communicate with the load sending module (154) to configure the FPGA bank voltage accordingly.
6. The system as claimed in claim 1, wherein the power sensing and decision making module (112) is configured to monitor power to detect a fluctuation therein.

7. The system as claimed in claim 1, wherein the signalling standard is one of CMOS1.2V, CMOS1.8V, CMOS2.5V, CMOS3.3, LVDS, Differential IO or single ended IO.

8. The system as claimed in claim 1, wherein the load sensing module (154) comprises a resistor divider including:
a plurality of resistors R1-Rn connected in parallel and connectable to the module using a series of switches P1 to Pn, where R1 has a base value, and R2 – Rn have decreasing values of resistance; and
the voltage is divided by closing one or more of the switches and keeping the remaining circuit open.

9. The system as claimed in claim 8, wherein the divided voltage from the load sensing module (154) of the child board (150) is given to the to the power sensing and decision making module (112) to detect the voltage required by the child board (150).

10. The system as claimed in claim 1, wherein, the power sensing and decision making module (112) is configured for powering the FPGA bank IO power module (114), comprising:
a plurality of resistors R16/R18/R20/R22/R24 where the resistors have increasing values of resistance are connected in parallel and connectable to the module using a series of switches Q1 to Qn to form R3, at the feedback path is responsible for setting the desired output voltage; and
the controller (112) opens the appropriate switch based on the type of signaling required by the child board (150).