Description:[001] The current invention relates the design of a DLJLFET synapse that can realize various synaptic functions and neuronal spiking analogous to the biological system. The neurobiological system, such as the human brain consumes ultralow power for encoding, processing complex spatiotemporal information, recognition, and classification. The neuromorphic computing system has attracted vast interest due to its capability very close to the human brain in terms of performance, area, accuracy, and energy efficiency. Neuromorphic structures attempt to mimic the conduct of the human brain, which will broaden novel energy-efficient computing systems. Theoretical investigation is done using SILVACO ATLAS 2D- TCAD simulation tool to investigates the functionality of proposed neuromorphic RISC-inspired scalable system using DLJLFET.
BACKGROUND
[002] Continued advances in semiconductor markets have been encouraged due to the improvement in the transistor
performance. However as the feature size is scaled [1], the deleterious short channel effects (SCEs), such as threshold voltage roll-off, drain induced barrier lowering (DIBL), subthreshold slope (SS), velocity saturation, and larger drain OFF state current have hindered the device performance and limits the device scaling .

[003] In addition, the channel scaling causes the shifting of the drain area depletion width towards source region and it continuously results in a variety of side effects. To overcome the different SCEs, MOSFETs other structures such as tunnel FET, FinFET, nanowire FETs,SOI FinFETs and junctionless transistors are explored. In the inversion-mode transistor, the process of sharp p-n junction formation at S/D regions has become a major challenge
due to diffusion law and the dopant atoms distribution in the semiconductor. Dealing with the above constraints,
junctionless field effect transistors are investigated as they have shown less SCEs.

[004] They offer various advantages such as junction free environment, simple and easy process of fabrication, better electrical properties, electrostatic integrity and inherent ability, lesser thermal budget, higher scalability, lower leakage current due to volume depletion process and they use volume conduction to improve the speed of transport. However, JL-FETs (doping concentration 1019 cm-3) have less ON-current as compared to standard MOSFETs.

[005] Besides this, it faces serious challenges like random dopant fluctuations (RDFs) result in the variation in OFF-state current and threshold voltage (Vth) , higher series resistance of S/D lowers the ON-state current and slows down the device performance, and increased parasitic capacitances.

[006] Further, to switch the device in OFF state, high value of gate work-function (5.5 eV) is required, JL-FET can stick to ON-state even after reducing gate voltage below Vth and fail to turn it OFF due to its undesired latch up because of impact ionization (II). In addition, different JL-FETs structures such as double gate JL-FET, nanowire JL-FET (JL-GAA-NWFET) are also reported to improve the performance of JLFETs.

[007] To overcome these problems dopingless JLT are investigated, where N+ source/drain regions are induced in an intrinsic silicon film by using work function engineering. This device resolves the process variability caused by RDFs, provides better gate control, the CMOS process compatibility, reduced OFF-state current and latching up problem.

[008] In the meantime, spiking neural networks (SNNs) emerge as a possible way for low-power neuromorphic hardware realization. Here biological neurons in the brain (a computer framework subsequently inspired) process information based on a binary spikes. The SNNs are great candidates for investigating neuron computation.

[009] In SNN, individual spikes are sparse in time, hence every spike event contains high information reducing the energy consumption. The SNNs have applications including pattern recognition, image recognition, object detection, speech recognition, medical diagnosis, bioinformatics temporal data processing and many more. The SNN functionality is similar to neurons present in the brain and for that purpose the leaky-integrated-fire (LIF) model is deployed.

[010] The researchers reported LIF neuron using multiple silicon-transistors, non-silicon memory devices, partially-depleted-silicon-on-insulator (PD-SOI) MOSFETs, silicon-NIPIN-diode, Fin-FET devices, bipolar junction transistor (BJT) devices etc.

[011] But earlier reported neurons face some challenging issues like requirement of high temperature processing, extremely-steep doping profile at the source/channel junction for activating and storing the charge carriers.

[012] To resolve above mentioned issues of realizing LIF neuron, the present research reports doping-less junction-less FETs (DL-JLFETs) based LIF neurons. The negative source-to- gate voltage results in charge integration making it energy saving operation with 2.5 orders lower energy consumption as compared to the brain neurons ( ~10-14 J/spike).
[013] The demonstrated DL-JLFET shows neuron activation at 50 GHz spike frequency which is approximately 9 times greater than biological nerves ( f0 = 10 Hz). Hence, DL-JLFET based LIF neurons realization is explored as a potential pathway to enable ultra-energy efficient and high speed neurons.

SUMMARY OF THE INVENTION
[014] In summary, we have explored a highly scalable,a speedy and excessive energy efficient dopingless-JLFET spiking neuron realization for 20 nm channel length. The dopingless-JLFET silicon neuron dissipates the energy of 4 fJ/spike which is 285 ×, 45×, 62.5 ×, and 11250 × lesser as compared to Double gate-JLFET, L-BIMOS, feedback FET (FBFET), and single MOSFET respectively.

[015] The reported spiking neuron generates 50 GHz, 90 GHz spiking frequency for 20 nm and 10 nm channel length respectively. The frequency of spike is approximately 10 × higher than natural biological neuron (10 Hz firing frequency) at sub-10 nm region.

[016] The DLJLFET silicon neuron dissipates the minimum energy (2.8 fJ) and lower threshold voltage (0.28 V) at 10 nm. The reported neuron requires 0.4 V spiking voltage which is 7.5 ×, 7 ×, and 5 × lesser as compared to FinFET, PD-SOI MOSFET, LBIMOS neurons, respectively.

OBJECTIVE OF INVENTION
[017] Spiking neural networks (SNNs) emerge as a possible way for low-power neuromorphic hardware realization. Here biological neurons in the brain (a computer framework subsequently inspired) process information based on a binary spikes. The SNNs are great candidates for investigating neuron computation. In SNN, individual spikes are sparse in time, hence every spike event contains high information reducing the energy consumption.
[018] The SNN functionality is similar to neurons present in the brain and for that purpose the leaky-integrated-fire (LIF) model is deployed. The researchers reported LIF neuron using multiple silicon-transistors,non-silicon memory devices, partially-depleted-silicon-on-insulator(PD-SOI) MOSFETs, silicon-NIPIN-diode , Fin-FET devices, bipolar junction transistor (BJT) devices etc.
[019] But earlier reported neurons face some challenging issues like requirement of high temperature processing, extremely-steep doping profile at the source/channel junction for activating and storing the charge carriers.
[020] To resolve above mentioned issues of realizing LIF neuron, the present research reoprts doping-less junction-less FETs (DL-JLFETs) based LIF neurons. The LIF behavior in DL-JLFET has been achieved due to the impact ionization (II) phenomena. This work, calibrated and exhaustive 2-D TCAD simulations are deployed to demonstrate the LIF neuron functionality.
[021] It is observed that DL-JLFET exhibits -0.35 V threshold voltage for shooting spike and the spiking energy is obtained as 4 fJ per spike which enables the reported LIF neuron to be 285 times more efficient as compared to the DG-JLFET LIF neuron. Further, the reported DL-JLFET based LIF neuron exhibits a 50 GHz spiking frequency at 20 nm channel length when the drain terminal is biased at 0.4 V.
[022] It is observed that spiking frequency increases and energy per spike decreases at low gate length due to the higher II rate in the device body for the lower dimensions. At 10 nm gate length energy required per spike is 2.8 fJ which is ~ 407, ~ 64.3, ~ 89.3, and ~ 16071 times lower than that of DGJLFET, L-shaped BIMOS, Feedback FET, and single MOSFET,respectively. Moreover, owing to the dopingless junctionless realization, this device based neuron demonstrates better gate control, reduces the latching-up problem, and immunity towards the process variability due to random dopant fluctuations (RDFs).
BRIEF DESCRIPTION OF DRAWINGS
[023] The accompanying drawings are included for providing better understanding of the concept, and are incorporated in and constitute a part of these specifications. The drawings illustrate the exemplary embodiments of the inventive concept and, together with the description, serve to explain the detailed principle of the inventive concept.
[024] Fig. 1. Demonstrates (a) a biological nervous system having cell body or soma with nucleus, dendrites for collecting the information from other neuron and the axon; (b) mathematical algorithm for nervous system; (c) a parallel combination of resistance and capacitance to represent LIF model at circuit level ; (d) generation of action potential and impulse train at output due to different electrical input signals ; and (e) enhancement in spiking frequency with increasing electrical input signals after spike threshold value.
[025] Fig. 2. Illustrates (a) Demonstration of dopingless-JLFET neuronal device and (b) calibration of transfer characteristics with the earlier reported dopingless JLFET [20].
[026] Fig. 3. Demonstrates transient fluctuations of spike current for different VSG at VDG=0.4V at gate length of (a) 20 nm, (b) 10 nm, (c) kink effect.

[027] Fig. 4. Shows applied electrical input signals and spike train at output of dopingless- JLFET LIF silicon neuron for different VSG and VDG = 0.4 V (a) VSG =-0.35 V (b) VSG = -0.37 V, (c) VSG = -0.40 V, and (d) VSG = -0.42 V.

[028] Fig. 5. Depicts (a) Frequency of spike signals generated at output versus VSG and (b) Energy of spike signals generated versus VSG.

[029] Fig. 6. Demonstrates (a) Dopingless-JLFET LIF neuron input biasing with output current spike, (b) energy band diagram for equilibrium and fire state, (c) hole concentration plot at equilibrium (t1) and fire state (t3), and (d) total current density plot for equilibrium and fire conditions.

[030] Fig. 7. Illustrates the Dopingless-JLFET LIF neuron contour plots for hole concentration at (a) equilibrium state, (b) fire state; total current density at (c) equilibrium state (t1), (d) fire state (t3), II rate at (e) equilibrium state, and (f) fire state.

[031] Fig. 8. Depicts (a) device gate length scaling impact on (a) output current spike; (b) threshold voltage (c) spiking frequency; (d) energy per spike.

[032] Fig. 9. Depicts schematics of the SNN for dopingless-JLFET LIF silicon neuron.

DETAILED DESCRIPTION:
[033] Hereinafter, preferred embodiments of the inventive concept will be described in depth with reference to the accompanying drawings in such a manner that the technical idea of the inventive concept may be easily carried out by a person with the basic skills in the art to which the invention pertains. The current disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein.
Model And Computational Approach
[034] Fig. 1 (a) illustrates a biological neuron structure. The dendrites present in neuron structure collect input signals information from various synapses and collect responses as Ik. The soma is useful for performing the LIF functionality using the collected input signals information. In the end, spike inputs are accumulated and activates a neuron spiking function. The produced spike tends to reach another neural with an axon spike driver assistance.

[035] Let us first consider the case of a neuron driven by inputs Xk1, Xk2, Xk3 · · ·Xkm and a positive synaptic weights Wk1,Wk2,Wk3 · · ·Wkm (see Fig. 1(b)). These synaptic weights and bias weights are summarized at summing junction. The neuron activation is used to produce LIF function. The LIF neuron monitors its membrane potential, Vk, which integrates incoming input spiking signals and produces an output signal, whenever the membrane potential Vk crosses a predefined threshold/critical voltage (Vcrit). The LIF model for SNN realization can be represented by connecting capacitor (Ck) in parallel with the leaking resistor (R0) having conductance, gk as illustrated in Fig. 1(c).

[036] Fig. 2(a) shows the 2-D cross-sectional view of the reported DL-JLFET as a LIF neuron. The charge accumulation functionality takes place due to high electric field under channel region, which enhances II rate in DL-JLFET. The DL-JLFET LIF neuron uses source to gate voltage bias (VSG) to describe the charge integration phenomena and applied VDG results into high electric field. Due to the enhanced II rate, potential well is used for collecting excess charge carriers. SILVACO Atlas simulator [34] is deployed to emulate the DL-JLFET as LIF neural. The device is simulated after incorporating Lombardi mobility model, bandgap narrowing (BGN), Shockley–Read–Hall recombination models.
[037] The simulation frame work deployed here is well calibrated against [20] [Fig. 2(b)]. The device dimensions considered are source/drain/channel doping is considered as 1×1019 cm-3, length of the source/ drain region is taken as 20 nm each, gate work-function is 4.6 eV, gate oxide is considered as HfO2 of thickness 1 nm, and gate length is varied as 10, 12, 15, 18, 20 nm.

[038] For computing the spiking energy, below expression [22] is used.
Espike = Vspike × tspike × Ith
5. RESULTS AND DISCUSSION
[039] Here, neuron functionality of DL-JLFET is captured using electrical input signals in form of voltage. The dopingless-JLFET device serve as cell body of original brain neuron and voltage of cell body work as membrane potential. Here, in DL-JLFET device, gate electrode is used as the reference terminal and it is biased at 0 V.

A. Impact of VSG on DL-JLFET Silicon Neuron

[040] Here, Fig. 3(a), Fig.3(b) illustrates transient fluctuations of the spike current for different input voltages when VDG is fixed at 0.4V at the gate length of 20 nm and 10 nm, respectively. The generation of excess carriers is based on II mechanism. At proper VDG and VSG biasing, II is initiated. This biasing lowers down the barrier potential that leads to the instant increase in the drain current, as shown in Fig. 3(a) and Fig. 3(b). It is evident that with the increase in input voltage VSG, the drain current ID, reaches predefined threshold current Ith (set at 0.5 mA /µm)) faster [25], [27],[33].

[041] Here, Vth compatible to Ith is -0.35V at 20 nm channel length and -0.28V at 10 nm channel length due to the charge integration in the potential well as depicted in Fig. 3(a) and Fig. 3(b), respectively. Hence, high II rate at smaller gate length results in reduced Vth. As long as Vin is less than Vth (i.e < -0.35 V at 20 nm channel length and < -0.28V at 10 nm channel length), drain current (Iout) reaches maximum value before reaching to its threshold current Ith = 0.5 mA/µm.

[042] Thus, at lower input voltage, spike is not available at output. In other hand, as Vin is greater than -0.35 V and - 0.28 V for the channel length equal to 20 nm and 10 nm, respectively,a spike is generated at output as shown in Fig.3(a) and Fig. 3(b). This indicates that at a particular VSG, ID reaches the current limit, Ith (set at 0.5 mA /µm).

[043] Hence, at smaller channel length, due to high II rate, fast transients are observed to mimic neuron functionality. Therefore, for dopingless-JLFET LIF neuron, at 10 nm channel length, Vth is observed as -0.28 V which is | 70mV | lowered as compared to the Vth at 20 nm channel length as shown in Fig. 3(a) and Fig. 3(b).

[044] The kink-effect for dopingless-JLFET is observed in the output characteristics for different VSG at 20 nm channel length (Fig. 3(c)) to confirm charge integration due to II. The effect of kink is observed after applying 0.4 V at drain terminal as shown in Fig. 3(c).

B. Spiking Behavior of dopingless-JLFET Silicon Neuron
[045] The reported dopingless-JLFET shows the excessive production of charge carrier due to II phenomena at lower voltage. This is an important parameter for the activation of silicon neuron property in the device. One of the outstanding features of the dopingless-JLFET device based LIF neuron is that the drain current increases with time for various input voltage (VSG) values.

[046] Therefore, we analysed ID with respect to time for different VSG values, where VD is constant at 0.4 V as illustrated in Fig. 4. However, spike formation takes place when VSG is kept higher than 0.35 V at fixed VDG of 0.4 V. At VDG = 0.4 V and VSG = -0.35 V, the spike current at output crosses the threshold value (Ith = 0.5 mA/µm ) and spiking impulse signal disappears due to imposed reset action, i.e., VDG = 0 V is applied for 12 ps, which is required for removing the deposited hole carriers

[047] Now, one more time, VDG =0.4 V is applied for 1 pico-second, and this procedure tends to increase the current value again, which results into production of spiking signal after crossing Ith value, as depicted in Fig. 4 (b). In that event, train of impulse signals is originated after every 13 pico-second, which is used to calculate the spiking frequency of output signal. The no of spikes shaped signals increases with increasing VSG, which
is confirmed from Fig. 4 (b)-(d).

[048] The train of spike signals generation is a result of quick storage of holes in the potential well due to high II rate. As | VSG | increases, associated output current reaches Ith immediately due to high electric field causing II. Therefore, a higher value of spike frequency is attained with an enhancement in the VSG. If considered input voltage is less i.e. | VSG | less than 0.35 V, zero spiking frequency is marked for dopingless-JLFET LIF neuron as depicted in Fig. 5 (a). Here, zero spikes are because of the inadequate electron distribution from the source area to the drain area is attained with an enhancement in the VSG.
[049] Whereas, for high electrical input i.e | VSG | greater than 0.35 V, it is observed that drain terminal current arrive at Ith of 0.5 mA /µm as depicted in Fig. 3(a). Thus, it causes current spikes at the output. Hence, as | VSG | above 0.35V, f0 increases in continuity as represented in Fig. 5 (a). Therefore, the reported dopingless-JLFET structure provides the property of a natural neuron, i.e., for | VSG | less than 0.35 V, zero spiking frequency is marked and for | VSG | greater than 0.35 V, number of spiking current pulse increases that results in the increment of spiking frequency.

[050] The current pulse spiking frequency for the reported dopingless-JLFET LIF silicon neuron is found to be in the range of 50 GHz, which is an important parameter for the hardware acceleration [26] for neuron computation. The integrated block of leaky neuron function for DL-JLFET LIF reports maximum energyof 4 fJ at VDG = 0.40 V and VSG = -0.35 V. This energy consumption for spikes are calculated by eqn. (2) given below using following parameters [22],[41].
Espike = Vspike × tspike × Ith (2)
Espike = 0.4V × 0.5mA/µm × 20ps = 4fJ (3)

[051] The various bias conditions required to document spiking conduct and to implement the SNN way of behaving are illustrated in Fig. 5. The emitter to base voltage should be above threshold voltage to achieve spiking signals.

[052] The calculated energy/spike using above expression is less in comparison to earlier stated LIF neuron. Hence, dopingless- JLFET reported as the most energy efficient LIF neuron for SNN. As VSG increases, rapid accumulation of charge carriers takes place result in the integration of output current ID. Hence, energy for each spike reduces as we increase input source to gate voltage as depicted in Fig. 5(b).

[053] The neural behaviour of device at equilibrium and fire condition is depicted using band diagram, hole concentration plot and current density plot as visible in Fig. 6. This entire mechanism can be verified using contours plots for hole concentration, II rate and total current density at equilibrium and fire state are depicted in Fig. 7. The dopingless-JLFET LIF silicon neuron works on principle of II of carriers, which give rise to extremely large number of holes to observe standard LIF neuron attributes.

[054] The energy band diagram for dopingless- JLFET under equilibrium condition (VSG = VDG = 0 V) and at fire condition (VSG = -0.35 V, VDG = 0.4 V) is illustrated. in Fig. 6(b). Here, from energy band diagram, it is observed
that the source/channel region barrier height is very high at equilibrium condition at time instant t1. Due to this, electrons thermionic emission does not take place from source to drain region. Hence, the hole concentration and total current density are very low as depicted in Fig. 6(c), Fig. 6(d), Fig. 7(a), Fig.7(c). Due to no thermionic emission, II rate is very less as observed in Fig. 7(e). Therefore, under equilibrium condition, dopingless-JLFET will be in OFF condition.

[055] The II is initiated to start conduction with the help of charge integration phenomena and proper biasing. At time instant t2, as VSG is increased, barrier potential reduces in comparison to t1 time interval at equilibrium condition. Due to which, electrons start flowing from S/D regions results in II. This stage is known as carrier integration state as holes start to accumulate in potential well.

[056] At fixed VDG = 0.4 V, increase in | VSG | results in charge accumulation mechanism. When dopingless-JLFET is biased at VSG = -0.35 V, VDG = 0.4 V, source–channel region barrier height is decreased as validated in Fig. 6(b). Due to reduced barrier height, electrons thermionic emission takes place from S/D region. These created electrons flow in drain area leaving holes in channel region. This can be confirmed using hole concentration plots, total current density plot as illustrated in Fig. 6(c), Fig. 6(d), Fig. 7(b), Fig.7 (d) at fire state of dopingless-JLFET based LIF silicon neuron.

[057] At this state, II rate will be high in channel region, this can be observed in Fig. 7(f). Thus, at fire state (t3 time instant) of operation, device will produce a spike shaped current signal (Ith =0.5 mA /µm) at the output terminal. The accumulated holes result in additional electrostatic shrinkage of source–channel barrier which causes flow of hole leakage current towards the source side originating from channel area. This leakage describes the “leaking” characteristics of dopingless-JLFET based LIF silicon neuron. At t4 time instant shown in Fig. 6(a) represents the reset condition of device.

[058] At ID = Ith, the device resetting action takes place by biasing the drain terminal at zero potential. Due to this holes accumulated in channel region will recombine results into zero current due to equal amount of hole leakage current and current due to II hole. Hence,dopingless-JLFET silicon neuron is in reset condition. After a particular refractory time, device drain terminal is again biased at 0.4V to work as LIF silicon neuron.

C. Effect of Channel Length Scaling
[059] The spiking characteristics of the reported dopingless- JLFET neuron is controlled by II which occurs under channel region. As the II rate is highly dependent on an electric field developed under channel area, hence the spiking behavior of dopingless-JLFET neuron is obtained. Therefore, at VSG= -0.35 V, VDG = 0.4 V, we have investigated the effect of different channel lengths on the output spike current, Vth, spiking frequency and energy consumption by each spike as shown in the inset of Fig. 8(a), 8(b), 8(c), and 8(d), respectively.

[060] It is observed that reduction in channel length from 30nm to 12 nm results in requirement of less time to reach its predefined threshold current (Ith=0.5 mA /µm) due to the high speed of charge integration at smaller Lg as shown in Fig. 8(a). This behavior is because of the high electric field below channel area which is responsible for the increased II rate. Therefore, at smaller channel length, drain current reaches to Ith at faster rate, thus reduces the threshold voltage (Fig.8(b)) and increases the spiking frequency of dopingless-JLFET LIF neuron as depicted in Fig. 8(c).

[061] Thus, due to high II rate at the reduced channel length, the spiking energy decreases significantly [see Fig. 8(d)]. Hence, the reported DL-JLFET device works as the LIF neuron. Therefore, the right choice of channel length is important for controlling the spiking energy as well as to ensure the performance of the device.

D. SNN Implementation for dopingless-JLFET LIF Neuron

[062] Fig. 9 illustrates the input voltage (Vin) which give rise to current at output (Iout). Here, VDG is subjected to reset region. For the better impact ionization mechanism, drain biasing is responsible maintaining Vin greater than Vth. With the help of proper biasing, extremely large amount of holes are stored, which result into formation of positive feedback and enhancement in output current Iout. Whenever Iout crosses the threshold current, impulse is fired at output and reset circuit is activated and VDG get reset.
, Claims:Claim 1: A leaky-integrate-fire (LIF) neuron device comprising:
• a dopingless junctionless field-effect transistor (DL-JLFET),
• wherein the DL-JLFET includes an intrinsic silicon channel with source and drain regions induced via work-function engineering,
• a gate oxide formed of high-k dielectric material,
• and configured to exhibit impact ionization (II) phenomena under specific source-to-gate (VSG) and drain-to-gate (VDG) biasing conditions,
• wherein said II effect results in carrier accumulation in a potential well to generate a spike current when a threshold voltage is crossed,
• thereby mimicking the spiking behavior of a biological neuron.
Claim 2: The LIF neuron device of claim 1, wherein the gate oxide comprises hafnium dioxide (HfO2) with a thickness of 1 nm.
Claim 3: The LIF neuron device of claim 1, wherein the channel length is in the range of 10 nm to 20 nm for improved spiking frequency and energy efficiency.
Claim 4: The LIF neuron device of claim 1, wherein the threshold voltage required for spike generation is approximately -0.35 V at 20 nm gate length and -0.28 V at 10 nm gate length.
Claim 5: The LIF neuron device of claim 1, wherein the energy per spike is approximately 2.8 to 4 femtojoules (fJ).
Claim 6: The LIF neuron device of claim 1, wherein the device achieves a spiking frequency of up to 90 GHz under optimized VSG and VDG biasing conditions.
Claim 7: The LIF neuron device of claim 1, wherein the impact ionization results in enhanced hole concentration and current density in the channel region, enabling leaky behavior through electrostatic barrier modulation.
Claim 8: The LIF neuron device of claim 1, further comprising a reset mechanism through VDG pulsing to discharge accumulated carriers and initiate a refractory period.
Claim 9: A spiking neural network (SNN) system comprising a plurality of LIF neuron devices of claim 1, interconnected to simulate neuronal communication through spike-based signaling.