Description:TECHNICAL FIELD
This disclosure relates generally to the field of the voltage regulators and particularly relates to method and system for communicating via at least one power pin of a voltage regulator.
BACKGROUND
Voltage regulators are crucial for reliable and stable operation of electronic devices as they ensure a steady output voltage despite fluctuations in input voltage or variations in load conditions. These voltage regulators are built using semiconductor fabrication and inherent manufacturing tolerances and variations in the semiconductor fabrication process can lead to deviations in the regulator's output voltage. Thus, a faulty voltage regulator may affect performance of sensitive electronic components.
To prevent this, wafer level trimming may be employed in the manufacturing of three-terminal voltage regulators to achieve precise output voltage specifications. This technique allows adjusting the regulator's parameters at the wafer stage before the individual chips are cut and packaged. Wafer level trimming may be performed by applying laser trimming or electrical programming to the wafer, allowing the manufacturers to finely tune the internal resistors and other components to correct any deviations from the desired output voltage. However, the traditional method of wafer level trimming is limited to the wafer stage and only applicable before the individual chips are cut and packaged. Once a voltage regulator is packaged, the internal components become inaccessible making it difficult or challenging to directly fix or adjust the voltage regulator if a deviation arises in the voltage regulator's output voltage. Further, an additional pad is required for wafer level trimming which adds to the complexity in the manufacturing process. Further, the additional pad can complicate probe card design used in wafer testing. Probe card challenges include increased difficulty in ensuring accurate contact with the additional pads and the potential for increased wear and maintenance requirements, which can affect both the efficiency and cost of the testing process. Further, the additional pads demand more meticulous handling, which may slow down the testing process and increase labor costs.
Therefore, there is a requirement for an effective methodology to fine-tune the output voltage to a desired voltage level.
SUMMARY
In an embodiment, a method of communicating via at least one power pin of a voltage regulator is disclosed. The method may include inputting a binary communication input via the at least one power pin by modulating a voltage between a set of threshold levels. In an embodiment, the set of threshold levels are defined based on a voltage differential. In an embodiment, the voltage differential is determined based on a maximum tolerable voltage and a minimum tolerable voltage of the at least one power pin and a number of threshold levels in the set of threshold levels.
In another embodiment, a voltage regulator is disclosed. The voltage regulator may include at least one power pin. The one power pin is configured to receive a binary communication input, wherein the binary communication input is generated by modulating a voltage between a set of threshold levels. In an embodiment, the set of threshold levels are defined based on a voltage differential. In an embodiment, the voltage differential is determined based on a maximum tolerable voltage and a minimum tolerable voltage of the at least one power pin and a number of threshold levels in the set of threshold levels.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles.
FIG. 1 is a block diagram of an exemplary voltage regulator, in accordance with an embodiment of the present disclosure.
FIG. 2A and FIG. 2B illustrate a first set of binary signals and a second set of binary signals respectively, in accordance with some embodiments of the present disclosure.
FIG. 3 is a timing diagram illustrating a communication protocol for communicating through power supply pins of a voltage regulator, in accordance with an embodiment of the present disclosure.
FIG. 4A is an exemplary transmitter circuit for communicating through power supply pins of a voltage regulator, according to an embodiment.
FIG. 4B is an exemplary receiver circuit for detecting and processing communication signals in a voltage regulator system, in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION OF THE DRAWINGS
Exemplary embodiments are described with reference to the accompanying drawings. Wherever convenient, the same reference numbers are used throughout the drawings to refer to the same or like parts. While examples and features of disclosed principles are described herein, modifications, adaptations, and other implementations are possible without departing from the scope of the disclosed embodiments. It is intended that the following detailed description be considered as exemplary only, with the true scope being indicated by the following claims. Additional illustrative embodiments are listed.
Further, the phrases “in some embodiments”, “in accordance with some embodiments”, “in the embodiments shown”, “in other embodiments”, and the like, mean a particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present disclosure and may be included in more than one embodiment. In addition, such phrases do not necessarily refer to the same embodiments or different embodiments. It is intended that the following detailed description be considered exemplary only, with the true scope and spirit being indicated by the following claims.
Referring now to FIG. 1, a block diagram 100 of an exemplary voltage regulator 102 is illustrated, in accordance with an embodiment of the present disclosure. The voltage regulator 102 has an input pin 'Vin' 104 and an output pin 'Vout' 106 and a ground pin 'GND' 108. It may be noted that the input pin 104 may be electrically coupled to a voltage supply and the output pin 106 may be electrically coupled to a load (not shown). In one exemplary scenario, the voltage regulator 102 may be manufactured to provide an output voltage of about 5 volts at the output pin 106. However, due to inherent variation in silicon there may be a variation in the output voltage making it less or greater than the 5 volt level by some percentage level say 5%. It may be noted that after packaging of the wafer, no wafer level trimming can be performed to alter the output of the voltage regulator 102. Therefore, the present disclosure provides an effective methodology for communicating with the voltage regulator 102 using the input pin 104 'Vin' or the output pin 106 in order to program the voltage regulator 102 to operate in an operational state from a plurality of operational states of the voltage regulator 102. Thus, a communication protocol is defined in the current disclosure that may allow the voltage regulator 102 to operate in a selected operational state. In one example, the plurality of operational states may include operating the voltage regulator 102 to provide an output voltage of about 5 Volts, 8 Volts, 10 Volts and so on. It may be noted that the embodiments of the present disclosure may be utilized to communicate with any system on a chip and not be limited to voltage regulator 102.
It may be noted that a binary communication input may be input via the input pin 104 or the output pin 106 to communicate with the voltage regulator 102. It may be noted that the voltage regulator 102 may work on master-slave configuration where the voltage regulator 102 may act as slave. Thus, the binary communication input may be transmitted from master to slave when the binary communication input is transmitted over the input pin 104. Further, the binary communication input may be transmitted from slave to master when the binary communication input is transmitted over the output pin 106. The data and strobe signals may be embedded within the binary communication input as described in detail below.
In order to provide a binary communication input to the voltage regulator 102, the voltage input provided to the input pin 104 or the output pin 106 may be modulated in a manner that it can replicate the binary "0" and "1". Also, in order for the voltage regulator 102 to intercept the binary communication input based on the modulation of the voltage input a clock signal is required. The clock signal may be embedded within the voltage modulation itself, eliminating the need for a separate clock pin. This approach enables communication through the existing power pins without requiring additional dedicated communication pins, which is particularly advantageous in pin-limited applications. The voltage modulation technique employed ensures that the voltage regulator 102 continues to function properly during the communication process, maintaining its primary regulation function while simultaneously receiving configuration commands.
It may be noted that a binary communication input may be input via the input pin 104 or the output pin 106 by modulating a voltage between a set of threshold levels. Further, the set of threshold levels may be defined based on a voltage differential. It may be noted that the voltage differential may be determined based on a maximum tolerable voltage and a minimum tolerable voltage of the input pin 104 or the output pin 106 and a number of the threshold levels in the set of threshold levels. It may be noted that the maximum tolerable voltage and the minimum tolerable voltage of the input pin 104 or the output pin 106 may depend on physical and electrical specification of the input pin 104 or the output pin 106. The threshold levels are carefully selected to ensure reliable detection of the binary communication input while maintaining proper operation of the voltage regulator 102. By establishing multiple threshold levels within the operating voltage range of the regulator, the communication protocol can distinguish between different voltage states with sufficient noise margin to prevent false detections. This multi-level approach provides robustness against voltage fluctuations and noise that are commonly present on power supply lines, ensuring reliable communication even in electrically noisy environments.
It may be noted that the voltage differential may be determined as a ratio of a difference between the maximum tolerable voltage and the minimum tolerable voltage and the number of threshold levels. Further, a "logic 1" and a "logic 0" of the binary communication input may each be represented based on a first state of a first binary signal and a second state of a second binary signal. Further, the each of the first state and the second state are detected as a "set state" or a "reset state" based on the modulation of the voltage as discussed in detail in subsequent description. The use of two binary signals for detection provides a form of redundancy and error checking in the communication protocol. By requiring specific combinations of states between the first and second binary signals 200A and 200B, the protocol can reject invalid transitions and improve noise immunity. This dual-signal approach enables the receiver to distinguish between intentional communication signals and random voltage fluctuations that might occur during normal operation. Additionally, the hysteresis between the "set state" and "reset state" detection thresholds further enhances the robustness of the communication method by preventing rapid toggling of the detection signals when the voltage is near a threshold level. This sophisticated detection mechanism allows for reliable post-packaging configuration of the voltage regulator 102 without compromising its primary voltage regulation function.
Referring to FIG. 2A and FIG. 2B, a first set of binary signals 200A and a second set of binary signals 200B are depicted respectively in accordance with some embodiments of the present disclosure. As discussed above, a set of threshold levels are defined based on a voltage differential. The voltage differential may be determined as a ratio of a difference between the maximum tolerable voltage and the minimum tolerable voltage and the number of threshold levels. It may be noted that in one example, the set of threshold levels may include a mid-level (Vmid) 206 that may be defined as an average of the Vmax 202 and the Vmin 204. It may be noted that two high levels such as a high-high level (VHH) 208 and a high-low level (VHL) 210 may be defined between the Vmax 202 and the Vmid 206. Further, two low levels such as a low-high level (VLH) 212 and a low-low level (VLL) 214 are defined between the Vmid 206 and the Vmin 204. These threshold levels create distinct voltage ranges that enable reliable detection of binary signals even in the presence of noise or voltage fluctuations on the power supply lines. The use of multiple threshold levels with sufficient separation provides robust signal detection capabilities while still allowing the voltage regulator 102 to function properly throughout the communication process.
Accordingly, the number of threshold levels defined are '5'. Accordingly, the voltage differential may be determined using equation (1) given below. This equation establishes the fundamental voltage step size between adjacent threshold levels, ensuring appropriate spacing for reliable signal detection while maintaining the voltage regulator's operational parameters within acceptable limits. The voltage differential calculation provides a systematic approach to defining the threshold levels based on the available voltage range between maximum and minimum tolerable voltages.
(VMAX-VMIN)/5 ……(1)
Further, the VHH 208 and the VHL 210, the VLH 212 and the VLL 214 may be determined using equations (2) to (5) respectively. These equations precisely define each threshold level as a specific fraction of the total voltage range, creating a structured hierarchy of detection points. By establishing these threshold levels mathematically rather than arbitrarily, the communication protocol ensures consistent performance across different voltage regulator 102 implementations and operating conditions. The equations below provide the exact voltage values for each threshold level relative to the minimum voltage (VMIN), with each threshold separated by one voltage differential unit from adjacent thresholds.
VHH=4×(VMAX-VMIN)/5 ……(2)

VHL=3×(VMAX-VMIN)/5 ……(3)

VLH=2×(VMAX-VMIN)/5 ……(4)

VLL=1×(VMAX-VMIN)/5 ……(5)
Accordingly, a "logic 1" of the binary communication input may be represented based on detection of the first set of binary signals 200A. The first set of binary signals 200A includes a first binary 216 and a second binary signal 218 which are generated based on a modulation of input voltage between the Vmax 202 and the Vmin 204 and some of the set of threshold levels 206-214 as discussed in detail below. Further, a "logic 0" of the binary communication input may be represented based on detection of a second set of binary signals 200B. The second set of binary signal 200B includes a first binary signal 216 and a second binary signal 218 which are generated based on a modulation of input voltage between the Vmax 202 and the Vmin 204 and some of the set of threshold levels 206-214.
It may be noted that the "logic 1" of the binary communication input may be represented by the first set of binary signals 200A. As can be seen in FIG. 2A, the first binary signal 216 of the first set of binary signals 200A may be detected in a "set state" based on the modulation of the voltage from Vmax level 202 to below the VHL level 210 and in a "reset state" based on the modulation of the voltage above the VHH level 208. Further, the second binary signal 218 is always detected in the "reset state" to represent the "logic 1" of the binary communication input. It may be noted that the second binary signal 218 may be in a persistent "reset state" irrespective of the modulation of the voltage. Thus, the first binary signal 216 and the second binary signal 218 of the first set of binary signals 200A may be concurrently detected in order to detect the "logic 1" of the binary communication input. The hysteresis between the VHH and VHL threshold levels provides noise immunity for the first binary 216 signal detection, preventing rapid toggling when the voltage is near a threshold level. This implementation ensures that the first binary signal 216 transitions cleanly between states only when the voltage crosses the defined thresholds with sufficient margin, making the communication protocol robust against minor voltage fluctuations and noise on the power supply lines. The consistent "reset state" of the second binary signal 218 during logic 1 transmission serves as a verification mechanism, confirming that the voltage did not drop to the lower threshold levels that would indicate a logic 0 transmission.
Referring now to FIG. 2B, the "logic 0" of the binary communication input is determined based on the second set of binary signals 200B. The second set of binary signals 200B includes a first binary signal 216 and a second binary signal 218. The first binary signal 216 is detected in a "set state" based on the modulation of the voltage below the VLH level 212 and in a "reset state" based on the modulation of the voltage above the VHH level 208. Further, the second binary signal 218 is detected in a "set state" based on the modulation of the voltage below the VLL level 214 and in a "reset state" based on the modulation of the voltage above the VLH level 212. Thus, the first binary signal 216 and the second binary signal 218 of the second set of binary signals 200B may be concurrently detected in order to detect the "logic 0" of the binary communication input. This configuration creates a distinctive pattern for logic 0 detection that differs significantly from the logic 1 pattern. The first binary signal 216 behaves similarly to its counterpart in logic 1 transmission but responds to the lower VLH threshold rather than VHL. The key differentiator is the second binary signal 218, which actively transitions between states during logic 0 transmission but remains inactive during logic 1 transmission. The hysteresis between VLH and VLL for the second binary signal provides the same noise immunity benefits as described for the first binary signal. This dual-signal approach with different threshold responses creates a robust encoding scheme that can reliably distinguish between logic states even in challenging electrical environments.
Referring now to FIG. 3, a timing diagram illustrating a communication protocol for communicating through power supply pins of a voltage regulator 102 is depicted, in accordance with some embodiments of the present disclosure. As can be seen in FIG. 3, an exemplary communication input “10010” 302 is depicted that when supplied via the Vin pin 104 may configure the voltage regulator 102 to operate in one operational state from the plurality of operational states of the voltage regulator 102 as discussed above. It may be noted that Vin 304 may be modulated in a manner that either of the first set of binary signals 200A or the second set of binary signals 200B may be detected in order to transmit the binary communication input 302.
It may be noted that the first binary signals 216A or 216B may act as a strobe signal 306. Further, received signal 308 may be received based on a pre-receiver signal 310 that may be generated by inverting the second binary signal 218 218A or 218B. Further, in order to detect the received signal 308 the pre-receiver signal 310 is sampled on a falling edge of the strobe signal 306. Accordingly, the binary communication input 302 may be received as the received signal 308 by the voltage regulator 102 in order to configure the voltage regulator 102 to operate in the one operational state from the plurality of operational states of the voltage regulator 102 as discussed above.
Referring now to FIG. 4A, an exemplary transmitter circuit 400A for communicating via at least one power pin of a voltage regulator 102 is illustrated, in accordance with an embodiment of the present disclosure. The transmitter implementation 400A may include a feedback loop where the output voltage Vout 106 from the voltage regulator 102 is used as the input voltage Vin 104. This configuration may allow for dynamic adjustment of the regulator's output based on a communication protocol or a plurality of operational states predefined in a memory (not shown) of the voltage regulator 102.
In some aspects, the transmitter implementation 400A may incorporate a selector logic 402. The selector logic 402 may be configured to select between different voltage levels, such as Vmax level 202, Vmin level 204, or Vmid level 206, based on the desired modulation of the input voltage for inputting the binary communication input 302 and the strobe signal 306 at the Vin 104.
The transmitter implementation 400A may enable precise control over the voltage levels applied to the input pin 104 of the voltage regulator 102. By modulating these voltage levels according to the communication protocol described earlier, the system may effectively transmit binary data to the voltage regulator 102 using its power pin.
In some cases, this implementation may allow for post-packaging adjustment of the voltage regulator's output. For example, if the voltage regulator 102 produces an output of 3.2V, but a 3.3V output is desired, the transmitter implementation 400A may be used to communicate the necessary adjustments to the voltage regulator 102.
The selector logic 104 may operate in conjunction with the defined voltage thresholds (VHH 208, VHL 210, VLH 212, VLL 214) to generate the appropriate voltage levels for representing logic 1 and logic 0 states in the binary communication input. This may allow for robust and reliable communication through the power pin, even in the presence of noise or other electrical disturbances.
Referring now to FIG. 4B, an exemplary receiver circuit 400B for communicating through power supply pins of a voltage regulator 102 is illustrated, in accordance with an embodiment of the present disclosure. The receiver implementation includes a first comparator 404 and a second comparator 406, wherein the first comparator 404 is configured to detect transitions between the VHH level 208 and the VHL level 210 to generate the first binary signal 216. Further, the second comparator 406 is configured to detect transitions between the VLH level 212 and the VLL level 214 to generate the second binary signal 218. The outputs of the first comparator 404 and second comparator 406 are provided to a logic network that includes a pair of D flip-flops arranged in series. It may be noted that the first binary signal 216 may be delayed in order to generate a pulse to reset the first D flip-flop 408 in order for the first D flip-flop 408 to generate the pre-receiver signal 310. Accordingly, the second D flip-flop 410 generates the received signal 308 by sampling the pre-receiver signal 310 on the falling edge of the strobe signal 306. It may be noted that the logic network following the first comparator 404 and the second comparator 406 includes one or more diodes and gates that process the outputs from the first comparator 404 and second comparator 406 to generate the appropriate timing and data signals. This receiver circuit 400B effectively converts the analog voltage level transitions on the power pin into clean digital signals that represent the transmitted binary data. The hysteresis provided by the separate threshold levels (VHH/VHL and VLH/VLL) ensures reliable detection even in the presence of noise on the supply voltage. Accordingly, the binary communication input 302 may be received by the voltage regulator 102 to configure the voltage regulator 102 to operate in a desired operational state from among the plurality of operational states, such as different output voltage levels or other programmable parameters.
In accordance with various embodiments, the disclosed method and system for communicating via power pins of voltage regulators may provide several advantages. The technique allows for post-packaging configuration and adjustment of voltage regulators without requiring additional dedicated communication pins. This can reduce component size, simplify PCB layouts, and lower overall system costs. The voltage-based communication protocol is robust against noise and timing variations typically present on power supply lines. By utilizing multiple voltage thresholds and hysteresis in the detection circuitry, the system maintains reliable data transmission even in electrically noisy environments.
The ability to dynamically adjust voltage regulator 102 parameters after packaging enables greater flexibility in inventory management and product customization. Manufacturers may stock a single voltage regulator 102 part that can be configured for multiple applications, reducing SKU counts and simplifying logistics. The communication method is also backwards-compatible with existing voltage regulator 102 designs, allowing for easy integration into established product lines.
Furthermore, the disclosed technique may enable in-system diagnostics and performance optimization of voltage regulators. System designers can implement adaptive voltage scaling or other power management techniques by leveraging the bi-directional communication capability through the power pins.
While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. The descriptions are not intended to limit the scope of the invention to the particular forms set forth herein. To the contrary, the present descriptions are intended to cover such alternatives, modifications, and equivalents as may be included within the scope of the invention as defined by the appended claims and otherwise appreciated by one of ordinary skill in the art. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments.
It is intended that the disclosure and examples be considered as exemplary only, with a true scope of disclosed embodiments being indicated by the following claims. , Claims:CLAIMS
What is claimed is:
1. A method of communicating via at least one power pin (104, 106) of a voltage regulator (102), the method comprising:
inputting a binary communication input via the at least one power pin (104, 106) by modulating a voltage between a set of threshold levels (208-214),
wherein the set of threshold levels (208-214) are defined based on a voltage differential, and
wherein the voltage differential is determined based on a maximum tolerable voltage (202) and a minimum tolerable voltage (204) of the at least one power pin (104, 106) and a number of the threshold levels in the set of threshold levels (208-214).

2. The method as claimed in claim 1, wherein the input of the communication input configures an operational state from a plurality of operational states of the voltage regulator (102).

3. The method as claimed in claim 1, wherein the voltage differential is determined as a ratio of a difference between the maximum tolerable voltage (202) and the minimum tolerable voltage (204) and the number of threshold levels.

4. The method as claimed in claim 1, wherein the set of threshold levels (208-214) comprises:
a mid-level (206) defined as an average of the maximum tolerable voltage (202) and the minimum tolerable voltage (204); and
two high levels (208, 210) and two low levels (212, 214) defined above and below the mid-level (206) respectively,
wherein the two high levels (208, 210) comprise: a high-high level (208) and a high-low level (210), and
wherein the two low levels (212, 214) comprise: a low-high level (212) and a low-low level (214).

5. The method as claimed in claim 4, wherein a “logic 1” and a “logic 0” of the binary communication input are represented based on a first set binary signals and a second set binary signals, and
wherein each of the first set of binary signals (200A) and the second set of binary signals (200B) include a first binary signal and a second binary signal, and
wherein each of the first binary signal (216) and the second binary signal (218) are detected in a “set state” or a “reset state” based on the modulation of the voltage.

6. The method as claimed in claim 5, wherein the “logic 1” of the binary communication input is determined by:
detecting the first binary signal (216) in the “set state” based on the modulation of the voltage below the high-low level (210) and in the “reset state” based on the modulation of the voltage above the high-high level (208), and
wherein the “logic 0” of the binary communication input is determined by:
detecting the first binary signal (216) in the “set state” based on the modulation of the voltage below the low-high level (212) and in the “reset state” based on the modulation of the voltage above the high-high level (214), and
detecting the second binary signal (218) in the “set state” based on the modulation of the voltage below the low-low level (214) and in the “reset state” based on the modulation of the voltage above the low-high level (212).

7. A voltage regulator (102), comprising:
at least one power pin (104, 106), wherein the at least one power pin (104, 106) is configured to:
receive a binary communication input, wherein the binary communication input is generated by modulating a voltage between a set of threshold levels (208-214),
wherein the set of threshold levels (208-214) are defined based on a voltage differential, and
wherein the voltage differential is determined based on a maximum tolerable voltage (202) and a minimum tolerable voltage (204) of the at least one power pin (104, 106) and a number of the threshold levels in the set of threshold levels (208-214).

8. The voltage regulator (102) as claimed in claim 7, wherein the input of the binary communication input configures an operational state from a plurality of operational states of the voltage regulator (102).

9. The voltage regulator (102) as claimed in claim 7, wherein the voltage differential is determined as a ratio of a difference between the maximum tolerable voltage (202) and the minimum tolerable voltage (204) and the number of threshold levels.

10. The voltage regulator (102) as claimed in claim 7, wherein the set of threshold levels (208-214) comprises:
a mid-level (206) defined as an average of the maximum tolerable voltage (202) and the minimum tolerable voltage (204);
two high levels (208, 210) and two low levels (212, 214) defined above and below the mid-level (206) respectively,
wherein the two high levels (208, 210) comprise: a high-high level (208) and a high-low level (210), and
wherein the two low levels (212, 214) comprise: a low-high level (212) and a low-low level (214).

11. The voltage regulator (102) as claimed in claim 10, wherein a "logic 1" and a "logic 0" of the binary communication input are represented based on a first set binary signals and a second set binary signals, and
wherein each of the first set of binary signals (200A) and the second set of binary signals (200B) include a first binary signal (216) and a second binary signal (218), and
wherein each of the first binary signal (216) and the second binary signal (218) are detected in a "set state" or a "reset state" based on the modulation of the voltage.

12. The voltage regulator (102) as claimed in claim 11, wherein the "logic 1" of the binary communication input is determined by:
detecting the first binary signal (216) in the "set state" based on the modulation of the voltage below the high-low level (210) and in the "reset state" based on the modulation of the voltage above the high-high level (208), and
wherein the "logic 0" of the binary communication input is determined by:
detecting the first binary signal (216) in the "set state" based on the modulation of the voltage below the low-high level (212) and in the "reset state" based on the modulation of the voltage above the high-high level, and
detecting the second binary signal (218) in the "set state" based on the modulation of the voltage below the low-low level (214) and in the "reset state" based on the modulation of the voltage above the low-high level (212).