Description:
FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)
1. Title of the invention – A RESETTABLE FAULT LATCH CIRCUIT FOR SHORT CIRCUIT AND OVERCURRENT PROTECTION IN ELECTRICAL APPLIANCES
2. Applicant(s)

(a) NAME: SAMARTH E-MOBILITY PRIVATE LIMITED

(b) NATIONALITY: INDIAN

(c) ADDRESS: PLOT NO.121, KALOL G.I.D.C., KALOL, GANDHINAGAR-382721 GUJARAT
3. PREAMBLE TO THE DESCRIPTION

The following specification particularly describes the invention and the manner in which it is to be performed.

 
A RESETTABLE FAULT LATCH CIRCUIT FOR SHORT CIRCUIT AND OVERCURRENT PROTECTION IN ELECTRICAL APPLIANCES

FIELD OF INVENTION:

The present invention relates to fault detection and protection circuits in electrical and electronic systems. More specifically, it pertains to a resettable fault latch circuit incorporating a microcontroller for detecting and responding to short circuit (SC) and overcurrent (OC) conditions. The invention provides a robust and noise-resistant fault latching mechanism with continuous monitoring and safe reset functionality, suitable for a wide range of electrical appliances and industrial applications.

BACKGROUND OF INVENTION:

The demand for reliable protection mechanisms in electrical appliances and electronic systems has grown significantly due to the increasing complexity and criticality of modern circuitry. Faults such as short circuits (SC) and overcurrent (OC) conditions can arise across a wide range of applications from consumer electronics and household appliances to industrial automation systems and embedded control units. These fault conditions, if not promptly and effectively addressed, can lead to malfunction, damage to components, reduced lifespan of the system, and in some cases, safety hazards such as fire or equipment failure.

In a typical electrical system, a fault event is identified when current levels exceed predefined operational thresholds. Such conditions often stem from external shorts, component failures, or unforeseen circuit behaviours. The rapid identification and interruption of current flow are crucial in minimizing the negative impact of these fault events. Protection strategies usually incorporate fault detection followed by a response mechanism that either limits or entirely disables power delivery to sensitive components.

Among various protection strategies, fault latching is a widely adopted technique where the system maintains a "fault state" once a fault is detected, thereby ensuring the circuit does not return to its regular operational state until the fault is acknowledged and cleared. However, most conventional fault latch circuits present several limitations that reduce their effectiveness and adaptability across varied use cases.

One significant drawback observed in many existing implementations is the lack of continuity in fault monitoring during the reset phase. In certain designs, the circuit disables fault detection when a reset operation is initiated. This creates a temporal blind spot, wherein new fault conditions can arise and remain unregistered. This deficiency is particularly problematic in systems that require persistent safety assurance, where any interruption in fault detection could compromise the entire operation.

Another major concern is the susceptibility of traditional latch circuits to erroneous triggers caused by electrical disturbances such as noise, transients, or fluctuations that typically occur during start up or high-speed switching. These disturbances can falsely simulate fault events, prompting the circuit to enter a latched state even when the system is functioning correctly. Such false fault activations not only disrupt normal operation but also lead to unnecessary downtime, reducing system efficiency and user confidence.

Moreover, existing latch circuits are often built using relatively complex arrangements involving multiple logic devices, timing components, and software intervention. This leads to increased circuit complexity, higher power consumption, and greater cost, which makes these solutions impractical for compact or low-cost applications. For instance, if the system undergoes a software reset or a controller reboot, the latch state may be unintentionally cleared, even if the original fault persists. Such vulnerabilities undermine the reliability of the protection scheme.

These challenges highlight the need for a simplified, robust, and effective fault protection circuit that ensures fast and reliable fault detection, secure fault latching, and safe reset functionality without compromising continuous monitoring or falling victim to false activations. A circuit that is capable of maintaining fault awareness throughout its operation cycle, including during the reset phase, and that offers noise immunity and reduced component complexity, is highly desirable across a broad spectrum of electrical and electronic systems.

This problem is evident in several prior art references. One such invention is disclosed in patent cited documents US20130154597A1 discloses a load-limiting circuit that includes a transistor switch controlled by a latching circuit. The system senses current exceeding a threshold and latches the transistor switch off to prevent damage. An external controller can reset the latch to resume operation.

Another prior art document US20110291634A1 discloses an overcurrent protection circuit that includes a determiner to assess whether the switch current exceeds a predetermined threshold. An OFF period setting counter adjusts the drive signal's timing based on the overcurrent state, effectively controlling the switching element's operation. However, the system's reliance on timing adjustments and counters introduces complexity and may not provide immediate response to sudden overcurrent events, potentially compromising protection efficacy.

Another prior art document CN219181187U discloses an overcurrent protection circuit comprising a current detection circuit, a voltage detection circuit, a state conversion circuit, and a power tube module. The system adjusts output current by comparing sampling current and voltage against reference values. While the design offers dual-mode operation, the complexity of multiple modules and the need for precise calibration may limit its applicability in simpler or cost-sensitive applications.

Another prior art document CN102651543B discloses a chip-scale overcurrent protection circuit that operates independently of the power supply module. It includes a heavy current switching module, an equal-proportion current detection module, a judgment module, and a self-start module. The design enhances safety and reliability, offering strong universality and low power consumption. However, its independence from the power supply module may necessitate additional considerations for integration into existing systems.

Another prior art document CN114755475A discloses a current detection circuit and overcurrent protection system that includes an acquisition conversion module, a threshold setting module, a comparison module, a latch module, and an output module. The system allows for accurate current detection with customizable threshold settings, enhancing flexibility. Nonetheless, the inclusion of multiple modules may increase the system's complexity and size, potentially limiting its use in compact applications.

The cited prior art demonstrates various approaches to overcurrent protection, each with its strengths and limitations. Common challenges include reliance on external controllers, complexity due to multiple modules, and potential synchronization issues during resets. These limitations underscore the need for a simplified, robust, and effective fault protection circuit that ensures fast and reliable fault detection, secure fault latching, and safe reset functionality without compromising continuous monitoring or falling victim to false activations. A circuit capable of maintaining fault awareness throughout its operation cycle, including during the reset phase, and offering noise immunity and reduced component complexity, is highly desirable across a broad spectrum of electrical and electronic systems.

However, the present invention offers a simplified and reliable fault latch circuit that directly addresses the shortcomings identified in the cited inventions. By incorporating a logic gate-based feedback mechanism and a noise-tolerant signal conditioning network, the circuit ensures continuous monitoring even during the reset phase, eliminating the vulnerability window. Unlike prior designs that depend heavily on microcontroller logic or multi-stage comparators, this invention uses minimal discrete components, reducing layout complexity and cost. The reset mechanism is deterministic and gated, ensuring it only activates when the system is verified to be in a healthy state, thereby preventing premature or unsafe reactivation. This design not only enhances reliability but also broadens compatibility with both analog and digital systems in safety-critical environments.

OBJECT OF THE INVENTION:

An object of the present invention is to provide a resettable fault latch circuit for detecting and maintaining fault conditions such as short circuit and overcurrent in electrical systems.

Another object of the present invention is to provide a fault latch circuit that holds the fault state latched after the fault signal disappears, until a controlled reset is performed.

Another object of the present invention is to include a noise filtering mechanism that prevents false latching due to transient noise, electrical disturbances, or startup conditions.

Another object of the present invention is to ensure continuous fault detection during the reset operation, preventing any interruption in monitoring.

Another object of the present invention is to provide a reset mechanism controlled externally, such as via a microcontroller, enabling secure and reliable clearing of the latched fault condition.

Another object of the present invention is to minimize the number of components required for the fault latch circuit, reducing cost and simplifying the design.

Another object of the present invention is to improve fault detection response time by optimizing signal processing within the circuit.

Another object of the present invention is to enhance immunity to electrical noise to ensure accurate fault detection under noisy operating conditions.

Another object of the present invention is to prevent the system from resuming operation until the fault condition is confirmed to be resolved, thereby enhancing safety.

Another object of the present invention is to provide a versatile and cost-effective fault protection solution applicable across a variety of electrical and electronic applications.

SUMMARY OF THE INVENTION:

This summary is provided to introduce a selection of concepts in a simplified form that are further disclosed in the detailed description of the invention. This summary is not intended to identify key or essential inventive concepts of the claimed subject matter, nor is it intended for determining the scope of the claimed subject matter.

The present invention relates to a resettable fault latch circuit for short circuit (SC) and overcurrent (OC) protection in electrical appliances.

The main aspect of the present invention is to provide a resettable fault latch circuit for short circuit and overcurrent protection in electrical appliances. The circuit comprises a fault detection unit configured to detect a fault condition in the electrical appliance, and a logic gate having a first input coupled to an output of the fault detection unit, a second input, and an output. The output of the logic gate is coupled to its second input through a feedback network, forming a feedback loop that maintains a fault state at the output of the logic gate when a fault condition is detected. The circuit further includes a reset unit coupled to the second input of the logic gate and configured to reset the fault state at the output in response to a reset signal.
Yet another aspect of the present invention is to provide a fault detection unit that comprises a shunt current sensing circuit, a voltage amplification circuit based on an operational amplifier, and a comparator.
Yet another aspect of the present invention is to provide a logic gate configured as an OR gate for the purpose of establishing the fault latching and reset functionality.
Yet another aspect of the present invention is to provide a feedback network comprising a resistive divider network including a resistor and a capacitor connected across the lower resistor of the divider. This forms a tunable deglitch circuit that prevents false fault latching during start-up or due to noise encountered during operation.
Yet another aspect of the present invention is to provide a reset unit comprising a switching device configured to momentarily ground the second input of the logic gate in response to the reset signal. This action breaks the feedback loop and resets the fault state at the output of the logic gate.
Yet another aspect of the present invention is to provide a unidirectional conduction block connected in series with the feedback network to ensure proper current flow and prevent unintended feedback in the circuit. The unidirectional conduction block may be implemented as a diode.
Yet another aspect of the present invention is to provide a reset signal generated by a microcontroller after confirming a healthy state of the electrical appliance, enabling controlled resetting of the latch circuit.
Yet another aspect of the present invention is to provide a reset unit configured to reset the fault state at the output of the logic gate while maintaining the fault detection capability of the fault detection unit.

BRIEF DESCRIPTION OF THE DRAWINGS:

The foregoing summary, as well as the following detailed description of the invention, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, exemplary constructions of
the invention is shown in the drawings. Components in the drawings are not necessarily to scale; emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that disclosure of such
drawings include disclosure of electrical components, electronic components or circuitry commonly used to implement such components.
Fig 1 represent the overall system diagram of the present invention.

Fig 2 represent the logic gate configuration of the present invention.

Fig 3 represent the feedback network configuration of the present invention.

Fig 4 represent the reset unit configuration of the present invention.

DETAILED DESCRIPTION OF THE INVENTION:

Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific functional and structural details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

The present invention overcomes the aforesaid drawbacks of conventional protection in electrical appliances. The objects, features, and advantages of the present invention will now be described in greater detail. Also, the following description includes various specific details and is to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that: without departing from the scope of the present disclosure and its various embodiments there may be any number of changes and modifications described herein.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It must also be noted that as used herein and in the appended claims, the singular forms "a", "an," and "the" include plural references unless the context clearly dictates otherwise. Although any systems and methods similar or equivalent to those described herein can be used in the practice or testing of embodiments of the present invention, the preferred, systems are now described.

As per the detailed embodiment of the present invention, a resettable fault latch circuit for short circuit (SC) and overcurrent (OC) protection in electrical appliances, the circuit comprising: a fault detection unit (101) configured to detect a fault condition in the electrical appliance; a logic gate (102) having a first input (102a) coupled to an output of the fault detection unit (101), a second input (102b), and an output (102c); characterized in that, the output (102c) of the logic gate (102) is coupled to the second input (102b) through a feedback network (103), forming a feedback loop that maintains a fault state at the output (102c) of the logic gate (102) when a fault condition is detected by the fault detection unit (101); and the circuit further comprises a reset unit (104) coupled to the second input (102b) of the logic gate (102) and configured to reset the fault state at the output (102c) in response to a reset signal (105).

As per the detailed embodiment of the present invention, the fault detection unit (101) comprises a shunt current sensing circuit (101a), a voltage amplification circuit (101b) based on an operational amplifier, and a comparator (101c).

As per the detailed embodiment of the present invention, the logic gate (102) is an OR gate.

As per the detailed embodiment of the present invention, the feedback network (103) comprises a resistive divider network including a resistor R1 (103a), a resistor R2 (103c) and a capacitor (103b). a capacitor (103b) connected across the resistor R2 (103c) of the resistive divider network, forming a tunable deglitch circuit that prevents false fault latching during start-up or due to noise during operation.

As per the detailed embodiment of the present invention, the reset unit (104) comprises a switching device (104a) configured to momentarily ground the second input (102b) of the logic gate (102) in response to the reset signal (105), thereby breaking the feedback loop and resetting the fault state at the output (102c) of the logic gate (102).

As per the detailed embodiment of the present invention, the circuit further comprises a unidirectional conduction block (106) connected in series with the feedback network (103) to ensure proper current flow and prevent unintended feedback in the circuit, wherein the unidirectional conduction block (106) is a diode.

As per the detailed embodiment of the present invention, the reset signal (105) is generated by a microcontroller (107) after confirming a healthy state of the electrical appliance.

As per the detailed embodiment of the present invention, the reset unit (104) is configured to reset the fault state at the output (102c) of the logic gate (102) while maintaining the fault detection capability of the fault detection unit (101).

As per the detailed embodiment of the present invention, the system includes a fault detection unit (101), which comprises a shunt current sensing circuit (101a) for detecting current through a load. The sensed voltage is then passed to a voltage amplification circuit (101b) to boost the signal level appropriately. The amplified signal is subsequently fed into a comparator (101c) which compares it against a predefined threshold to detect abnormal conditions such as overcurrent or short circuits.

As per the detailed embodiment of the present invention, the output of the comparator (101c) is provided to the first input (102a) of a logic gate (102), specifically configured to function as a fault latch mechanism. Upon detection of a fault condition, the output of the comparator goes high, triggering the output of the logic gate and initiating the fault latching operation.

As per the detailed embodiment of the present invention, the logic gate (102) is configured with a second input (102b) that receives a feedback signal from its output (102c) through a feedback network (103). This network consists of a resistor (103a) and a capacitor (103b) connected in such a way as to form a tunable deglitch filter. This prevents transient signals or startup noise from falsely triggering the latch.

As per the detailed embodiment of the present invention, the feedback network (103) plays a vital role in maintaining the latched fault condition by ensuring that the second input (102b) of the logic gate continues to receive a logic high signal even if the initial fault signal from the comparator disappears momentarily. This persistent condition at the logic gate output ensures reliable latching until a manual or automated reset is performed.

As per the detailed embodiment of the present invention, a reset unit (104) is configured to reset the latched state by momentarily grounding the second input (102b) of the logic gate. The reset unit includes a switching device (104) that, when activated by a reset signal (105) from a controller, temporarily interrupts the feedback loop, allowing the logic gate output (102c) to return to its default low state.

As per the detailed embodiment of the present invention, a unidirectional conduction block (106), such as a diode, is used to prevent undesired signal flow in the feedback loop or control path. This component ensures that current flows only in the intended direction, thereby preventing interference or malfunction of the latch or reset mechanisms.

As per the detailed embodiment of the present invention, a microcontroller (107) oversees the operation of the entire fault protection system. It monitors the output of the logic gate (102) and, upon detection of a fault, disables the external power control elements (such as other switching devices controlling the load) to ensure system protection. The microcontroller also generates the reset signal (105) when the system has returned to normal operating conditions.

As per the detailed embodiment of the present invention, the circuit achieves efficient fault isolation and system reset using a minimal set of components: a single logic gate (102), a few passive elements (resistor and capacitor), a switching device (104), and a standard comparator (101c), resulting in reduced cost, board space, and complexity while maintaining robust performance.

As per the detailed embodiment of the present invention, the output of the logic gate (102c) is further connected to a microcontroller (107) and a solid-state switching interface (109), wherein the microcontroller (107) is configured to send a signal to the solid-state switching interface (109) to disconnect the load upon detection of a fault condition.

As per the detailed embodiment of the present invention, the solid-state switching interface (109) is further configured to operate based on the fault signal, and during fault conditions, the solid-state switching interface (109) is capable of independently isolating the load without receiving a signal from the microcontroller (107), thereby providing an additional layer of protection.

As per the detailed embodiment of the present invention, the truth table of the logic gate (102) can be defined such that when both inputs are low, the output remains low, indicating a normal state. When a high signal is received at the first input (102a) due to a fault, the output (102c) latches high. The feedback to the second input (102b) ensures that the latch remains active even if the fault clears momentarily. Only the activation of the reset unit (104), through the reset signal (105), breaks this loop.

As per the detailed embodiment of the present invention, the use of the capacitor (103b) in the feedback network (103) is essential for noise suppression. It filters out high-frequency disturbances during transient events such as power-on or load switching, ensuring that only genuine fault conditions lead to latch activation.

As per the detailed embodiment of the present invention, effective latching behavior is achieved by carefully configuring the feedback path resistors. Specifically, resistor R2 (103c) is chosen to be much larger than resistor R1 (103a), satisfying the condition R2 >> R1. This configuration allows the highest possible voltage from the fault signal originating from the logic gate output (102c) to be applied to second input (102b) of the logic gate. The voltage at second input (102b) stays above the gate’s logic threshold, thereby ensuring a stable and reliable latch state. Consequently, the latch continues to hold the fault condition even after first input of the logic gate (102a) (the initial fault signal) is removed, and it remains latched until a separate reset signal is applied to deactivate the latch.

As per the detailed embodiment of the present invention, the entire system provides real-time fault detection, fast response, and automatic isolation of the faulted section. The combined function of the fault detection unit (101), logic gate (102), feedback network (103), reset unit (104), unidirectional conduction block (106), and microcontroller (107) ensures continuous monitoring and user safety with optimized hardware and software integration.
As per the detailed embodiment of the present invention, the output signal from the Logic Gate (102c) is connected to a solid-state switching interface (109) and microcontroller (107), which is responsible for isolating the load during fault conditions. This interface utilizes power semiconductor devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Silicon-Controlled Rectifiers (SCRs), Triacs, or Gate Turn-Off Thyristors (GTOs). Unlike mechanical switches, these solid-state devices do not involve moving contacts, thereby enabling a significantly faster switching response and enhanced reliability.
As per the detailed embodiment of the present invention, under normal operating conditions, the solid-state switching interface (109) maintains a conductive path, allowing uninterrupted current flow to the load. However, upon the detection of a fault and the activation of the latch circuit, the logic gate output triggers the solid-state switch interface (109) to rapidly interrupt the power flow, effectively isolating the load from the supply. The rapid disconnection is crucial for protecting sensitive components and preventing further system damage.
As per the detailed embodiment of the present invention, the output from the logic gate (102c) is used to indicate a fault condition. When a fault is detected, the microcontroller (107) receives this signal and then sends a command to the solid-state switching interface (109) to disconnect the load from the power supply. the solid-state switching interface (109) is configured to receive fault signal independently form logic gate (102c) and isolate the load even without receiving signal from the microcontroller (107). This provides an extra level of safety and ensures the load is quickly disconnected during a fault. Once the fault is cleared, the microcontroller (107) can send another signal to turn the switch back on and restore normal operation.

The technical features of the present invention are further elaborately shown and explained through the figures of the invention, providing a comprehensive understanding of its design and functionality.

FIG. 1 illustrates the overall block diagram of a resettable fault latch circuit for providing short circuit (SC) and overcurrent (OC) protection in electrical appliances. The system comprises a fault detection unit (101), a logic gate (102), a feedback network (103), a reset unit (104), a unidirectional conduction block (106), a microcontroller (107), and a solid-state switching interface (109).

The fault detection unit (101) receives inputs from a shunt current sensing circuit (101a) and a voltage amplification circuit (101b). These inputs are processed by a comparator (101c) to determine the presence of a fault condition. When a fault is detected, the comparator generates a high-level output signal.

This signal is sent to the first input (102a) of the logic gate (102), which is preferably an OR gate. The second input (102b) of the logic gate receives feedback through the feedback network (103), creating a feedback loop. This loop ensures that once a fault is detected, the output (102c) of the logic gate remains latched in a fault state.

The feedback network (103) is configured between the output (102c) and second input (102b) of the logic gate, and includes a resistor-capacitor (RC) network. A unidirectional conduction block (106), such as a diode, is connected in series with the feedback loop to allow current to flow only in the intended direction and prevent reverse feedback.

The microcontroller (107) evaluates the fault condition and generates a reset signal (105) when the fault is cleared. This signal activates the reset unit (104), which includes a switching device (104a). The switching device momentarily grounds the second input (102b) of the logic gate (102), breaking the feedback loop and resetting the fault latch.

The output of the logic gate (102c) is connected to the solid-state switching interface (109), which acts to disconnect or isolate the load in the presence of a fault and reconnect it after reset, ensuring safe operation of the appliance.

FIG. 2 depicts the logic gate (102). The logic gate is implemented as an OR gate with two inputs: the first input (102a) receives the fault signal from the comparator (101c), and the second input (102b) is connected to the output (102c) via the feedback network (103).

The output (102c) of the logic gate becomes high when a fault is detected and remains high due to the feedback path, thereby latching the fault condition.

The feedback network (103) in this configuration comprises a resistor R1 (103a), a resistor R2 (103c) and capacitor (103b) forming a deglitch circuit that smooths out transient noise and prevents false latching. The feedback loop maintains the logic gate in its latched state until the reset path is activated.

The reset unit (104) intervenes by grounding the second input (102b) through the switching device (104a) upon receiving a reset signal (105), effectively breaking the feedback loop. This causes the output (102c) of the OR gate to go low, resetting the fault condition.

FIG. 3 shows the internal configuration of the feedback network (103), which forms the deglitch and hold circuit for the logic gate. The feedback network comprises a a resistor R1 (103a), a resistor R2 (103c) and a capacitor (103b), connected in a parallel arrangement.

The resistor R1 (103a) is part of a voltage divider that controls the voltage level fed back into the second input (102b) of the OR gate. The capacitor (103b) is placed across the resistor R2 (103c) to introduce a time constant, which helps filter out spurious signals or momentary noise that could otherwise result in false latching.

The lower terminal of both the resistor R2 (103c) and capacitor (103b) is grounded, ensuring proper reference potential and stability of the signal. This configuration helps in implementing a tunable delay, avoiding false triggering during start-up conditions or due to electrical noise in the environment.

FIG. 4 illustrates the reset unit (104) and its operation. The unit includes a switching device (104a), such as an MOSFET, which is configured to momentarily short the second input (102b) of the OR gate to ground when triggered.

The gate of the switching device (104a) is controlled by a reset signal (105) generated by the microcontroller (107). Upon activation of the reset signal, the MOSFET turns on, allowing current to flow to ground and momentarily pulling the logic gate’s second input (102b) low.

This breaks the feedback loop between the output (102c) and input (102b) of the OR gate, thereby unlatching the output and resetting the fault state. Once the MOSFET is turned off, normal monitoring resumes, and the system can detect and respond to new fault conditions.

The reset unit thus ensures that the system remains protected yet capable of recovery after safe conditions are confirmed by microcontroller (107).

Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the illustrative examples, make and utilize the present invention and practice the claimed methods. It should be understood that the foregoing discussion and examples merely present a detailed description of certain preferred embodiments. It will be apparent to those of ordinary skill in the art that various modifications and equivalents can be made without departing from the scope of the invention.

LIST OF REFRENCE NUMERALS
Fault detection unit (101)
Shunt current sensing circuit (101a)
voltage amplification circuit (101b)
Comparator (101c)
Logic gate (102)
First input of the logic gate (102a)
Second input of the logic gate (102b)
Output of the logic gate (102c)
Feedback network (103)
Resistor R1 (103a)
Capacitor (103b)
Resistor R2 (103c)
Reset unit (104)
Switching device (104a)
Reset signal (105)
Unidirectional conduction block (106)
Microcontroller (107)
solid-state switching interface (109)
, C , Claims:Claims:
We claim;
1. A resettable fault latch circuit for short circuit (SC) and overcurrent (OC) protection in electrical appliances, the circuit comprising:
a. a fault detection unit (101) configured to detect a fault condition in the electrical appliance;
b. a logic gate (102) having a first input (102a) coupled to an output of the fault detection unit (101), a second input (102b), and an output (102c);
characterized in that,
the output (102c) of the logic gate (102) is coupled to the second input (102b) through a feedback network (103), forming a feedback loop that maintains a fault state at the output (102c) of the logic gate (102) when a fault condition is detected by the fault detection unit (101); and the circuit further comprises a reset unit (104) coupled to the second input (102b) of the logic gate (102) and configured to reset the fault state at the output (102c) in response to a reset signal (105).

2. The resettable fault latch circuit as claimed in claim 1, wherein the fault detection unit (101) comprises a shunt current sensing circuit (101a), a voltage amplification circuit (101b) based on an operational amplifier, and a comparator (101c).

3. The resettable fault latch circuit as claimed in claim 1, wherein the logic gate (102) is an OR gate.

4. The resettable fault latch circuit as claimed in claim 1, wherein the feedback network (103) comprises a resistive divider network including a resistor R1 (103a), a resistor R2 (103c) and a capacitor (103b). a capacitor (103b) connected across the resistor R2 (103c) of the resistive divider network, forming a tunable deglitch circuit that prevents false fault latching during start-up or due to noise during operation.

5. The resettable fault latch circuit as claimed in claim 1, wherein the reset unit (104) comprises a switching device (104a) configured to momentarily ground the second input (102b) of the logic gate (102) in response to the reset signal (105), thereby breaking the feedback loop and resetting the fault state at the output (102c) of the logic gate (102).

6. The resettable fault latch circuit as claimed in claim 1, further comprising a unidirectional conduction block (106) connected in series with the feedback network (103) to ensure proper current flow and prevent unintended feedback in the circuit, wherein the unidirectional conduction block (106) is a diode.

7. The resettable fault latch circuit as claimed in claim 1, wherein the reset signal (105) is generated by a microcontroller (107) after confirming a healthy state of the electrical appliance.

8. The resettable fault latch circuit as claimed in claim 1, wherein the reset unit (104) is configured to reset the fault state at the output (102c) of the logic gate (102) while maintaining the fault detection capability of the fault detection unit (101).

9. The resettable fault latch circuit as claimed in any of the preceding claims, wherein the output of the logic gate (102c) is further connected to a microcontroller (107) and a solid-state switching interface (109), wherein the microcontroller (107) is configured to send a signal to the solid-state switching interface (109) to disconnect the load upon detection of a fault condition.

10. The resettable fault latch circuit as claimed in claim 9, wherein the solid-state switching interface (109) is further configured to operate based on the fault signal, and during fault conditions, the solid-state switching interface (109) is capable of independently isolating the load without receiving a signal from the microcontroller (107), thereby providing an additional layer of protection.

Dated this 26th June 2025