Description:
FORM 2
THE PATENTS ACT, 1970 (39 OF 1970)
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)
1. Title of the invention – A RESETTABLE BATTERY FAULT PROTECTION CIRCUIT IN BMS USING SINGLE LOGIC GATE AND TUNABLE DEGLITCH CIRCUIT
Applicant(s)

NAME: SAMARTH E-MOBILITY PRIVATE LIMITED

NATIONALITY: INDIAN

ADDRESS: PLOT NO.121, KALOL G.I.D.C., KALOL, GANDHINAGAR-382721 GUJARAT
3. PREAMBLE TO THE DESCRIPTION

The following specification particularly describes the invention and the manner in which it is to be performed.

 
A RESETTABLE BATTERY FAULT PROTECTION CIRCUIT IN BMS USING SINGLE LOGIC GATE AND TUNABLE DEGLITCH CIRCUIT

FIELD OF INVENTION:

The present invention relates to battery management systems (BMS), and more specifically to a resettable battery fault protection circuit designed to detect and manage short circuit and overcurrent conditions. More particularly focuses on the use of a single logic gate in conjunction with a tunable deglitch circuit to achieve reliable fault latching and safe reset operations. It aims to protect battery packs and associated circuitry by interrupting abnormal current flow and maintaining system monitoring throughout the fault handling process.

BACKGROUND OF INVENTION:

Battery Management Systems (BMS) are essential in modern battery-powered applications, such as electric vehicles, renewable energy systems, consumer electronics, and industrial power systems. A BMS monitors and controls critical parameters, including voltage, current, temperature, and state of charge, to ensure the safe and efficient operation of the battery pack. Among the most important functions of a BMS is the protection mechanism against fault conditions, such as short circuit (SC) and overcurrent (OC) events. These faults can have severe consequences, including battery damage, overheating, and failure of associated components like charge and discharge MOSFETs. If undetected or improperly managed, such faults can lead to catastrophic failure of the battery and the entire system.

SC and OC events typically occur when the current flowing through the system exceeds safe thresholds, potentially causing excessive heat generation and damage to the battery cells and other system components. Fast and accurate detection of these faults is crucial for mitigating damage and ensuring system safety. When an SC or OC fault is detected, the BMS typically interrupts the current flow by turning off the charge and discharge MOSFETs, isolating the battery from the fault condition. This helps protect the battery and other components from immediate damage.

However, existing SC and OC protection mechanisms face a number of challenges. One of the key issues is the time it takes for the system to detect and respond to a fault. While some fault detection circuits are able to respond quickly, the severity of certain fault events, such as short circuits, can cause irreversible damage within a fraction of a second. In these cases, the protective actions taken by the BMS may occur too late to prevent damage, underscoring the need for fast detection and response times.

Additionally, when a fault occurs, it is crucial that the system enters a safe state and remains in that state until it is confirmed that the fault has been cleared. A fault latch mechanism is typically employed to hold the system in a protected state until diagnostic procedures confirm whether the fault has been resolved. This ensures that the system does not resume charging or discharging if the fault persists. However, conventional latch circuits have several drawbacks.

A major problem with existing latch circuits is that once a fault is detected and latched, the fault detection system often becomes inactive during the reset phase. This means that if a new fault occurs while the system is being reset, the fault may go undetected, potentially leading to further damage. The reset process, in particular, poses a significant challenge in maintaining continuous fault detection. If the fault detection mechanism is temporarily disabled during reset, the system becomes vulnerable to undetected faults during this critical phase.

Furthermore, existing circuits can suffer from false fault latching due to electrical noise, power fluctuations, or transients that occur during system start-up or normal operation. These false positives can cause unnecessary system shutdowns, reducing reliability and availability. For example, a brief transient or noise spike might trigger a fault condition, causing the system to enter a protective state even though no actual fault exists. This leads to unnecessary interruptions in system operation and reduces the overall efficiency of the battery management system.

Another problem with conventional fault latch designs is their complexity and the increased component count. Many existing circuits require multiple logic gates, flip-flops, and additional control circuitry to handle fault latching and reset functions. This increases the design complexity, power consumption, and cost of the system, making it less suitable for applications that require a simple, reliable, and cost-effective solution.

In many existing circuits, logic gates such as AND, OR, and NOR are used in combination with external latches or microcontroller logic to determine and maintain fault states. The issue with such designs lies in their dependency on synchronized operation with the rest of the control circuitry, especially the microcontroller or digital controller. During a system reset—whether triggered intentionally through software or due to an external watchdog mechanism—the fault latch circuits can be inadvertently cleared. This leaves the battery unprotected during the reset cycle, creating a potentially unsafe window of operation where faults may go undetected or unmitigated.

This problem is evident in several prior art references. One such invention is disclosed in patent cited documents CN114362726A discloses a battery overcurrent protection circuit that uses a logic gate-based fault detection mechanism along with a delay circuit to improve response time and accuracy. However, the approach depends on a layered logic network and multiple discrete components, which increases design complexity. The patent also indicates that without proper synchronization with the main controller, the circuit may fail to maintain a stable latched state, particularly during reset events or power cycling.

Another prior art document CN104660230A describes a protection circuit that integrates multiple comparators and a control unit for overcurrent detection. While this setup enhances precision, it follows a sequence-dependent logic operation which can introduce latency and does not inherently preserve the fault state during system resets. The circuit’s response is tightly coupled with the controller’s timing, meaning that if the controller resets, the protective logic might unintentionally re-enable the load despite the presence of a persisting fault.

Another prior art document CN210867180U provides a structural improvement by offering a protection device that monitors current flow and controls switching through logical signal transitions. Although this circuit detects and acts upon overcurrent events, it lacks a built-in latching mechanism that remains engaged independently of the controller’s operation. Without such a mechanism, the protection state may be lost if the system undergoes a reset or if there is fluctuation in control signals, making the design unsuitable for safety-critical applications requiring persistent fault isolation.

Several prior art document have addressed aspects of SC and OC protection in battery systems, but they often fall short in terms of simplicity and continuous protection during reset phases. For example, prior art document US9257729B2 discusses a method for detecting and responding to potentially hazardous over-current due to internal short circuits in electric vehicle battery packs. While it emphasizes the importance of detecting such conditions, the approach involves complex detection mechanisms that may not be cost-effective or easily integral into all BMS designs.

Another prior art document, US10811869B2 focuses on overcurrent protection for battery systems, proposing intricate circuitry to manage fault conditions. While effective, the complexity of the design can be a barrier to widespread adoption, particularly in applications where space and cost constraints are critical.

Another prior art document US11567145B2, which presents a system for early detection of internal short circuits in battery cells. Although it offers proactive fault detection, the implementation relies on multiple components and does not address the need for a simplified latching mechanism that maintains protection during reset operations.

The problem associated with the available prior art depend heavily on microcontroller-based logic and complex arrangements for fault detection and recovery, making them vulnerable to failure in the event of microcontroller malfunction or system reset. Furthermore, such systems often require numerous components, increasing design complexity, cost, and susceptibility to failure. The absence of a persistent fault latch mechanism means that fault conditions may be inadvertently cleared during system resets, potentially compromising safety. Additionally, many existing solutions lack effective measures to prevent false fault triggering due to transient noise, resulting in reduced reliability. These limitations make current fault control systems unsuitable for safety-critical applications where continuous protection, low component count, and fail-safe operation are imperative.

The present invention provides a resettable fault latch circuit that uses minimal components including an OR gate, current sensing resistor, amplifier, and comparator. It retains fault conditions across system resets and enables fault recovery only after safe conditions are verified. A tunable deglitch block filters out transient disturbances, ensuring only genuine faults are latched, improving system safety, reliability, and cost-efficiency.

OBJECT OF THE INVENTION:

The primary object of the present invention is to provide a resettable battery fault protection circuit in BMS using single logic gate and tunable deglitch circuit for short circuit (SC) and overcurrent (OC) protection in battery management systems (BMS), ensuring the system enters a safe state upon detecting fault conditions.
Yet another object of the present invention is to maintain the fault condition using a single OR gate, even after the fault signal disappears, thereby guaranteeing continued system protection until a diagnostic confirms recovery.

Yet another object of the present invention is to enable fault latching through a feedback network incorporating a tunable deglitch block that ensures stable operation and prevents false latching due to noise or startup transients.

Yet another object of the present invention is to achieve continuous fault monitoring during the reset process, with the first input of the OR gate remaining active, thereby avoiding undetected SC or OC faults during fault recovery.

Yet another object of the present invention is to implement a microcontroller-controlled fault reset mechanism using a switching element to ground the second input of the OR gate, allowing precise and reliable fault reset while maintaining detection capability.

Yet another object of the present invention is to minimize component count and simplify the protection circuit design by using a single logic gate and a few passive components, thereby reducing manufacturing complexity and cost.

Yet another object of the present invention is to enhance the response time of fault detection by optimizing the delays associated with amplification, comparison, logic switching, and passive filtering components.

Yet another object of the present invention is to provide robust noise immunity through the integration of a tunable deglitch block, ensuring reliable operation in electrically noisy environments.

Yet another object of the present invention is to ensure safe operation of the BMS by preventing further charging or discharging until the system is verified to be in a healthy state post-fault.

Yet another object of the present invention is to offer a reliable and cost-effective protection mechanism for battery systems that enhances safety, reduces design complexity, and improves overall system reliability.

SUMMARY OF THE INVENTION:

This summary is provided to introduce a selection of concepts in a simplified form that are further disclosed in the detailed description of the invention. This summary is not intended to identify key or essential inventive concepts of the claimed subject matter, nor is it intended for determining the scope of the claimed subject matter.

The present invention relates to a resettable battery fault protection circuit in BMS using single logic gate and tunable deglitch circuit.

The main aspect of the present invention is to provide a resettable battery fault protection circuit in BMS using single logic gate and tunable deglitch circuit, comprising said battery management system having at least one current sensing element configured to sense the current flowing through a battery pack and to generate a sensed voltage (Vsh) across a shunt resistor, the sensed voltage being proportional to the current flowing through the shunt resistor. plurality of control switch being capable of controlling the current flowing through said battery pack. a protection system being capable of detecting the fault in said battery pack. Wherein said protection system comprising a signal conditioning and amplifier system being configured to amplify the sensed voltage (Vsh) and generate a conditioned sensed voltage (Vo) suitable for fault detection a reference voltage generator unit being capable of generating the reference voltage which being compared with the conditioned sensed voltage (Vo) using a comparator. a comparator being capable to generate a fault indication signal when the conditioned sensed voltage (Vo) exceeds the reference voltage (Vref). a resettable fault latch unit having single logic gate and a feedback control unit. said logic gate having atleast two inputs and one output the logic gate has an input A configured to receive a fault indication signal generated by a comparator, an input B connected to a feedback network and a fault reset unit, and an output connected to an input of the feedback control unit, microcontroller and the Gate Driving Logic Unit. said feedback control unit having signal flow control element, the feedback network and fault reset unit. the feedback network having at least one resistor and at least one capacitor arrangement forming a tunable deglitch circuit. the fault reset unit being capable of resetting the input B, the fault reset unit having a microcontroller controlled switching element configured to receive a reset control signal from a microcontroller and momentarily ground the input B of the logic gate to release the latched fault condition.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit wherein the signal flow control element is configured to ensure unidirectional current flow and prevent feedback disturbances.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit for a Battery Management System (BMS), which incorporates short circuit (SC) and overcurrent (OC) protection using a minimalistic and efficient logic gate-based fault latch system. The circuit enables rapid detection of fault conditions through current sensing, amplification, and comparison against a predefined threshold, followed by automatic interruption of battery current flow via charge and discharge control switches.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit that utilizes a single OR gate for implementing the fault latch mechanism. The OR gate receives the fault indication signal from the comparator at its first input and maintains the latched fault condition by feeding its output back to the second input through a feedback control unit, which includes a tunable deglitch circuit to enhance system stability and noise immunity.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit wherein the feedback control unit comprises a resistor-capacitor (RC) network forming a tunable deglitch block. The capacitor across the lower resistor helps in filtering spurious transitions or transient signals that may arise during startup or under noisy operational environments, thereby preventing false latching of the fault condition.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit wherein the latched fault state is held even after the fault signal at the OR gate’s first input is removed, ensuring that the system remains in a protected state until a diagnostic evaluation is completed and a healthy system condition is confirmed.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit wherein the reset operation is performed by a latch release unit comprising a switching element that momentarily grounds the second input of the OR gate upon receiving a reset signal from the microcontroller. This breaks the latch condition without disabling fault detection, as the first input remains active throughout the reset process.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit that maintains fault detection capability during the reset process, enabling continued monitoring of the battery for SC or OC events even as the latched fault condition is being cleared.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit that interfaces the OR gate’s output with a gate driving logic unit controlling the charge and discharge MOSFETs. Upon detection and latching of a fault condition, the MOSFETs are turned OFF to isolate the battery from load and charger, thereby protecting both the battery and system components.
Yet another aspect of the present invention is to provide the resettable battery fault protection circuit which offers advantages such as fast fault detection response time, reduced component count, simplified architecture, and cost-effective implementation, thereby enhancing the overall safety, reliability, and performance of the Battery Management System.
BRIEF DESCRIPTION OF THE DRAWINGS:

The foregoing summary, as well as the following detailed description of the invention, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, exemplary constructions of
the invention is shown in the drawings. Components in the drawings are not necessarily to scale; emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that disclosure of such
drawings include disclosure of electrical components, electronic components or circuitry commonly used to implement such components.
Fig 1 is an overall circuit of the present invention.

Fig 2 is a protection system diagram of the present invention.

DETAILED DESCRIPTION OF THE INVENTION:

Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific functional and structural details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

The present invention overcomes the aforesaid drawbacks of conventional battery fault protection circuit. The objects, features, and advantages of the present invention will now be described in greater detail. Also, the following description includes various specific details and is to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that: without departing from the scope of the present disclosure and its various embodiments there may be any number of changes and modifications described herein.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It must also be noted that as used herein and in the appended claims, the singular forms "a", "an," and "the" include plural references unless the context clearly dictates otherwise. Although any systems and methods similar or equivalent to those described herein can be used in the practice or testing of embodiments of the present invention, the preferred, systems are now described.

Throughout the invention, the Fault Indication Signal and (V_F1) are same unless and otherwise defined.

Throughout the invention, the feedback input, and (V_F2) are same unless and otherwise defined.

Throughout the invention, the BMS is Battery Management System.

As per the detailed embodiment of the present invention a resettable battery fault protection circuit in BMS using single logic gate and tunable deglitch circuit, comprising said battery management system having at least one current sensing element (101) configured to sense the current flowing through a battery pack (200) and to generate a sensed voltage (Vsh) across a shunt resistor, the sensed voltage being proportional to the current flowing through the shunt resistor. Plurality of control switch (114, 115) being capable of controlling the current flowing through said battery pack (200). a protection system (500) being capable of detecting the fault in said battery pack (200). Wherein said protection system (100) comprising a signal conditioning and amplifier system (102) being configured to amplify the sensed voltage (Vsh) and generate a conditioned sensed voltage (Vo) suitable for fault detection a reference voltage generator unit (104) being capable of generating the reference voltage which being compared with the conditioned sensed voltage (Vo) using a comparator (103). a comparator (103) being capable to generate a Fault Indication Signal when the conditioned sensed voltage (Vo) exceeds the reference voltage (Vref). a resettable fault latch unit (300) having single logic gate (301) and a feedback control unit (302). said logic gate (301) having atleast two inputs and one output the logic gate (301) has an input A (301a) configured to receive a fault indication signal generated by a comparator (103), an input B (301b) connected to feedback control unit (302), and an output (301c) connected to an input of the feedback control unit (302), microcontroller (110) and the Gate Driving Logic Unit (400). said feedback control unit (302) having signal flow control element (113), the feedback network (107) and fault reset unit (108). the feedback network (107) having resistor R1 (111a), resistor R2 (111c) and atleast one capacitor (111b) arrangement forming a tunable deglitch circuit. the fault reset unit (108) being capable of resetting the input B (301b), the fault reset unit (108) having a microcontroller (110) controlled switching element (112) configured to receive a reset control signal from a microcontroller (110) and momentarily ground the input B (310b) of the logic gate (301) to release the latched fault condition.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the logic gate (301) implemented using a single logic gate (301), wherein the single logic gate (301) is an OR gate.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the tunable deglitch circuit of the feedback network (107) being configured to filter spurious transitions and prevent false fault latching during start up or due to noise during operation.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the fault reset unit (108) includes a controllable switching element (112) configured to momentarily ground the input B (301b) of the logic gate (300) upon receiving a reset control signal from a microcontroller (110), thereby releasing the latched fault condition.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the switching element (112) is a metal-oxide-semiconductor field-effect transistor (MOSFET), a gate terminal of which is driven by the microcontroller (110) to perform the fault reset operation.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the signal flow control element (113) being positioned between the output (301c) of the logic gate (301) and the feedback network (107).
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the signal flow control element (113) is configured to ensure unidirectional current flow and prevent feedback disturbances, thereby maintaining proper fault detection and preventing disruption of the fault state during the reset process.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein 1. the fault detection remains operational during the reset process due to the logical characteristics of the OR gate (301), wherein the first input (301a) of the OR gate continues to receive the main fault indication signal independently of the reset operation performed on the second input (301b), thereby ensuring uninterrupted fault monitoring.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the ability of fault detection to remain operational during the reset process stems from the inherent characteristic of the OR gate (301). The first input (301a) of the OR gate continuously receives the real-time fault indication signal generated by the comparator (103). As long as this input remains in a high logic state, the output (301c) of the OR gate also remains high, regardless of the logic level at the second input (301b). During the reset operation, the microcontroller (110) momentarily grounds the second input (301b) via the latch release unit (108) to break the latched fault condition. However, this reset action does not interfere with ongoing fault detection because the first input (301a) remains active. Therefore, if a genuine fault persists, the output (301c) continues to indicate a fault, ensuring that the protection system (500) remains responsive and reliable throughout the reset process.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the feedback control unit (302) is capable of maintaining the fault state by holding the output (301c) in a fault-indicating condition even after the Fault Indication Signal becomes inactive, thereby ensuring that the system remains in a protected state until reset by the microcontroller (110), wherein the reset signal is generated by the microcontroller (110) after performing diagnostics to ensure a healthy state of the system.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein the microcontroller (110) is configured to transmit a control signal to the gate driving logic unit (400) for selectively disabling or enabling both the charge control switch (114) and the discharge control switch (115), based on the detection and clearance of a fault condition.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit, the gate driving logic unit (400) is configured to disable a charge control switch (114) and a discharge control switch (115) upon receiving the latched fault signal or a control signal from the microcontroller (110).
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein upon detection of a fault condition, both the charge control switch (114) and the discharge control switch (115) are turned OFF to disconnect the battery pack from the load (600) and charger, wherein the charge control switch (114) is configured to disable charging current, and the discharge control switch (115) is configured to disable discharging current flow.
As per the detailed embodiment of the present invention the resettable battery fault protection circuit wherein upon detection of a fault condition, the microcontroller (110) is configured to transmit a control signal to the gate driving logic unit (400), and concurrently, the latched fault signal from the OR gate (301) is supplied to the gate driving logic unit (400), wherein the gate driving logic unit (400) is adapted to disable both the charge control switch (114) and the discharge control switch (115), thereby isolating the battery pack (200) from an external charger and load (600), and wherein the charge control switch (114) and discharge control switch (115) remain disabled until the microcontroller (110) issues a reactivation signal upon verifying clearance of the fault condition.
As per the detailed embodiment of the present invention the feedback network (107) of the latch circuit is designed to ensure reliable operation during fault detection and reset conditions. During the reset process, when the feedback input (Input B) of the logic gate is momentarily grounded by the microcontroller (110) or an external control signal, the circuit configuration prevents current from being sourced from the output of the logic gate. This is achieved by incorporating a resistor R1 (111a) of suitable value between the output and the feedback input, thereby ensuring that the logic gate output does not interfere with the reset operation.
As per the detailed embodiment of the present invention the battery management system includes at least one current sensing element (101) configured to sense the current flowing through the battery pack (200). The current sensing element is capable of detecting current in both directions from the battery to the load (600) (discharging current) and from the charger to the battery pack (charging current). This bidirectional current sensing capability ensures accurate monitoring and protection during both charging and discharging operations, enabling effective fault detection and system management.
As per the detailed embodiment of the present invention to achieve effective latching behaviour, the resistors in the feedback path are carefully selected with the condition that R2 (111c) is significantly greater than R1 (111a) (R2 >> R1). This resistor ratio ensures that the maximum possible voltage from the fault signal (i.e., from the logic gate output) appears at Input B of the logic gate. This voltage level is maintained above the logic threshold of the gate input, thereby ensuring reliable and sustained latching of the fault condition. As a result, the latch remains active even after the initial fault signal (Input A) is cleared, until an explicit reset signal is provided to release the latch.
The technical details of working mechanism are further explained below, providing a comprehensive understanding of its functionality:

The resettable fault latch circuit for protection in a Battery Management System (BMS) is designed using a single OR gate. This circuit ensures that once a fault is detected, it remains latched until a controlled reset signal is applied. The major functional blocks and their roles are explained below:

1. Fault Detection and Signal Conditioning:
The current flowing through the battery pack (200) is measured using a shunt resistor (R_sh) in the Current Sensing Element (101).
The voltage drop across R_sh is processed by the Signal Conditioning and Amplifier System (102), which amplifies the sensed voltage (V_sh) to a suitable level for comparison.
A Comparator (103) compares the amplified signal with a predefined reference voltage (V_ref) from the Reference Voltage Generator unit (104).
If the sensed voltage exceeds the reference threshold, indicating a fault, the comparator output (V_O) goes high, generating a Fault Indication Signal.
2. Fault Latching Using a Single OR Gate:
The comparator output Fault Indication Signal is connected to the Input A of Logic Gate (301a) of an OR gate.
The Output of Logic Gate (301c) of the OR gate is fed back to its Input B of Logic Gate (301b) via a Feedback Network (107) with a Tunable Deglitch circuit, consisting of resistors R_1 (111a), R_2 (111c) and a capacitor C_1 (111b), preventing false latching due to noise or start up transients.
When a fault is detected:
a fault indiaction signal (V_F1) = 1 → OR gate output (FLT) becomes 1.
The feedback network holds the Input B of Logic Gate (301b) high (V_F2 = 1), latching the fault.
Even if the initial fault disappears (V_F1 = 0), the fault remains latched due to the feedback network (107).

3. Fault Indication and Protection Activation:
The latched Fault Signal is sent independently to both the microcontroller (110) and Gate Driving Logic Unit (400)
The Microcontroller (110) transmits a control signal to the Gate Driving Logic Unit (400), which disables the Charge Control Switch (114) and the Discharge Control Switch (115), thereby preventing further current flow through the Battery Pack (200). Additionally, during a fault condition, the Gate Driving Logic Unit (400) is independently capable of controlling the switching elements to promptly isolate the fault by deactivating Switches (114) and (115), ensuring the safety and integrity of the Protection System.
A Signal Flow Control Element (113) ensures proper signal flow and prevents unintended feedback.

4. Fault Reset Mechanism Using Latch Release Unit:
To reset the fault, the microcontroller (110) activates a Latch Release Unit, which consists of Switching Element (112).
The Switching Element (112) grounds the Input B of Logic Gate (301b) of the OR gate (V_F2 → 0), breaking the latch condition.
This resets the fault output (FLT → 0), allowing normal system operation to resume.
During the reset process, the first input of the OR gate remains active, ensuring real-time fault detection is not compromised.

Fault Signal (V_F1) Feedback Input (V_F2) OR Gate Output (FLT) Fault Condition State of Protection System
0 0 0 No Fault System Normal
1 0 1 Fault Detected Latch Activated
0 1 1 Fault Latched Latch Maintained
1 1 1 Fault Continues Latch Maintained
0 0 (after reset) 0 Latch Released System Normal

Table 1: Truth Table for Fault Latch Circuit

The table illustrates the functional behaviour of the fault detection and latching mechanism implemented using a single OR gate with two inputs the primary fault signal (VF1) and the feedback input (VF2) and a single output, the fault status (FLT). The logic ensures fault latching, persistent protection, and a reliable reset process.

Case 1: Normal Operation
V_F1= 0, V_F2= 0 → FLT = 0
Explanation: No fault is present, and the feedback latch is inactive.
Outcome: The system operates normally, allowing current to flow through the battery pack.
Case 2: Fault Detected (Latch Triggered)
V_F1= 1, V_F2= 0 → FLT = 1
Explanation: A fault (overcurrent/short circuit) is detected. Since the feedback loop has not yet latched, the fault is newly triggered.
Outcome: The output of the OR gate goes high (1), and the latch circuit activates. This disables the control switches to protect the battery.
Case 3: Fault Latched (After Primary Fault Clears)
V_F1= 0, V_F2= 1 → FLT = 1
Explanation: Although the primary fault indication signal is no longer active, the latch maintains the fault state through the feedback input.
Outcome: The protection system remains in a latched state to prevent reactivation until the microcontroller initiates a reset, ensuring the system is first diagnosed as safe.
Case 4: Persistent Fault
V_F1= 1, V_F2= 1 → FLT = 1
Explanation: The fault indication signal is still active, and the feedback is maintaining the latch.
Outcome: The system stays in fault-protection mode, as the fault is ongoing. This prevents damage from continuous abnormal current.
Case 5: Reset After Fault Clears
V_F1= 0, V_F2= 0 (after reset) → FLT = 0
Explanation: After fault conditions are cleared and the microcontroller issues a reset signal, the feedback input is momentarily grounded.
Outcome: The OR gate output drops to 0, the latch is released, and the system returns to normal operation.
The technical features of the present invention are further elaborately shown and explained through the figures of the invention, providing a comprehensive understanding of its design and functionality.

As shown in Fig. 1 to Fig. 2, FIG. 1 illustrates a Battery Management System (BMS) integrated with a battery pack (200), which supplies voltage and current to an external load (600). A current sensing unit (112) includes a shunt resistor, which generates a differential voltage used to detect overcurrent or fault conditions. Two switching elements are incorporated for charge and discharge control switch (114,115) these switches are controlled by a gate driving logic unit (400) and/or a microcontroller (110).

Figure 2 illustrates a resettable fault latch circuit architecture integrated within a battery management system (BMS) for short-circuit (SC) and overcurrent (OC) protection. The system is centered on a battery pack (200), where current flow is continuously monitored by a current sensing element (101), typically a low-value shunt resistor. The sensed voltage drop is routed to a signal conditioning and amplifier system (102), which amplifies the signal and delivers it to a comparator (103). The comparator (103) compares the amplified current signal against a fixed threshold provided by a reference voltage generator unit (104). When the current exceeds the preset threshold, the comparator (103) produces a fault indication signal.

This fault indication signal is fed to input a (301a) of a logic gate (301), preferably an OR gate, which forms the core of the resettable fault latch unit (300). The output of the logic gate (301c) is routed back to input b (301b) through a feedback control unit (302) and a feedback network (107). The feedback network (107) incorporates a tunable deglitch circuit, comprising a resistor R1 (111a), a resistor R2 (111c), and a capacitor (111b), which suppresses or noise that may occur during startup or switching operations. This configuration enables the logic gate to latch the fault condition even after the initial fault indication signal is removed from input a (301a), thereby holding the system in a protected state.

A microcontroller (110) is connected to the circuit and is responsible for issuing a reset control signal when it determines that the system is safe to resume normal operation. This signal activates the fault reset unit (108), which contains a switching element (112) to temporarily ground input B (301b) of the logic gate (301), thereby clearing the latched state. A signal flow control element (113), typically a diode, is positioned to ensure unidirectional current flow and prevent unintended back feeding into the feedback path.

The latched output (301c) of the logic gate (301) is connected to both the gate driving logic unit (400) and the microcontroller (110). Upon detection of a fault condition, the microcontroller (110) is configured to transmit a control signal to the gate driving logic unit (400), and concurrently, the latched fault signal generated at the output (301c) of the OR gate (301) is also supplied to the gate driving logic unit (400). The gate driving logic unit (400) is adapted to disable both the charge control switch (114) and the discharge control switch (115), thereby isolating the battery pack (200) from the external charger and load (600). The switches (114) and (115) remain disabled until the microcontroller (110) verifies that the fault condition has been cleared and issues a reactivation signal. This coordinated mechanism ensures that the protection system (500) operates autonomously and effectively isolates the battery pack (200) during fault conditions, while allowing safe and controlled reactivation post-reset.
The advantages of the present invention are further highlighted through a detailed description of its design and functionality, providing a comprehensive understanding of its technical benefits.

Enhanced Protection and System Safety
The invention ensures robust fault handling by maintaining the fault state until the system performs diagnostic checks and verifies the return to a healthy condition. This prevents premature reactivation and protects the battery and system components from further damage.

Continuous Fault Monitoring During Reset
The design enables fault detection to remain active even during the reset phase, thereby ensuring that short-circuit (SC) or overcurrent (OC) conditions are not overlooked. This continuous monitoring enhances operational safety and system stability.

Fast and Accurate Fault Detection
The inclusion of a single OR gate-based latch combined with a tunable deglitch circuit allows for rapid detection of faults. This quick response minimizes the risk of thermal or electrical stress on the battery management system (BMS).

Simplified Circuit Architecture
The use of minimal components—including a single logic gate, a resistor-capacitor deglitch circuit, and a switching element -based reset path—reduces design complexity, eases integration, and lowers production and maintenance costs.
Improved Noise Immunity and Startup Reliability
The tunable deglitch circuit effectively filters out transient noise and prevents false fault triggering during power-up. This ensures stable and reliable operation in real-world applications.

Efficient and Controlled Fault Reset
The reset mechanism, driven by a microcontroller-controlled switching element, allows for precise control over fault clearance without disabling the fault detection path. This guarantees uninterrupted protection while enabling system recovery.

Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the illustrative examples, make and utilize the present invention and practice the claimed methods. It should be understood that the foregoing discussion and examples merely present a detailed description of certain preferred embodiments. It will be apparent to those of ordinary skill in the art that various modifications and equivalents can be made without departing from the scope of the invention.

LIST OF REFRENCE NUMERALS
Battery Pack (200)
Current Sensing Element (101)
Signal Conditioning and Amplifier System (102)
Comparator (103)
Reference Voltage Generator Unit (104)
Feedback Network (107)
Fault Reset Unit (108)
Microcontroller (110)
Resistor R1 (111a)
Resistor R2 (111c)
Capacitor (111b)
Switching Element (112)
Signal Flow Control Element (113)
Charge Control Switch (114)
Discharge Control Switch (115)
Protection System (500)
Resettable Fault Latch Unit (300)
Logic Gate (301)
Input A of Logic Gate (301a)
Input B of Logic Gate (301b)
Output of Logic Gate (301c)
Feedback Control Unit (302)
Gate Driving Logic Unit (400)
, C , Claims:Claims:
We claim;
1. A resettable battery fault protection circuit in BMS using single logic gate and tunable deglitch circuit, comprising:
said battery management system having at least one current sensing element (101) configured to sense the current flowing through a battery pack (200) and to generate a sensed voltage (Vsh) across a shunt resistor, the sensed voltage being proportional to the current flowing through the shunt resistor;
plurality of control switch (114, 115) being capable of controlling the current flowing through said battery pack (200);
a protection system (500) being capable of detecting the fault in said battery pack (200);
wherein;
said protection system (500) comprising a signal conditioning and amplifier system (102) being configured to amplify the sensed voltage (Vsh) and generate a conditioned sensed voltage (Vo) suitable for fault detection;
a reference voltage generator unit (104) being capable of generating the reference voltage which being compared with the conditioned sensed voltage (Vo) using a comparator (103);
a comparator (103) being capable to generate a fault indication signal when the conditioned sensed voltage (Vo) exceeds the reference voltage (Vref);
a resettable fault latch unit (300) having single logic gate (301) and a feedback control unit (302);
said logic gate (301) having atleast two inputs and one output the logic gate (301) has an input A (301a) configured to receive a fault indication signal generated by a comparator (103), an input B (301b) connected to the feedback control unit (302), and an output (301c) connected to an input of the feedback control unit (302), microcontroller (110) and the Gate Driving Logic Unit (400);
Said feedback control unit (302) having signal flow control element (113), the feedback network (107) and fault reset unit (108);
the feedback network (107) having resistor R1 (111a), resistor R2 (111c) and atleast one capacitor (111b) arrangement forming a tunable deglitch circuit.
the fault reset unit (108) being capable of resetting the input B (301b), the fault reset unit (108) having a microcontroller (110) controlled switching element (112) configured to receive a reset control signal from a microcontroller (110) and momentarily ground the input B (310b) of the logic gate (301) to release the latched fault condition.

2. The resettable battery fault protection circuit as claimed in claim 1, wherein the logic gate (301) implemented using a single logic gate (301), wherein the single logic gate (301) is an OR gate.

3. The resettable battery fault protection circuit as claimed in claim 1, wherein the tunable deglitch circuit of the feedback network (107) being configured to filter spurious transitions and prevent false fault latching during start-up or due to noise during operation.

4. The resettable battery fault protection circuit as claimed in claim 1, wherein the fault reset unit (108) includes a controllable switching element (112) configured to momentarily ground the input B (301b) of the logic gate (300) upon receiving a reset control signal from a microcontroller (110), thereby releasing the latched fault condition.

5. The resettable battery fault protection circuit as claimed in claim 1, wherein the switching element (112) is a metal-oxide-semiconductor field-effect transistor (MOSFET), a gate terminal of which is driven by the microcontroller (110) to perform the fault reset operation.

6. The resettable battery fault protection circuit as claimed in claim 1, wherein the signal flow control element (113) being positioned between the output (301c) of the logic gate (301) and the feedback network (107).

7. The resettable battery fault protection circuit as claimed in claim 1, wherein the signal flow control element (113) is configured to ensure unidirectional current flow and prevent feedback disturbances, thereby maintaining proper fault detection and preventing disruption of the fault state during the reset process.

8. The resettable battery fault protection circuit as claimed in claim 1, wherein the fault detection remains operational during the reset process due to the logical characteristics of the OR gate (301), wherein the first input (301a) of the OR gate continues to receive the main fault indication signal independently of the reset operation performed on the second input (301b), thereby ensuring uninterrupted fault monitoring.

9. The resettable battery fault protection circuit as claimed in claim 1, wherein the feedback control unit (302) is capable of maintaining the fault state by holding the output (301c) in a fault-indicating condition even after the fault indication signal becomes inactive, thereby ensuring that the system remains in a protected state until reset by the microcontroller (110), wherein the reset signal is generated by the microcontroller (110) after performing diagnostics to ensure a healthy state of the system.

10. The resettable battery fault protection circuit as claimed in claim 1, wherein the microcontroller (110) is configured to transmit a control signal to the gate driving logic unit (400) for selectively disabling or enabling both the charge control switch (114) and the discharge control switch (115), based on the detection and clearance of a fault condition.

11. The resettable battery fault protection circuit as claimed in claim 1, wherein the wherein the gate driving logic unit (400) is configured to disable a charge control switch (114) and a discharge control switch (115) upon receiving the latched fault signal or a control signal from the microcontroller (110).

12. The resettable battery fault protection circuit as claimed in claim 1, wherein upon detection of a fault condition, both the charge control switch (114) and the discharge control switch (115) are turned OFF to disconnect the battery pack from the load (600) and charger, wherein the charge control switch (114) is configured to disable charging current, and the discharge control switch (115) is configured to disable discharging current flow.

Dated this 28th June 2025