FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
THERMAL IMPEDANCE MONITORING PROCESS FOR POWER
MODULE;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION
ORGANISED AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE
ADDRESS IS 7-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO
100-8310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES
THE INVENTION AND THE MANNER IN WHICH IT IS TO BE
PERFORMED.
2
[DESCRIPTION]
[Title of Invention]
THERMAL IMPEDANCE MONITORING PROCESS FOR POWER
MODULE
[Technical Field]5
[0001]
The present disclosure is in the field of protecting power semiconductor
modules from failures due to overheating in particular overheating due to
thermal interfaces degradation and maintenance of equipment using such
modules.10
[Background Art]
[0002]
Thermal interfaces degradation in a power module is due to delamination
and void creation in any of the substructures between a semiconductor die and
a heatsink. These degradations increase temperature of the semiconductor die15
that can lead to an unsafe temperature operation region. The consequence of
the high temperature is the semiconductor breakdown and power module
failure. Monitoring the thermal interfaces is then important to maintain the
power module in a safe temperature region and guide maintenance and
replacement phases of the power module.20
[0003]
The degradation phenomena are caused by the temperature swing and the
CTE mismatch between the different materials composing a power module
stack-up shown in figure 1 that includes at least: semiconductor die 3 (for
example in silicon), die attach 4 (for example in solder), a conductive layer 625
(for example in copper), an electrical insulator layer 7, and a heat-sink 8 (for
example in aluminum).
[0004]
3
The power module 1, can also comprise elements such : a thermal
conductive layer 9 (for example in copper), a join layer 10 (for example solder),
a base plate 11 (for example copper), a thermal interface 12 (for example
graphite or thermal paste). A symmetric material stack-up can be also
envisaged in the case of a double side cooling where the stack-up present5
hereinbefore is repeated on the top side 5 of the semiconductor die 3.
[0005]
Figure 2 shows possible cracks 2 in a layer such as layer 4. Such cracks
cause a reduction of the thermal conduction of the layer.
[0006]10
In document Broeck & al. “In situ thermal impedance spectroscopy of
Power electronic modules for localized degradation identification”, PCIM
Europe 2019; International Exhibition and Conference for Power Electronics,
Intelligent Motion, Renewable Energy and Energy Management, 07-09 May
2019 Nuremberg, Germany; VDE ISBN:978-3-8007-4938-6, is disclosed a15
method to extract the thermal impedance frequency response function of power
modules without interrupting normal converter operations. A sinusoidal small-
signal loss excitation to a power device, extracts the temperature response of
such power device and correlates both signals to estimate the thermal
impedance at the excitation frequency. The method relies on phase information20
rather than magnitude, and thus is insensitive to measurement errors in loss
and/or temperatures. It requires a small signal loss excitation method that will
impact on torque ripple for a motor driver application for example.
[0007]
In document Polom & al., “Real-Time, In Situ Degradation Monitoring25
in Power Semiconductor Converters” 2019 IEEE Applied Power Electronics
Conference and Exposition (APEC) , 17-21 March 2019, IEEE, DOI:
10.1109/APEC.2019.872182 the spatiotemporal dynamic thermal response of
4
a semiconductor assembly response change with degradation is measured with
a heat injection having a certain frequency content (sinus and square). The
temperature of the semiconductor die is estimated via TSEP (thermal sensitive
electrical parameter), the frequency response function (FRF) is computed for
each system identification experiment, the FRF segments are combined and a5
function model is interpreted for thermal interface degradation.
[0008]
In the document Xiang & al., “Condition Monitoring Power Module
Solder Fatigue Using Inverter Harmonic Identification “, IEEE Transactions on
Power Electronics, Volume: 27, Issue: 1, January 2012 Pages 235 - 247, DOI:10
10.1109/TPEL.2011.2160988, a method to monitor solder fatigue in an inverter
applying IGBT power module is described to detect the change of the output
harmonic. It is shown that low-order harmonics, caused by nonideal switching,
are affected by the device junction temperature, which in turn depends upon
module solder condition. The method lacks on accuracy; thus, the inverter15
controller is set to cause harmonic resonance at a given frequency.
[0009]
The standard JESD51-14 describe a method to measure the ‘transient
measurement of thermal resistance’. The method consists of measuring the
junction temperature preferably after the heating power is switched off (cooling20
curve). Although not recommended, in principle also the heating curve can be
used if there is a constant heating power during the heating pulse time. In the
first case, the measurement obliges the power module to be turned-off after
being worked in a known and thermal steady-state condition. In both cases, the
power losses should be known, which is hardily estimated during the on-line25
operation (in field application).
[0010]
Thermal impedance measurements techniques are powerful transient
5
thermal response techniques which can give information on the degradation of
the different interfaces of the power module. The technique typically consists
in:
First, applying a starting steady-state thermal condition on the power
module using the semiconductor switch as active devices. This starting5
condition can either be a zero-power condition, or a condition where a known
and measured constant power is dissipated at the semiconductor.
[0011]
Second, applying a controlled power step increase (in case the start
condition is a zero-power condition) or a power step decrease (in case the start10
condition is a constant power condition), and then recording the evolution of
the semiconductor temperature until the new steady state thermal condition is
reached.
[0012]
Finally, the recorded temperature transient behavior is described by15
using an equivalent Foster and Cauer network which represent the thermal
structure of the power module by several RC elements. A fitting of the
temperature transient using the foster equation allow to extract the resistances
and capacitances of the different part of the power module, giving information
of the evolution of thermal resistances and capacitances.20
[0013]
Lock-in thermography techniques are well-proven commercially
available techniques to detect material and system damages (e.g. delamination
cracks in composites, voids, etc...) as discussed in Gerd Busse “Lockin-
Thermography: Principles”, NDE-applications and trends, January 201425
Conference: 2014 Quantitative InfraRed Thermography,
DOI:10.21611/qirt.2014.e.
[0014]
6
The lock-in thermography techniques uses a process where the material
or system to be analyzed thermally is excited with a non-steady state signal (e.g
a pulsed signal, or a sinusoidal signal) at a specific frequency (related to the
material thickness or damage depth), for example using an infrared radiative
source such as a set of halogen lamps, recording images of the transient5
temperature response of the system/material, using specific software and
algorithm, calculating the phase and the amplitude between the response and
the excitation, and thus generating a phase image and an amplitude image.
These techniques are used in thermal steady state conditions.
[0015]10
Problems with respect to the state-of-the-art methods for thermal
impedance monitoring are that:
- The dissipated power in the semiconductor must be known, i.e., it must
be measured or estimated. In cases where the semiconductor is integrated in a
power converter, this can be a difficult task;15
- with the thermal measurement techniques described above, (where the
measurements are done in a steady state thermal situation) no information can
be gained on which of the layers of the power module stack-up is degraded.
[Summary of Invention]
[0016]20
The present disclosure proposes a measurement method using a lock-in
technique in transient states instead of steady state situations.
[0017]
More precisely, the present disclosure proposes a thermal impedance
monitoring process for a power module of a power converter used for25
transforming DC current to AC current, or vice-versa, where the semiconductor
dissipates an asymmetrical loss between two half cycles of an AC frequency f
of the AC current, said power module comprising at least a semiconductor die
7
attached to a material stack-up of layers for its thermal dissipation and/or
electrical connections, said process comprising:
- sampling and measuring a signal relating to the junction temperature Tj
of said semiconductor die at a frequency higher than ten time said AC
frequency of said AC current,5
- calculating a time duration Δt= tTjmax- tTjmin between a moment
tTjmax, where said junction temperature of said semiconductor die is at a
maximum value, and a moment tTjmin, where said junction temperature is at a
minimum value, in one period of said AC current, and storing said time duration
Δt in a memory,10
- repeating said sampling and measuring said signal and said calculating
said time duration at different times tx=t0 to tp during the operating life of the
power module to provide a series of time durations Δtt0 to Δttp , and comparing
said time durations Δttp values with Δtt0 for monitoring an evolution of said time
duration Δtx to determine an evolution of degradation of the thermal impedance15
of said power module.
[0018]
The process may comprise measuring said AC frequency and storing
couple of time duration Δttx and AC frequency, ffund values.
[0019]20
The process may comprise modifying said AC frequency during
dedicated operation periods of said converter to provide several different AC
frequencies fm=f1, f2, ..., fn each allowing to detect a thermal impedance of a
specific layer of said stack up, repeating said sampling and measuring and said
calculating the time durations Δttxf1, Δttxf2, ... , Δttxfn corresponding to such25
different AC frequencies,
- repeating said sampling and measuring said signal and said calculating
said time duration during the operating life of the power module to provide a
8
series of Δt0 to Δtx values for each of said different AC frequencies, and
comparing said Δttxfm values with Δtt0fm at each of said AC frequencies fm=f1,
f2, ..., fn for monitoring an evolution of Δtxfm for each of said AC frequencies to
determine an evolution of degradation of the thermal impedance of said specific
layers.5
[0020]
The process may comprise measuring a time difference Δtmin between
two successive minima of the junction temperature and calculating said AC
frequency as f=1/Δtmin.
[0021]10
The signal relating to the junction temperature Tj may be a temperature
sensitive electrical parameter of said semiconductor.
[0022]
In such case the signal may be a non-calibrated temperature sensitive
electrical parameter of said semiconductor.15
[0023]
Said AC frequency may be lower than 𝑓𝑑 = 𝐷𝑑𝑖𝑒
𝑙𝑑𝑖𝑒2 where ldie is the die
thickness and Ddie is the diffusivity coefficient of the die.
[0024]
Said AC frequency may be lower than 2kHz.20
[0025]
Said AC frequency may be lower than 1kHz.
[0026]
Said AC frequency may be the fundamental frequency powering the
converter or the fundamental output frequency ffund of the converter.25
[0027]
The present disclosure concerns also a converter comprising sensor
means on a power semiconductor switch die of said converter for sensing a
9
temperature on said power semiconductor switch die, analog to digital
converter means, sampling means and a processor provided with memory
means for storing and running a software configured for executing the thermal
impedance monitoring process described hereabove.In particular, said sensor
means may be designed to sense a temperature sensitive electrical parameter of5
said die. The present disclosure proposes also a software comprising
instructions for executing the thermal impedance monitoring process disclosed
hereabove.
[0028]
A detailed description of exemplary embodiments of the disclosure will10
be discussed hereunder in reference to the attached drawings.
[Brief Description of Drawings]
[0029]
[FIG. 1]
Figure 1 is an example of traditional stack of layers for a power module.15
[FIG. 2]
Figure 2 is a view of a cracked solder layer.
[FIG. 3]
Figure 3 is a prior art diagram of surface temperature response phase shift
versus depth of a defect.20
[FIG. 4]
Figure 4 is a Cauer network example of a stack-up of a power module.
[FIG. 5]
Figure 5 is a first Bode diagram for a first example of defects layers of a
stack-up.25
[FIG. 6]
Figure 6 is a second Bode diagram for a second example of defects layers
of a stack-up.
10
[FIG. 7]
Figure 7 is a third Bode diagram for a third example of defects layers of
a stack-up.
[FIG. 8]
Figure 8 is an expanded Bode diagram for the first example of defects5
layers of the stack-up of figure 5.
[FIG. 9]
Figure 9 is a simplified schematic view of a converter example with
processor.
[FIG. 10A]10
Figure 10A is a diagram of losses and junction temperature versus time
for a pristine and a degraded stack-up.
[FIG. 10B]
Figure 10B is a diagram of losses and junction temperature versus time
for a pristine and a degraded stack-up.15
[FIG. 11]
Figure 11 shows the losses waveforms for different modulation types
in a DC/AC converter according to different controls.
[FIG. 12]
Figure 12 shows a diagram of equivalent phase shift versus fundamental20
frequency for different degradations of layers.
[FIG. 13A]
Figure 13A shows process steps of the present process.
[FIG. 13B]
Figure 13B shows process steps of the present process.25
[FIG. 13C]
Figure 13C shows process steps of the present process.
[Description of Embodiments]
11
[0030]
In order to characterize the behavior of a power module, the thermal
wave theory predicts that the thermal response of the surface of a homogeneous
infinite material half-space subjected to a thermal excitation 𝑃0 = 𝑃0 (1 +
cos(𝜔𝑡))/2 is shifted by + 𝜋
4 (+45ᵒ). Because of the wave nature of the5
excitation heat propagation within the material can be analyzed from wave
theory ,in which a defect or interface present at a distance d under the surface
of the material can be modelled by a reflection coefficient R (0 no defect (perfect transmission); R=1=> strong defect
(perfect reflection)).20
[0031]
It can be seen that when a defect is positioned at d<1.55 μm and has a
coefficient of reflection R>0.4, the surface temperature response phase shift
changes from the semi-infinite body value of 45ᵒ to a lower value that depends
on R and on the position of the defect.25
[0032]
Figure 3 thus shows the basic principle of lock-in thermography to
characterize defects and interfaces in materials, devices including a module
12
stack-up.
[0033]
Importantly the value of μ is frequency dependent: for defects located
further into the material, greater sensitivity is obtained when lower excitation
frequency is used. Thus, by varying the excitation frequency, information about5
interface (degradation) of different layer stack or interface can be gained.
[0034]
Although this simple model can give a good guidance on methods using
thermal waves to detect damage, a power semiconductor stack cannot be
modelled by a semi-infinite body, due to the different thermal properties of10
each layer of the stack. In order to analyze this system more precisely a 1D
electrical equivalent of the thermal model can be used, one which the frequency
response function can by analyzed.
[0035]
Thermal impedance: electrical equivalent model:15
On the basis that heat conduction and electronic conduction are both
physical processes modelled by the same phenomenon (diffusion), the thermal
impedance of a semiconductor module can be modelled by analogy with the
scaled heat conduction equation and the telegrapher’s equations. Thus, an
equivalent electrical network of the thermal system can be deduced. The20
resistances and capacitances of the electrical equivalent are defined by analogy
with a thermal resistance, Rth and capacitance Cth, using the following
equations:
𝑅𝑡ℎ = ∆𝑇
𝜙 = 𝑙
𝜆 ∙ 𝐴 (1)
Where l is the thickness;25
A is the cross section area;
λ is the thermal conductivity,
13
𝐶𝑡ℎ = 𝐸𝑡ℎ
∆𝑇 = 𝑐 ∙ 𝜌 ∙ 𝑉 (2)
Where c is the specific heat capacity [J/g];
V is the volume [m3];
ρ is the density [g/m3].
[0036]5
In the case of a simple model of power module composed with a stack-
up of different materials, each layer will present a thermal resistance and a
thermal capacitance. Thus, an electrical network, called Cauer network, can
represent the thermal system of a stack-up of 5 layers as shown in Figure 4. Ploss
is the heat flux from the top side 5 of the semiconductor die 3 of figure 1,10
corresponding to the losses dissipated on the semiconductor die (the electrical
equivalent is a current source), Cth and Rth are the equivalent capacitance and
resistance of each layer starting with the die layer 3 and the heatsink layer 8and
Tamb is the environment heatsink temperature.
[0037]15
The total thermal impedance of the network of figure 4 can be calculated
using the following equation where s is the Laplacian operator:
𝑍(𝑠)
= 1
𝑠 ∙ 𝐶𝑡ℎ1 + 1
𝑅𝑡ℎ1 + 1
𝑠 ∙ 𝐶𝑡ℎ2 + 1
𝑅𝑡ℎ2 + 1
𝑠 ∙ 𝐶𝑡ℎ3 + 1
𝑅𝑡ℎ3 + 1
𝑠 ∙ 𝐶𝑡ℎ4 + 1
𝑅𝑡ℎ4 + 1
𝑠 ∙ 𝐶𝑡ℎ5 + 1
𝑅𝑡ℎ5
. (3)
[0038]20
For the case of a degraded layer, a new (increased) resistance 𝑅𝑡ℎ,𝑣 may
be calculated using a percentage of void, f, as described in the next equation.
As the material quantity is not modified, the thermal capacitance 𝐶𝑡ℎ remains
14
unchanged:
𝑅𝑡ℎ,𝑣 = 𝑅𝑡ℎ
(1 − 𝑓)2 . (4)
[0039]
For example, in the case of the stack-up of nine layers described in
figure 1 and the material data of Table 1 hereunder:5
{Table 1}
Stack up
layers
𝜆 [W/mK] 𝜌 [g/cm3] 𝑐 [J/gK] 𝑙 [mm]
3 (silicon) 80 2,3 0,712 0,14
4 (die attach) 50 7,4 0,24 0,1
6 404 8,9 0,385 0,3
7 160 3,3 0,72 0,7
9 450 8,9 0,385 0,32
10 60 7,4 0,24 0,4
11 450 8,9 0,385 4
12 30 1,81 0,85 0,15
8 239 2,7 0,921 20
[0040]
The thermal impedance may be plotted in a bode diagram, where the
amplitude and the phase are plotted in function of the excitation frequency of a
sinus type. In the curves of Figures 5 to 7 a comparison is done between a10
pristine, that is non-degraded module, and a degraded module according to
figure 1 with measurements done at increasing frequencies.
[0041]
Figure 5 is the Bode diagram of a stack according to figure 1 with the
layer 4 and the layer 10 having 40% of voids. Figure 6 is the Bode diagram of15
a stack according to figure 1 with the layer 4 has 40% of voids. Figure 7 is the
15
Bode diagram of a stack according to figure 1 with the layer 10 has 40% of
voids. These figures show that the amplitude and the phase of the thermal
impedance are modified by the degradation.
[0042]
Curves 32, 33 of figure 5, curves 36, 37 of figure 6 and curves 40, 41 of5
figure 7 are representing the phase difference between the temperature
variations of the die for of pristine in dotted line and degraded layers in plain
lines. Curves 30, 31 of figure 5, curves 34, 35 of figure 6 and curves 38, 39 of
figure 7 are representing the amplitude of the temperature variation of the die
with pristine in dotted line and degraded layers in plain lines.10
[0043]
The influence of a degradation of layer 4 which is located close to the
excitation source can best be detected by a phase shift of curve 33 with respect
to curve 32 at about 100Hz excitation as in figures 5 and 6, whereas a relatively
lower excitation frequency from about 1 to 10Hz is required to detect a15
frequency shift between curve 40 and curve 41 corresponding to a damage in
layer 10 which is located further away from the heat source as seen in figure 7.
Note that no phase shift change is observed at 100Hz in case damage is
introduced in layer 10. Thus, by varying the excitation frequency, it is possible
to gain information on which layer is damaged.20
[0044]
Power semiconductors die losses:
The previous section described the thermal response of the system to a
sinusoidal excitation. In real application cases the power dissipation does not
necessarily follow a sinusoidal behavior. The goal of this section is to describe25
the necessary conditions of the semiconductor operating point that generate a
suitable thermal response of the system such that an information on a layer
degradation can be gained. To support the loss profile requirements, the bode
16
diagram of figure 6 is plot on a larger frequency range as in figure 8 where the
interval goes from 1Hz to 1 MHz.
[0045]
In the present example, figure 8 shows the following information:
- The magnitude of the bode diagram gives essentially the same5
information as a thermal impedance plot;
- The phase information shows that the curve 44 of non-degraded and the
curve 45 of degraded cases merge at f>1kHz. Thus, no information on
the degradation can be gained by analysing the phase response of the
system above this frequency.10
[0046]
The reason why the degraded and non-degraded cases cannot be
separated at f>1KHz is because in the high frequency range the thermal
impedance of the heat source (the silicon die) acts as a filter to the electrical
excitation. This is straightforward when noticing that the thermal response15
timescale of the die is of order of 𝜏𝑑 = 𝑅𝑡ℎ𝑑 𝐶𝑡ℎ𝑑 . Using the
definitions:
𝜏𝑑 = 𝑅𝑡ℎ𝑑 𝐶𝑡ℎ𝑑 = 𝑙
𝜆 ∙ 𝐴 . 𝑐 ∙ 𝜌 ∙ 𝑉 = 𝑙
𝜆 ∙ 𝐴 . 𝑐 ∙ 𝜌 ∙ 𝐴. 𝑙 = 𝑙2𝑐 ∙ 𝜌
𝜆 = 𝑙𝑑 2
𝐷𝑑
. (5)
[0047]
In diffusion theory 𝐷 = 𝜆
𝑐∙𝜌 (𝑢𝑛𝑖𝑡: [ 𝐽.𝑚3𝑔.𝐾
𝑠.𝑚.𝐾.𝑔.𝐽] = [𝑚2
𝑠 ]) is called the20
diffusivity coefficient. 𝜏𝑑 ≈ 𝑙𝑑2
𝐷𝑑
is the timescale needed for a heat pulse to travel
through the die thickness 𝑙𝑑𝑖𝑒.
[0048]
Using the values of material 3 in Table 1 we find 𝐷𝑑 = 4.88 10−5 𝑚2
𝑠 ,
using a die thickness 𝑙𝑑 = 0.14 𝑚𝑚; 𝜏𝑑 = 4.01 10−4𝑠. The thermal system25
17
response bandwidth is thus limited by 𝑓𝑑 = 1
𝜏𝑑
= 2.5 𝑘𝐻𝑧, which is the same
order of magnitude as the 1kHz value found by examination of the bode
diagram in figure 8.
[0049]
The implication for the applicability of this invention is thus that the5
electrical excitation frequencies of interest should be significantly lower than
𝑓𝑑 = 𝐷𝑠𝑖
𝑙𝑑 2 ; i.e., preferably lower than 2kHz and preferably lower than 1kHz.
[0050]
Advantageously to the present invention, typical signal modulation
strategies such as PWM modulation in converters typically operate at10
frequencies higher than 1kHz, such as 5kHz, or 10kHz. In consequence, the
thermal system response will be weak in this frequency range, and the
temperature oscillations due to the PWM frequency will be weak as seen in the
magnitude of the bode plot <-60dB of figure 8. Thus, advantageously, the
thermal system will not be influenced by the PWM excitation. For the use of15
the model described in the previous section this justifies that the losses can be
averaged over a PWM period.
[0051]
Advantageously to the present invention, typical excitation frequencies
may be limited by the load impedance, by the load requirements, or by the20
external control of the system, such that the system is typically excited in the
frequency range of interest, i.e., at a frequency lower than 1kHz, for example
50Hz, 60Hz, 100Hz, 400Hz, or 1 Hz.
[0052]
Another implication of this analysis is that a low frequency electrical25
excitation signal should not decrease from the maximum power value to the
zero-power value within a time interval lower than 𝜏𝑑.
18
[0053]
Thus, to summarize the power semiconductor losses requirements within
the present invention: the power semiconductor die losses waveform is
dependent on the application where the power module or system is installed.
[0054]5
This invention relates to the cases of DC/AC or AC/DC power converter
topologies, and to the cases where the losses are low frequency periodic
pulsating waves with the following characteristics:
a. A maximum pulse duration of a half-period of the fundamental
frequency of the AC current, such that there exists a zero-loss time10
interval.
AND
b. At least one local maximum inside the pulse, OR an asymmetrical loss
dissipation between the two half-cycles.
AND15
c. The time difference between the last maximum and the zero-loss time
is larger than 𝜏𝑑 = 𝑙𝑑2
𝐷𝑑
, where 𝑙𝑑 is the thickness of the semiconductor
chip, and 𝐷𝑑 is the heat diffusivity of the semiconductor chip. This
implies the low frequency of the modulated losses to be lower than
𝑓𝑑 = 𝐷𝑑𝑖𝑒
𝑙𝑑𝑖𝑒2 where ldie is the die thickness and Ddie is the diffusivity20
coefficient of the die.
[0055]
As an example, for condition c, the semiconductor chip is a silicon chip
of thickness 𝑙𝑑𝑖𝑒 = 100μm, the thermal diffusivity coefficient of silicon is
𝐷𝑑𝑖𝑒 =4.89 10-4 m2/s, and thus 𝑓𝑑𝑖𝑒 = 4.89kHz, and 𝜏𝑑𝑖𝑒 =205μs.25
[0056]
An example of DC/AC power topology is shown in figure 9 where a DC
19
supply 51 serves to build a three-phase alternating supply 52 using power
semiconductor switches 1. The DC/AC power converter has a 3-phase
configuration supplied by a DC bus voltage. The semiconductor die can be any
IGBT, Diode, MOSFET, MISFET and in any placement of the power converter
topology. In the following example, the semiconductor die of interest in the5
power module is placed in one leg at the high side position.
[0057]
The switching and conduction losses of the semiconductor die 50 are
generated in a normal operation of the power module in a motor control
application given the load current, the bus voltage during the switching and10
conduction events.
[0058]
The semiconductor die losses generation in a power module on a DC/AC
or AC/DC operation is proportional to the following variables that are related
to the operating point: the current passing through Icond, the switched current15
Isw, the switched voltage Vsw, the switching frequency fsw, the junction
temperature, Tj , the duty cycle modulation strategy / PWM technique.
[0059]
In such an application, typically, a periodic pulsed loss waveform in an
DC/AC or AC/DC application is generated in the fundamental frequency, e.g.,20
a grid frequency 50Hz or an electrical motor rotation control frequency of 1Hz
– 2kHz. In any strategy, the losses on the semiconductor are generated only
during a time corresponding to a first half-cycle of the fundamental frequency,
and the semiconductor does not generate any losses during the second half
cycle of the fundamental frequency.25
[0060]
Considering that the power converter generates a sinusoidal current
waveform, at the fundamental frequency of 100Hz, on the output of the phases
20
ABC and a chopped voltage waveform at the switching frequency operation of
20kHz.
[0061]
Figures 10A and 10B are representation of the junction temperature and
losses for a pristine and degraded power module at 100Hz of fundamental AC5
frequency. Figure 10A is a general view of the power and junction temperature
waves with respect to time, Figure 10B is a zoomed figure on one loss period
comprising also a measurement of the die temperature Tj duration time. In this
example, the losses wave 70 in figure 10A on the semiconductor die has only
the positive sinusoidal shape. In other words, the losses follow a sinusoidal10
shape between 0° and 180° (0 and π) and have a null value between 180° and
360° (π and 2 π) within the fundamental frequency 𝑓𝑓:
𝑃𝑙𝑜𝑠𝑠 ≈ { 𝐴 ∙ 𝑠𝑖𝑛2(2𝜋 ∙ 𝑓𝑓 ∙ 𝑡) 𝑓𝑜𝑟 0 ≤ 2𝜋 ∙ 𝑓𝑓 ∙ 𝑡 ≤ 𝜋
0 𝑓𝑜𝑟 𝜋 < 2𝜋 ∙ 𝑓𝑓 ∙ 𝑡 < 2𝜋. (6)
[0062]
The temperature response Tj of the die 71, 72 in figure 10A is calculated15
using the thermal impedance. The temperature wave has one minimum 71a,
72a and one maximum 71b, 72b within a fundamental period. When measuring
the time between the minimum temperature point and the maximum
temperature point gives an indicator of the module degradation. In figure 10B
showing a single loss period, it can be seen that the degraded power module20
with 40% of voids in layer 4of figure 1 operating at 100Hz of AC current has a
longer duration time Δt=td than that of the pristine power module Δt=tp. This
can be explained by the bode diagram of figure 6, showing a larger absolute
phase angle for the degraded thermal impedance compared to the pristine
thermal impedance at 100Hz.25
[0063]
An important point is that it is possible only by examination of the
21
temperature response to identify the beginning of the pulse corresponding to
tTjmin, because the sudden power change generates a kink in the temperature
response. Thus, advantageously, the information of Δt=tTjmax-tTjmin is
related to the phase angle between the temperature response and the power
excitation.5
[0064]
Figure 11 shows the losses in the fundamental frequency of the converter
plotted for different modulation strategies when a DC/AC power converter
drives an electrical motor. The different modulation strategies are: Sine 60,
DPWM1 61, DPWM3 62, Spacevector 63. The losses are calculated10
considering both the conduction losses and the switching losses of the
semiconductor die, and averaged over a modulation period.
[0065]
The topologies of the converter are not limited to the converter taken as
an example but could be multilevel topologies as the NPC (neutral point15
clamped inverter), ANPC (Active-neutral-point-clamped inverter), MMC
(modular multilevel converter), FC (flying capacitor) and other topologies that
are the state of art.
[0066]
This shows that in an AC/DC or DC/AC power converter having a power20
module comprising at least a semiconductor die attached to a material stack-up
for the thermal dissipation and/or for electrical connections, where the
semiconductor dissipates an asymmetrical loss between two half cycles of the
AC frequency, measuring a signal related to the temperature of the
semiconductor at said frequency, measuring the time duration Δt=tTjmax-25
tTjmin between the temperatures Tjmax and Tjmin where the junction
temperature is at the maximum and respectively its minimum value, in an AC
period permits to obtain a measurement of the degradation of at least one layer
22
in a stack of layers between the die and a heatsink to which the die is attached
by repeating such measurements during life of the power converter.
[0067]
Thus, advantageously since de degradation is sensitive to the temperature
increase time delay Δt, and not to the magnitude of the temperature, nor the5
magnitude of the power losses the thermal degradation estimation is not
sensitive to the accuracy of the junction temperature measurement, and thus
any signal related to the temperature of the semiconductor can be used,
provided there is a monotonous relation between the temperature and the signal.
It is not necessary to estimate or measure the power losses in the10
semiconductor, thus advantageously reducing the number of sensors, the
computation time and increasing the accuracy of the degradation measurement.
[0068]
In order to repeat measurements and compare such during the life of the
converter, the calculations of the temperature increase time delay Δt= tTjmax-15
tTjmin may be stored in a memory at each iteration and compared with an initial
value and/or a previous value and the evolution of such time delay Δtx for tx=t0
to tp may be monitored to obtain the degradation state of the thermal impedance.
[0069]
In addition to the measurement of the temperature increase time delay,20
the fundamental frequency ffund at which the losses are measured may be
measured and stored and the degradation state is determined by the time
duration Δt(ffund) at said fundamental frequency.
[0070]
Thus, advantageously, degradation information of a specific stack layer25
can be gained, as the variation of the damage indicator Δtx is sensitive to the
fundamental frequency.
[0071]
23
For example, the fundamental loss frequency can be measured using the
AC load current probe, or be given by the controller reference, or be given by
the user AC frequency request.
[0072]
As discussed hereunder, damages at different height in the stack causes5
different phase shift in the temperature increase curves and measuring damage
indicators Δti(ffund,i) at different frequencies ffund,i enables to gain information
on the degradation evolution at different layers of the stack. The higher
frequencies are used to monitor a degradation of the stack layers closer to the
semiconductor and the lower frequencies are used to monitor a degradation of10
the stack layers farther from the semiconductor.
[0073]
The effect of the degradation on the frequency response functions for a
specific layer of the stack can be determined by introducing a degradation in a
specific layer, for example using equation 4, measuring the phase shift15
associated with this degradation using the Z(s) estimation of equation 3, and
plotting a bode diagram as in figures 5 to 7.
[0074]
As an example, one or several frequencies between 20Hz to 500Hz are
used to monitor the degradation on the layer 4 according to Figure 6 and one or20
several frequencies between 1Hz to 10Hz are used to monitor the layer 10
resulting in the curve of figure 7.
[0075]
In the case of a combination of several degradations, monitoring of the
time delay at several frequencies enables to separate the contributions of the25
several degradations as in the example of figure 5.
[0076]
To support the relation between Δt and the phase angle, as a first
24
approximation, the change of phase angle 𝑃ℎ in angular unit of degrees (ᵒ) due
to the degradation, that is the change from Δt=tp to Δt=td can be approximated
by the following equation:
𝑃ℎ = (𝑡𝑑 − 𝑡𝑝) ∙ 𝑓𝑓 ∙ 360. (7)
[0077]5
Figure 12 shows a comparison of first-order estimation of the phase Ph
using equation (7), and the phase extracted from calculations using the
impedance method with respect to the fundamental frequency. In this diagram,
curve 80 is the estimated phase curve for degraded layers 4 and 10 of figure 1
while curve 81 is the theoretical curve for such degraded layers, curve 82 is the10
estimated phase curve for degraded layer 4 while curve 83 is the theoretical
curve fir such degraded layer, curve 84 is the estimated phase curve for degrade
layer 10 and curve 85 the theoretical curve for such degraded layer 10.This
shows that for frequencies above around 10 Hz, the first order estimation shows
similar trend as the more rigorous model, thus demonstrating that the15
information in Δt is the same as in the phase of the bode diagrams of figures 5
to 8.
[0078]
Then, in case the fundamental frequency f of the AC current may be
changed, the process may monitor the time difference for different fundamental20
frequencies. This gives a possibility to provide estimation of which of the layers
are degraded layers.
[0079]
As the time difference Δtmin between two successive minima of the
junction temperature is measured, the fundamental frequency may be25
calculated as ffund= 1/Δtmin.
[0080]
Thus, advantageously, this allows to record the fundamental frequency
25
without using an additional sensor, or without acquiring the fundamental
frequency information from a separate algorithm. Thus, advantageously, the
algorithm for degradation analysis can work independently of a control
algorithm of the converter or any other operating condition of the power
module.5
[0081]
In example, in figure 10A, the time interval between two successive
minima is Δtmin =0.02s, and thus the fundamental frequency is found as
ffund=1/Δtmin=50Hz.
[0082]10
The signal used for measuring the temperature may be any thermal
sensitive electrical parameter (TSEP) of the concerned semiconductor switch.
[0083]
Thus, the deterioration can be identified and quantified without any
complex prior TSEP calibration, reducing the complexity of the system.15
[0084]
For example, the TSEP can have values X between Xa and Xb
corresponding, for example to the range of temperature [-20C;200C], and the
relation between the temperature and the TSEP is linear such as:
T=XA+B in [Xa;Xb] where A and B are constant.20
[0085]
In this example, it is not necessary to calibrate the TSEP, i.e., to
determine A and B before implementing the method since only the variable X
is measured. In a sub example, A>0, and the moments tTjmax and tTjmin where
the junction temperature is at the maximum, respectively at the minimum25
correspond to the moments where X is at the maximum, respectively at the
minimum value. In another sub example, A<0, and the moments tTjmax and
tTjmin where the junction temperature is at the maximum, respectively at the
26
minimum correspond to the moments where X is at the minimum, respectively
at the maximum value.
[0086]
More generally, it is sufficient that the function T(X) is monotonously
increasing or decreasing, e.g., that its first derivative does not change sign in5
the interval [Xa;Xb]. Thus, advantageously non-calibrated TSEP with a non-
linear temperature characteristic can also be used in the scope of the present
disclosure.
[0087]
In figure 13A are shown process steps of the present disclosure with the10
process comprising:
- Step 100: sampling and measuring a signal S relating to the junction
temperature Tj of said semiconductor die at a frequency higher than ten time
said AC frequency of said AC current,
- Step 110 calculating a time duration Δt= tTjmax- tTjmin between a15
moment tTjmax, where said junction temperature of said semiconductor die is
at a maximum value, and a moment tTjmin, where said junction temperature is
at a minimum value, in one period of said AC current, and step 120 storing said
time duration Δt in a memory,
- Step 130 comparing said time durations Δtt0 to Δttp for t=t0 to tp values20
for monitoring an evolution of said time duration Δt to determine an evolution
of degradation of the thermal impedance of said power module;
- repeating 140, 150 said sampling and measuring said signal and said
calculating said time duration at different times tx=t0 to tp during the operating
life of the power module to provide a series of time durations Δtt0 to Δttp.25
[0088]
Step 100 may also comprise measuring said AC frequency and step 120
may comprise storing couple of time duration Δttx and AC frequency, ffund
27
values.
[0089]
Measuring in step 100 may be done with several means such as
thermocouple, infrared image, TSEP etc.
[0090]5
Since there may be some noise in the measurements, averaging of the Δt
values may be required and the comparison may not be done strictly with the
first Δt0 value measured, but rather with a mean value over a measurement
period of a few alternances at the beginning of the product usage. In such case,
the averaging may be done on about two to ten alternances.10
[0091]
Repetition of the sampling, measuring and the comparison maybe done
on a regular basis that is every day, week, month or after a number of
alternances of the AC frequency corresponding to the use of the converter (e.g.,
tenth or hundreds of hours) relevant with the estimated degradation rate.15
Repetition rate may also be accelerated when a difference between Δttx and Δt0
becomes larger than a predetermined warning value.
[0092]
The process may also comprise as shown in figure 13B one or more steps
260 of modifying said AC frequency during dedicated operation periods of said20
converter to provide several different AC frequencies fm= f1, f2, ..., fn each
allowing to detect a thermal impedance of a specific layer of said stack up,
repeating said sampling, and measuring the TSEP signal S and the frequency
200 and said calculating 210 the time durations Δttxf1, Δttxf2, ... , Δttxfn
corresponding to such different AC frequencies,25
- one or more steps 230 of comparing said Δtt0fm to Δttpfm values at each
of said AC frequencies for monitoring an evolution of Δt for each of said AC
frequencies to determine an evolution of degradation of the thermal impedance
28
of said specific layers,
- repeating said sampling and measuring said signal and said calculating
said time duration during the operating life of the power module to provide a
series of Δtx= Δt0 to Δtp values for each of said different AC frequencies fm for
comparing the Δtx values with the Δt0 value.5
[0093]
Here also, repetition of the sampling, measuring and the comparison
maybe done on a regular basis that is every day, week, month or after a number
of alternances of the AC frequency corresponding to the use of the converter
(e.g., tenth or hundreds of hours) relevant with the estimated degradation rate.10
Repetition rate may also be accelerated when a difference between Δttx and Δt0
becomes larger than a predetermined warning value.
[0094]
In addition, the tests using adaptation of the AC frequency may be done
in specific situations such as tests on the grid frequency or ramping of a motor15
speed.
[0095]
The process also may comprise as in figure 13C one or more steps 300
of measuring a time difference Δtmin between two successive minima of the
junction temperature and calculating 310 said AC frequency as f=1/Δtmin. This20
avoids having to measure the frequency with another means than the signal S
relating to the junction temperature Tj which may be a non-calibrated
temperature sensitive electrical parameter of said semiconductor.
[0096]
To proceed with the present process the converter as shown in figure 925
may comprise sensor means 53 on a power semiconductor switch die of said
converter for sensing a TSEP signal of said power semiconductor switch die,
analog to digital converter means 54, sampling means 55 and a processor 56
29
provided with the necessary memory means 57 and computing means for
storing and running a software configured for executing the thermal impedance
monitoring process of the present disclosure.
30
We Claim :
[Claim 1]
Thermal impedance monitoring process for a power module of a power
converter used for transforming DC current to AC current, or vice-versa, where
the semiconductor dissipates an asymmetrical loss between two half cycles of5
an AC frequency f of the AC current, said power module comprising at least a
semiconductor die attached to a material stack-up of layers for its thermal
dissipation and/or electrical connections, said process comprising:
- sampling and measuring (100) a signal relating to the junction
temperature Tj of said semiconductor die at a frequency higher than ten time10
said AC frequency of said AC current,
- calculating (110) a time duration Δt= tTjmax- tTjmin between a
moment tTjmax, where said junction temperature of said semiconductor die is
at a maximum value, and a moment tTjmin, where said junction temperature is
at a minimum value, in one period of said AC current, and storing (120) said15
time duration Δt in a memory,
- repeating (140) said sampling and measuring said signal and said
calculating said time duration at different times tx=t0 to tp during the operating
life of the power module to provide a series of time durations Δtt0 to Δttp , and
comparing (130) said time durations Δttp values with Δtt0 for monitoring an20
evolution of said time duration Δtx to determine an evolution of degradation of
the thermal impedance of said power module.
[Claim 2]
Thermal impedance monitoring process as claimed in claim 1 comprising
averaging the Δt measurements on periods for reducing noise in the25
measurements.
[Claim 3]
Thermal impedance monitoring process as claimed in claim 1 or 2
31
comprising measuring (200) said AC frequency and storing (220) couple of
time duration Δttx and AC frequency, ffund values.
[Claim 4]
Thermal impedance monitoring process as claimed in claim 3 comprising
modifying (260) said AC frequency during dedicated operation periods of said5
converter to provide several different AC frequencies fm=f1, f2, ..., fn each
allowing to detect a thermal impedance of a specific layer of said stack up,
repeating said sampling, and measuring and said calculating the time durations
Δttxfm= Δttxf1, Δttxf2, ... , Δttxfn corresponding to such different AC frequencies,
- repeating (240) said sampling and measuring (200) said signal and said10
calculating (210) said time duration during the operating life of the power
module to provide a series of Δt0fm to Δtxfm values for each of said different AC
frequencies, and comparing (230) said Δttm values with Δtt0 at each of said AC
frequencies for monitoring an evolution of Δt for each of said AC frequencies
fm=f1, f2, ..., fn to determine an evolution of degradation of the thermal15
impedance of said specific layers.
[Claim 5]
Thermal impedance monitoring process as claimed in claim 3 or 4
comprising measuring (300) a time difference Δtmin between two successive
minima of the junction temperature and calculating (310) said AC frequency as20
f=1/Δtmin.
[Claim 6]
Thermal impedance monitoring process as claimed in any one of claims
1 to 5 wherein the signal relating to the junction temperature Tj is a temperature
sensitive electrical parameter of said semiconductor.25
[Claim 7]
Thermal impedance monitoring process as claimed in claim 6 wherein
the signal relating to the junction temperature Tj is a non-calibrated temperature
32
sensitive electrical parameter of said semiconductor.
[Claim 8]
Thermal impedance monitoring process as claimed in any one of claims
1 to 7 wherein said AC frequency is lower than 𝑓𝑑 = 𝐷𝑑𝑖𝑒
𝑙𝑑𝑖𝑒2 where ldie is the die
thickness and Ddie is the diffusivity coefficient of the die.5
[Claim 9]
Thermal impedance monitoring process as claimed in any one of claims
1 to 8 wherein said AC frequency is lower than 2kHz.
[Claim 10]
Thermal impedance monitoring process as claimed in any one of claims10
1 to 9 wherein said AC frequency is lower than 1kHz.
[Claim 11]
Thermal impedance monitoring process as claimed in any one of claims
1 to 10 wherein said AC frequency is the fundamental frequency powering the
converter or the fundamental output frequency ffund of the converter.15
[Claim 12]
Converter comprising sensor means (53) on a power semiconductor
switch die of said converter for sensing a temperature of said power
semiconductor switch die, analog to digital converter means (54), sampling
means (55) and a processor (56) provided with memory means (57) for storing20
and running a software configured for executing the thermal impedance
monitoring process as claimed in any one of claims 1 to 11.
[Claim 13]
Converter as claimed in claim 12 wherein said sensor (53) means are
designed to sense a temperature sensitive electrical parameter of said power25
semiconductor switch die.
[Claim 14]
Permanent memory means (57) comprising a software comprising
33
instructions for executing the thermal impedance monitoring process as
claimed in any one of claims 1 to 11 when executed by a processor.