Description:TECHNICAL FIELD
The present disclosure generally relates to the field of controlling switched reluctance machine, and more particularly relates to a method and a system for current control of the switched reluctance machine.
BACKGROUND OF THE DISCLOSURE
The information disclosed in this background section is only for enhancement of understanding of the general background of the disclosure and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
In general, electrical machines have been widely utilized as motors and generators in an extensive range of industrial applications for more than a century. A reluctance machine is an electrical machine in which torque is produced by a tendency of movable part of the machine to move into a position where an inductance of an excited winding is maximized. The switched reluctance machine (SRM) is a type of the reluctance machine where the windings are energized as a function of the position of the movable part of the machine.
In general, the switched reluctance machines (SRM) need precise tracking of current reference in order to generate required torque. All the well-known techniques of phase current control of SRM are particularly challenging because of the non-linear dependence of flux-linkages both on phase current and rotor position. Therefore, several existing techniques are mostly dependent on information of flux-linkage characteristics of SRM. However, obtaining the flux-linkage characteristics involves time taking experiments and modelling these characteristics requires two-dimensional look-up tables or offline curve fitting techniques. The existing techniques suffer from various disadvantages, such as, high torque ripple, low torque density, vibration, acoustic noise, bulkiness, increased manufacturing costs, poor reliability and and/or poor performance.
Accordingly, there is a need for a technique that overcomes the limitations stated above in relation to the existing technology.

SUMMARY OF THE DISCLOSURE
In an embodiment, the present disclosure relates to a method for controlling switched reluctance machine (SRM). The method includes receiving a plurality of reference currents. In a non-limiting example, the plurality of reference currents is at least one of real-time values, predetermined values. The method further includes receiving at least one measured value of phase current and algebraic differentiation estimator coefficients. The method further includes estimating a first current rate based on the plurality of reference currents, the at least one measured value of phase current and the algebraic differentiation estimator coefficients. The method further includes predicting a phase current at future time instant, based on the received measured value of phase current and the estimated first current rate. The method further includes receiving at least one predetermined target reference current and determining a current slope, based on the received at least one predetermined target reference current and the predicted phase current. The method further includes estimating an average net disturbance voltage to an equivalent inductance ratio based on the estimated first current rate, direct current (DC) bus voltage, duty ratio, window length and an equivalent inductance. The method further includes computing a duty ratio for the at least one of real-time values, predetermined target reference current based on the average net disturbance voltage to an equivalent inductance ratio and the determined current slope. The method includes upon computing the duty ratio, generating a switching pulse for controlling the SRM based on the computed duty ratio.
In yet another embodiment, the present disclosure relates to a system for controlling switched reluctance machine (SRM). The system includes a memory, a processor, and the memory is communicatively coupled with the processor. The processor configured to receive a plurality of reference currents. In a non-limiting example, the plurality of reference currents is at least one of real-time values, predetermined values. The processor is further configured to receive at least one measured value of phase current and algebraic differentiation estimator coefficients. The processor is further configured to estimate a first current rate based on the plurality of reference currents, the at least one measured value of phase current and the algebraic differentiation estimator coefficients. The processor is further configured to predict a phase current at future time instant, based on the received measured value of phase current and the estimated first current rate. phase current and the algebraic differentiation estimator coefficients. The processor is further configured to receive at least one predetermined target reference current and determine a current slope, based on the received at least one predetermined target reference current and the predicted phase current. The processor is further configured to estimate an average net disturbance voltage to an equivalent inductance ratio based on the estimated first current rate, direct current (DC) bus voltage, duty ratio, window length and an equivalent inductance. The processor is configured to compute a duty ratio for the predetermined target reference current based on the average net disturbance voltage to an equivalent inductance ratio and the determined current slope. Lastly, the processor upon computing the duty ratio, further configured to generate a switching pulse for controlling the SRM based on the computed duty ratio.
The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS
Features, aspects, and advantages of embodiments of the disclosure will be described below with reference to the accompanying drawings, in which reference numerals denote like elements, and wherein:
Figure 1 illustrates an environment diagram of a system for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
Figure 2A-2H functional flow diagrams for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
Figure 3 illustrates a block diagram of a system for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
Figure 4 illustrates a flowchart of a method for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
Figure 5 illustrates exemplary graphs for calculating a window length (W_(l )) and an equivalent inductance 〖(L〗_eq) for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
Figure 6 illustrates exemplary graphs showing experimental results of controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
It should be appreciated by those skilled in the art that any block diagram herein represents conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION OF THE DISCLOSURE
The following detailed description of example embodiments refers to the accompanying drawings. The foregoing disclosure provides illustration and description but is not intended to be exhaustive or to limit the implementations to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the implementations. Further, one or more features or components of one embodiment may be incorporated into or combined with another embodiment (or one or more features of another embodiment). Additionally, the flowchart and description of operations provided below relate to one of the various embodiments. It should be noted that it is possible to make other embodiments that do not exactly match the flowchart and its description. It is understood that in other embodiments one or more operations may be omitted, one or more operations may be added, one or more operations may be performed simultaneously (at least in part).
It will be apparent that apparatus and/or methods described herein may be implemented in different forms of hardware, software, or a combination of hardware and software. The actual specialized control hardware or software code used to implement these systems/apparatus and/or methods does not limit the implementations. Thus, the operation and behavior of the systems and/or methods are described herein without reference to specific software code. It is understood that software and hardware may be designed to implement the systems and/or methods based on the description herein.
Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of implementations includes each dependent claim in combination with every other claim in the claim set.
No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items and may be used interchangeably with “one or more.” Also, as used herein, the terms “has,” “have,” “having,” “include,” “including,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. Furthermore, expressions such as “at least one of [A] and [B],” “[A] and/or [B],” or “at least one of [A] or [B]” are to be understood as including only A, only B, or both A and B.
The foregoing disclosure provides illustration and description but is not intended to be exhaustive or to limit the implementations to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the implementations.
As discussed earlier, existing techniques are mostly dependent on information of flux-linkage characteristics of SRM. However, obtaining the flux-linkage characteristics involves time taking experiments and modelling these characteristics. Which may in turn require two-dimensional look-up tables or offline curve fitting techniques. This characterization and modelling of the characteristics are quite of time consuming and complex. The existing techniques suffer from various disadvantages, such as, high torque ripple, low torque density, vibration, acoustic noise, bulkiness, increased manufacturing costs, poor reliability and and/or poor performance.
The methods and systems of the present disclosure solve a technical problem of how to provide a simple and model independent predictive current control of switched reluctance machine. The present technique may be utilized for control of SRM in many applications such as traction (electric vehicles, railway traction and aerospace applications) and power generation via renewable energy sources.
Embodiments disclosed herein provide a method and system for controlling switched reluctance machine (SRM). The present disclosure may utilize an average net disturbance voltage to an equivalent inductance ratio, an equivalent inductance to control the SRM. Further, the present disclosure may facilitate for a simple, model-independent predictive current control of switched reluctance machine (SRM). The present disclosure may also facilitate for a model independent predictive current control for SRM with a real-time RMS tracking error minimization for computing of optimal equivalent inductance (single number), and window of moving average (single number) and computation of duty ratio for target current tracking in every switching interval without the knowledge of machine model in all operating conditions (unsaturated as well as saturated), with fixed switching frequency operation of switched reluctance machine in current control mode.
Figure 1 illustrates an environment diagram of a system for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
As shown in figure 1, the environment 100 diagram of system for controlling switched reluctance machine (SRM) is disclosed. The environment 100 comprises a controller 102, a switched reluctance machine (SRM) 104. The controller 102 may be communicatively and electrically coupled with the SRM 104 to perform the one or more desired functions of the present disclosure.
In a non-limiting embodiment, the controller 102 may receive a power supply from a regulated power supply. In a non-limiting example, the controller 102 may be any known electronic or power electronic controller to implement the present disclosure. The controller 102 may control the SRM 104 to act as a means for one or more operations such as starting, stopping the machine, facilitating for forward or reverse rotation, selecting and regulating the speed, regulating or limiting the torque, and protecting against overloads and other electrical faults.
In a non-limiting embodiment, the controller 102 may control the SRM without requiring any complex calculations or any characteristics of the machine. A detailed explanation of the system for controlling the switched reluctance machine (SRM) is provided in the forthcoming paragraphs in conjunction with Figures 2-4.
Figure 2A-2H illustrates functional diagrams for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
In an embodiment, Figure 2A represents a functional diagram 200 of an exemplary flow for controlling switched reluctance machine (SRM), in accordance with one or more embodiments of the present disclosure. The order in which the functional diagram 200 is described is not intended to be construed as a limitation, and any number of the described functional blocks may be combined in any order to implement the process. Additionally, individual blocks may be deleted from methods without departing from the spirit and scope of the subject matter described. Furthermore, each function can be implemented in any suitable hardware, software, firmware, or combination thereof. However, for ease of explanation, in the embodiments described below, the functional 200 may be considered to be implemented by the controller 102 for controlling the SRM and/or by the processor 300 of the controller 102 of Figure 3.
At block 202, the functional diagram 200 may include computing the first current rate at present time instant (k) inrate(k). The first current rate inrate(k) may be calculated based on one or more configurations such as an online mode, and off-line mode, based on the type of currents being received, as discussed in detail below. Without any limitation, the different configurations may be implemented via a selection of inputs received via switches or control panel. The received currents may be at least a reference currents, and measured currents, respectively. Further, the received reference currents may be real-time references i*n(k) etc. Without any limitation, the offline mode of computing first current rate may be implemented by receiving plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), a sampling time period (Ts) to compute first current rate inrate1(k), as shown in Figure 2B. Further, the first current rate inrate(k) may be calculated based on at least one measured value of phase current (in(k)), a sampling time period (Ts) and algebraic differentiation estimator coefficients. The at least one measured value of phase current may be stored as a predefined set of measured values (wi) to calculate the first current rate inrate2(k), as shown in Figure 2C. Further, the first current rate may be calculated based on the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), at least one measured value of phase current (i_n (k)), a sampling time period (Ts) and algebraic differentiation estimator coefficients, as shown in Figure 2D.
At block 204, the functional diagram 200 may include predicting phase current for future time instant i_n^p (k+1). The prediction may include receiving the first current rate in rate(k) and a sampling time period (Ts), as shown in Figure 2E. In one non-limiting implementation i_n^p (k+1)= in(k).
At block 206, the functional diagram 200 may include computing future required current rate. The future required current rate may be calculated based on the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), phase current for future time instant i_n^p (k+1), and a sampling time period (Ts), as shown in Figures 2F-2G.
At block 208, the functional diagram 200 may include determining real-time equivalent inductance (Leq) and moving average window (Wl). The real-time equivalent inductance and moving average window may be calculated online based on at least one of reference currents i_n^* (k), the first current rate in rate(k) , a rotor position θ_m (k), a user input information such as number of rotor poles of the machine N_r, a turn on turn off angles (ρ_on, ρ_off ), a maximum speed ω_mx, a maximum current I_mx , a minimum inductance L_mn, of the SRM and a direct current (DC) bus voltage V_dc, as discussed in earlier embodiments of Figures 1, 3-4 and as shown Figure 2H.
At block 210, the functional diagram 200 may include estimation of average disturbance voltage to inductance ratio. The average disturbance voltage to inductance ratio may be calculated based on the first current rate i_n^rate (k), a DC bus voltage V_dc, a present switching cycle duty ratio d_n (k), the equivalent inductance L_eq,and the window length W_l, as discussed in earlier embodiments of Figures 1, 3-4 and as shown Figure 2H.
At block 212, the functional diagram 200 may include computing duty ratio for the next switching interval to control the SRM. The duty ratio may be calculated based on the future required current rate, average disturbance voltage to inductance ratio, as discussed in relation to other embodiments of Figures 1, 3-4 and as shown Figure 2H.
Figure 3 illustrates a block diagram of a system for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
In a non-limiting embodiment of the present disclosure, as discussed earlier, the controller 102 and the SRM are communicatively and electrically coupled with each other to perform the desired functions of the present disclosure. The controller 102 may comprise a processor 300, a memory 302, a user interface 304, and a communication interface 306, which are communicatively coupled with each other to perform the desired functions of the present disclosure. Optionally, the controller 102 may be communicatively coupled with a user device or a remote-control panel to receive one or more instructions from a user or an operator.
In a non-limiting embodiment of the present disclosure, the controller 102 may receive a regulated power supply from utility power supply. In a non-limiting example, the utility power supply may be any known utility power supply of a single phase or three phase or any suitable power supply. Without any limitation, any active power source may be used to provide power supply to the controller, as discussed in earlier embodiments.
In the illustrated figure, the processor 300 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. However, individual one of the ordinary skill will appreciate that in other embodiments, the controller 102 may also form a part of the processors 300 and may be implemented through software or hardware or a suitable combination of software and hardware as per the embodiment requirements of the present disclosure. In said embodiment, the processor 300 may perform all the functions carried out by the system to control the SRM. In one non-limiting example, the controller 102 may calculate an average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)) and an equivalent inductance 〖(L〗_eq) to compute a duty ratio (dn(k+1)). The duty ratio may be used to generate a switching pulse for controlling the SRM. Without requiring any characterization and modelling of the characteristics, which are quite time-consuming and complex.
In one non-limiting embodiment of the present disclosure, the processor 300 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and/or any devices that manipulate signals based on operational instructions. Among other capabilities, the at least one processor 300 may be configured to fetch and execute computer-readable instructions stored in the memory 302.
In one non-limiting embodiment of the present disclosure, the memory 302 may include any computer-readable medium or computer program product known in the art including, for example, volatile memory, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), and/or non-volatile memory, such as read only memory (ROM), erasable programmable ROM, and flash memories. Data/information may be stored within the memory 302 in the form of various data structures. The memory 302 may also store other data such as temporary data and temporary files, generated by the processors 300 or the controller for performing the various functions of the present disclosure. In yet another non-limiting embodiment of the present disclosure, the memory 302 may comprise the data. The data may include, without limiting to, a meta data, any additional or supplemental data to perform the desired functions of the present disclosure. In a non-limiting example, the data may include one or more operating parameters, preset trigger conditions, and errors pertaining to the control the SRM. In yet another non-limiting embodiment of the present disclosure may be implemented using hardware, and/or software, or partly by hardware and partly by software or firmware.
In one non-limiting embodiment of the present disclosure, the processor 300 may optionally receive a user input via the user interface 304. In a non-limiting example, the operator or the test engineer may interact with the controller 102 to input the one or more parameters as discussed earlier. The processor 300 may communicate with the user device via the communication interface 306. In a non-limiting example, the communication interface 306 may refer to a hardware or a software suitable for transmitting and receiving data between the controller 102 and the user device or the SRM controller panel.
In an embodiment, the controller 102 to control the SRM, may receive a plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), without any limitation the plurality of reference currents may be at least one of predetermined values (〖i^*〗_n (k), 〖i^*〗_n (k+1)), real-time values i*n(k). The controller 102 may receive at least one measured value of phase current (in(k)), and algebraic differentiation estimator coefficients. In a non-limiting example, the measured value of phase current (in(k)) may be a real-time measured value of the at least one phase current of the SRM. The controller 102 based on the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), at least one measured value of phase current and the algebraic differentiation estimator coefficients may estimate a first current rate (inrate(k)). The controller 102 to estimate the first current rate (inrate(k)) may compute a phase current reference slope based on the received plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), at least one measured value of phase current (in(k)) and algebraic differentiation estimator coefficients.
In yet another embodiment, the controller 102 based on the measured value of phase current and the estimated first current rate (inrate(k)), may further predict a phase current (i^p n(k+1)) at future time instant. The controller 102 is based on the received at least one predetermined target reference current (〖i^*〗_n (k+2)) and the predicted phase current (i^p n(k+1)), may receive at least one predetermined target reference current (〖i^*〗_n (k+2)) and determine a current slope. Further, the controller 102 based on the estimated first current rate (inrate(k)), direct current (DC) bus voltage Vdc, duty ratio d(k), window length (W_(l )) and an equivalent inductance 〖(L〗_eq) may estimate an average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)). Furthermore, the controller 102 based on the average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)) and the determined current slope computing a duty ratio (dn(k+1)) for the predetermined target reference current (〖i^*〗_n (k+2)). The controller upon computing the duty ratio (dn(k+1)), may generate a switching pulse for controlling the SRM based on the computed duty ratio (dn(k+1)).
In yet another embodiment, the controller 102 may compute the duty ratio (dn(k+1)) based on computing a gain based on the determined current slope and the average net equivalent disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)). The controller may also perform inversion on the gain with an equivalent inductance to DC bus voltage.
In yet another embodiment, as discussed earlier the controller 102 may determine the window length (W_(l )) and the equivalent inductance 〖(L〗_eq) to estimate the average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)). The controller 102 may receive an electrical position of a rotor and calculate a start angle and a stop angle of the rotor based on the user inputs such as at least one of turn on, turn off angles, rated speed of the machine, rated DC bus voltage, rated current, and minimum inductance of the machine. The controller 102 may receive an error value between the measured current and predetermined reference currents. The controller 102 may compute a root mean square (RMS) error within electrical cycle based on the electrical rotor position, start and stop angles of the rotor and the error value between measure phase current and reference phase current. The controller 102 may determine the number of elapsed electrical cycles using an electrical cycle counter. The controller 102 may perform decrementing linearly equivalent inductance of a current controller between a maximum and a minimum value based on the number of elapsed electrical cycles. The controller 102 may perform determining the window length and the equivalent inductance based on the rotor position, the start angle and the stop angle of the rotor, the error value between measure phase current and reference phase current, the RMS error, and the elapsed electrical cycle count, as shown in figure 5B-5C.
In yet another embodiment the controller 102 may determine the window length (W_(l )) and the equivalent inductance 〖(L〗_eq) estimate the average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)). The controller 102 may determine a real time minimum RMS error based on the computed RMS error and identifying the electrical cycle which provides the minimum RMS error. The controller 102 may obtain an updated decremented equivalent inductance value between the maximum and a minimum value based on the determined electrical cycle count that corresponds to real time minimum RMS error, as shown in figure 5B-5C. The controller 102 may select the updated decremented equivalent inductance between the maximum and the minimum value based on the real time minimum RMS error. The controller 102 may update the elapsed electrical cycle and the window length when the real time minimum RMS error is within a predetermined limit and obtain the updated decremented equivalent inductance as the desired equivalent inductance of the current controller, as shown in figure 5B-5C. In an embodiment, the figure 5A shows current tracking with linearly decrementing inductance and current tracking with final optimal inductance. In a non-limiting example, the SRM may be controlled based on precise tracking as shown in exemplary graphs showing experimental results of controlling switched reluctance machine (SRM). The figure 6A shows square current reference pulse tracking and figure 6B shows experimental results indicating low torque ripple, and optimal current reference tracking.
According to one exemplary embodiment, the controller 102 may be communicatively coupled with the test engineer’s computing device or a control panel. In a non-limiting example, the test engineer’s computing device or the control panel may be a mobile or portable computing device, a desktop computer, a server, any switch gear and/or the like.
Figure 4 illustrates a flowchart of a method for controlling switched reluctance machine (SRM), in accordance with some embodiments of the present disclosure.
Figure 4 represents a method flow of an exemplary method for controlling switched reluctance machine (SRM), in accordance with one or more embodiments of the present disclosure. The order in which the method 400 is described is not intended to be construed as a limitation, and any number of the process blocks described may be combined in any order to implement the process. Additionally, individual blocks may be deleted from methods without departing from the spirit and scope of the subject matter described. Furthermore, the process can be implemented in any suitable hardware, software, firmware, or combination thereof. However, for ease of explanation, in the embodiments described below, the method 400 may be considered to be implemented by the controller 102 for method for controlling switched reluctance machine (SRM) by the processor 300 of the controller 102 of Figure 3.
At step 402, the method 400 may include receiving a plurality of reference currents, as discussed in earlier embodiments of Figures 1-3.
At step 404, the method 400 may include receiving at least one measured value of phase current and algebraic differentiation estimator coefficients, as discussed in earlier embodiments of figures 1-3.
At step 406, the method 400 may estimate a first current rate, as discussed in earlier embodiments of figures 1-3.
At step 408, the method 400 may include predicting a phase current at future time instant, as discussed in earlier embodiments of figures 1-3.
At step 410, the method 400 may include receiving at least one predetermined target reference current and determine a current slope, as discussed in earlier embodiments of figures 1-3.
At step 412, the method 400 may include estimating an average net disturbance voltage to an equivalent inductance ratio, as discussed in earlier embodiments of figures 1-3.
At step 414, the method 400 may include computing a duty ratio for the predetermined target reference current, as discussed in earlier embodiments of figures 1-3.
At step 416, the method 400 may include generating a switching pulse for controlling the SRM based on the computed duty ratio, as discussed in earlier embodiments of figures 1-3.
The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
Alternatives will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the disclosed embodiments.
Furthermore, one or more computer-readable storage media may be utilized in implementing embodiments consistent with the present disclosure. A computer-readable storage medium refers to any type of physical memory on which information or data readable by a processor may be stored. Thus, a computer-readable storage medium may store instructions for execution by one or more processors, including instructions for causing the processor(s) to perform steps or stages consistent with the embodiments described herein. The term “computer- readable medium” should be understood to include tangible items and exclude carrier waves and transient signals, i.e., are non-transitory.
Suitable processors include, by way of example, a general-purpose processor, a special purpose processor, a conventional processor, a digital signal processor, a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits, Field Programmable Gate Arrays circuits, any other type of integrated circuit, and/or a state machine.
Advantages of the embodiment of the present disclosure are illustrated herein- As previously indicated, the present disclosure facilitates a precise tracking of current reference for SRM to generate required torque, thereby, reducing torque ripple and losses and improving overall performance. The present technique may also facilitate for simple control of the SRM without requiring any time-consuming characteristics and complex calculations.

REFERENCE NUMERALS
Description Reference number
100 Exemplary Environment
102 Controller
104 Switched Reluctance Machine
200 Functional flow
300 Processor
302 Memory
304 User Interface
306 Communication Interface
400 Method
402-416 Method Steps , Claims:1. A method for controlling switched reluctance machine (SRM), comprising:
receiving a plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), wherein the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)) are predetermined values;
receiving at least one measured value of phase current (〖i^*〗_n (k)) and algebraic differentiation estimator coefficients;
estimating a first current rate (inrate(k)) based on the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), the at least one measured value of phase current (〖i^*〗_n (k)) and the algebraic differentiation estimator coefficients;
predicting a phase current (〖in〗^p (k+1)) at future time instant, based on the received measured value of phase current and the estimated first current rate (inrate(k));
receiving at least one predetermined target reference current (〖i^*〗_n (k+2)) and determining a current slope, based on the received at least one predetermined target reference current (〖i^*〗_n (k+2)) and the predicted phase current (〖in〗^p (k+1));
estimating an average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)) based on the estimated first current rate (inrate(k)), direct current (DC) bus voltage Vdc, duty ratio dn(k), window length (W_(l )) and an equivalent inductance 〖(L〗_eq);
computing a duty ratio (dn(k+1)) for the predetermined target reference current (i^* (k+2)) based on the average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)) and the determined current slope; and
upon computing the duty ratio (dn(k+1)), generating a switching pulse for controlling the SRM based on the computed duty ratio (dn(k+1)).

The method as claimed in claim 1, wherein estimating the first current rate (inrate(k)) based on the received plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), at least one measured value of phase current (〖i^*〗_n (k)) and algebraic differentiation estimator coefficients comprising: computing a phase current reference slope based on the received plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), at least one measured value of phase current (〖i^*〗_n (k)) and algebraic differentiation estimator coefficients.

3. The method as claimed in claim 1, wherein computing the duty ratio (dn(k+1) for the target reference current (〖i^*〗_n (k+2)) further comprising:
computing a gain based on the determined current slope and the average net equivalent disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)); and
performing inversion on the gain with an equivalent inductance to DC bus voltage.

4. The method as claimed in claim 1, wherein determining the window length (W_(l )) and the equivalent inductance 〖(L〗_eq) comprises:
receiving an electrical position of a rotor;
calculating a start angle and a stop angle of the rotor based on the user inputs: turn on, turn off angles, rated speed of the machine, rated DC bus voltage, rated current, and minimum inductance of the machine;
receiving an error value between the measured current and reference currents;
computing a root mean square (RMS) error within electrical cycle based on the electrical rotor position, start and stop angles of the rotor and the error value between measure phase current and reference phase current;
determining number of elapsed electrical cycles using an electrical cycle counter;
decrementing linearly equivalent inductance of a current controller between a maximum and a minimum value based on the number of elapsed electrical cycles;
determining the window length and the equivalent inductance based on the rotor position, the start angle and the stop angle of the rotor, the error value between measure phase current and reference phase current, the RMS error, and the elapsed electrical cycle count.

5. The method as claimed in claim 4, wherein determining the window length (W_(l )) and the equivalent inductance 〖(L〗_eq) further comprises:
determining a real time minimum RMS error based on the computed RMS error and identifying the electrical cycle which provides the minimum RMS error;
obtaining an updated decremented equivalent inductance value between the maximum and a minimum value based on the determined electrical cycle count that corresponds to real time minimum RMS error;
selecting the updated decremented equivalent inductance between the maximum and the minimum value based on the real time minimum RMS error;
updating the elapsed electrical cycle and the window length when the real time minimum RMS error is within a predetermined limit; and
obtaining the updated decremented equivalent inductance as the desired equivalent inductance of the current controller.

6. A system for controlling switched reluctance machine (SRM), comprises:
a memory; and
a processor;
the memory communicatively coupled with the processor, the processor configured to:
receive a plurality of reference currents (〖i^*〗_n (k), i^* (k+1)), wherein the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)) are predetermined values;
receive at least one measured value of phase current (〖i^*〗_n (k)) and algebraic differentiation estimator coefficients;
estimate a first current rate (inrate(k)) based on the plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), the at least one measured value of phase current (〖i^*〗_n (k)) and the algebraic differentiation estimator coefficients;
predict a phase current (〖in〗^p (k+1)) at future time instant, based on the received measured value of phase current and the estimated first current rate (inrate(k));
receive at least one predetermined target reference current (〖i^*〗_n (k+2)) and determining a current slope, based on the received at least one predetermined target reference current (〖i^*〗_n (k+2)) and the predicted phase current (i^p (k+1));
estimate an average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)) based on the estimated first current rate (inrate(k)), direct current (DC) bus voltage Vdc, duty ratio dn(k), window length (W_(l )) and an equivalent inductance 〖(L〗_eq);
compute a duty ratio (dn(k+1) for the predetermined target reference current (〖i^*〗_n (k+2)) based on the average net disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)) and the determined current slope; and
upon computing the duty ratio (dn(k+1)) generate a switching pulse for controlling the SRM based on the computed duty ratio (dn(k+1).

7. The system as claimed in claim 6, wherein to estimate the first current rate (inrate(k)) based on the received plurality of reference currents (〖i^*〗_n (k), 〖i^*〗_n (k+1)), at least one measured value of phase current (〖i^*〗_n (k)) and algebraic differentiation estimator coefficients, the processor is further configured to: compute a phase current reference slope based on the received plurality of reference currents (〖i^*〗_n (k), i^* (k+1)), at least one measured value of phase current (〖i^*〗_n (k)) and algebraic differentiation estimator coefficients.

8. The system as claimed in claim 6, wherein to compute the duty ratio (dn(k+1)) for the target reference current (〖i^*〗_n (k+2)), the processor further configured to:
compute a gain based on the determined current slope and the net equivalent disturbance voltage to an equivalent inductance ratio (Ꝩnav(k)); and
perform inversion on the gain with an equivalent inductance to DC bus voltage.

9. The system as claimed in claim 6, wherein to determine the window length (W_(l )) and the equivalent inductance 〖(L〗_eq) the processor is further configured to:
receive an electrical position of a rotor.
calculate a start angle and a stop angle of the rotor based on the turn on, turn off angles, DC bus voltage, rated speed, rated current, minimum inductance of the machine;
receive an error value between the measured current and phase current reference;
compute a root mean square (RMS) error of an electrical cycle based on the electrical rotor position, start and stop angles of the rotor and the error value of the between the measured current and phase current reference;
determine number of elapsed electrical cycles using an electrical cycle counter;
decrement linearly equivalent inductance of a current controller between a maximum and a minimum value based on the number of elapsed electrical cycles;
determine the window length and the equivalent inductance based on the rotor position, the start angle and the stop angle of the rotor, the error value between the measured current and phase current reference, the RMS error, the elapsed electrical cycle count and the decremented equivalent inductance.

10. The system as claimed in claim 9, wherein to determine the window length (W_(l )) and the equivalent inductance 〖(L〗_eq) the processor is further configured to:
determine a real time minimum RMS error based on the computed RMS error and identifying the electrical cycle which provides the minimum RMS error;
obtain an updated decremented equivalent inductance value between the maximum and a minimum value based on the determined electrical cycle count that corresponds to real time minimum RMS error;
select the updated decremented equivalent inductance between the maximum and the minimum value based on the real time minimum RMS error;
update the elapsed electrical cycle and the window length when the real time minimum RMS error is within a predetermined limit; and
obtain the updated decremented equivalent inductance as the desired equivalent inductance of the current controller.