Description:TECHNICAL FIELD
[0001] The present disclosure relates to the field of semiconductor devices. In particular, the present disclosure relates to Gallium Nitride (GaN)-based High Electron Mobility Transistors (HEMT) including a graded p-type passivation structure, and a method of fabricating a semiconductor device.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present disclosure. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed disclosure, or that any publication specifically or implicitly referenced is prior art.
[0003] Traditional High Electron Mobility Transistors (HEMT) 100A, as illustrated in FIG. 1A, are well-known for their ability to manage high power and high frequencies. This type of transistors is highly suitable for the applications like power conversion, radio frequency transmission, and electric vehicles. Gallium Nitride (GaN)-based HEMTs 100B, as illustrated in FIG. 1B, are used in high-power and high-frequency applications. However, in power devices, the presence of traps in GaN HEMTs leads to an increase in ON resistance following an OFF-state switching event, thereby causing higher power loss, self-heating, and operational instabilities, such as threshold voltage shifts. The primary factor driving this trapping behavior is an occurrence of localized high electric fields in a channel region of the GaN-based HEMTs. Additionally, these intense localized fields can trigger premature breakdown of the GaN-based HEMTs, severely impacting performance and reliability of the GaN HEMTs and limiting their practical potential.
[0004] Several strategies have been explored to control or suppress the channel electric field, including the use of field plates, buffer doping modifications, Reduced Surface Field (RESURF) designs, and improvements in surface passivation. However, these approaches often fall short in fully suppressing the electric field peak. Currently, p-type oxide passivation is utilized to redistribute the electric field across gate-to-drain access region of the GaN HEMT. However, the peaking of the channel electric field at gate/field plate edge and/or drain edge is not completely suppressed and surface trapping is not mitigated.
[0005] Therefore, there is, a need to provide an improved GaN HEMTs to at least overcome the above-mentioned drawbacks.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] Some of the objects of the present disclosure, which at least one embodiment herein satisfies, are as listed below.
[0007] A general object of the present disclosure is to provide a multi-layer passivation structure with different p-type concentrations that results in a junction formation at the interface of layers.
[0008] Another object of the present disclosure is to provide a graded P-type passivation layer that suppresses dynamic RON, resulting in frequency-independent dynamic RON, and improves the breakdown voltage of the GaN HEMTs.
[0009] Another object of the present disclosure is to provide a graded P-type passivation layer for Gallium Nitride (GaN) High Electron Mobility Transistors to suppress Electro-Luminescence (EL) intensity, indicating a reduced and uniformly distributed channel electric field in the GaN HEMT, thereby redistributing channel electric field between a gate electrode and a drain electrode of the GaN HEMTs.
[0010] Another object of the present disclosure is to provide a graded P-type passivation layer that enhances the reliability of the GaN HEMTs under real power converter operation.

SUMMARY
[0011] Aspects of the present disclosure relate to the field of semiconductor devices. In particular, the present disclosure relates to Gallium Nitride (GaN)-based High Electron Mobility Transistors (HEMT) including a graded p-type passivation structure, and a method of fabricating a semiconductor device.
[0012] In an aspect, the present disclosure relates to GaN HEMT. The GaN HEMT includes a source electrode, a drain electrode formed over a barrier layer, and a gate electrode positioned between the source electrode and the drain electrode. The GaN HEMT includes a graded p-type passivation structure formed over at least one of the barrier layer or a GaN cap layer. The graded p-type passivation structure includes a plurality of layers formed of a p-type oxide material. Each of the plurality of layers is configured with p-type doping concentration to form junctions at the interface of the plurality of layers. The junctions at the interface may redistribute channel electric field between the gate electrode and the drain electrode, reduce peaking of the channel electric field, suppress dynamic ON resistance (ΔRON), enhance breakdown voltage, suppress electro-luminescence (EL) intensity, indicating a reduced and uniformly distributed channel electric field in the GaN HEMT, and improve reliability of the GaN HEMT under real power converter operation.
[0013] In an embodiment, the p-type oxide material may include a single material selected from a group consisting of Aluminium Titanium Oxide (AlTiO) or other p-type semiconducting oxides including Copper Oxide or Nickel Oxide.
[0014] In an embodiment, the p-type doping concentration of each of the plurality of layers may be varied by altering a ratio of deposition cycles of Aluminium Oxide (Al₂O₃) to Titanium Dioxide (TiO₂) during at least one of: atomic layer deposition (ALD), chemical vapor deposition (CVD), evaporation deposition, and sputtering deposition.
[0015] In an embodiment, the graded p-type passivation structure may include at least three layers. At least three layers may include a highly doped p-type layer, a medium-doped p-type layer, and a lightly doped p-type layer.
[0016] In an embodiment, the graded p-type passivation structure may be deposited under the gate electrode and configured as a gate dielectric.
[0017] In an embodiment, the graded p-type passivation structure may be deposited over a passivation layer composed of any or a combination of Aluminium Oxide (Al₂O₃), Silicon Nitride (SiNx), and Silicon Dioxide (SiO₂).
[0018] In an embodiment, the junctions at the interface of the plurality of layers may form a plurality of depletion regions to suppress the peaking of the channel electric field at an edge of at least one of the gate electrode, a field plate, and the drain electrode.
[0019] In an embodiment, the dynamic ON resistance (ΔRON) may be frequency-independent across switching frequencies under real power converter operation.
[0020] In an embodiment, the barrier layer formed of at least one of Aluminium Nitride (AlN) barriers, graded Aluminium Gallium Nitride (AlGaN) barriers, or back barrier structures may be deposited over a GaN channel layer. The GaN channel layer may be deposited over a buffer layer selected from any or a combination of carbon-doped buffer layer, iron-doped buffer layer, or carbon-iron co-doped buffer layers.
[0021] In an embodiment, the buffer layer may be deposited over a substrate. The substrate may be composed of a material selected from Silicon (Si), Silicon Carbide (SiC), sapphire, Diamond, GaN, or Qromis substrate technology (QST).
[0022] In an aspect, the present disclosure relates to a method of fabricating a semiconductor device. The method includes forming ohmic contacts on a source electrode and a drain electrode by depositing an ohmic metal stack structure followed by an annealing process. The method includes performing a mesa etching process to define active regions and electrically isolate individual devices on a semiconductor substrate. The method includes depositing a gate metal, including one or more Schottky metal stacks over a gate electrode, depositing a first passivation layer, including a low-doped p-type semiconductor material, using a deposition technique, and depositing a second passivation layer, including a p-type semiconductor material, using the deposition technique. The second passivation layer is formed of a doping concentration different from the first passivation layer. The method includes depositing a third passivation layer including a p-type semiconductor material using the deposition technique, where the third passivation layer is formed of a doping concentration different from the first and second passivation layers. The first, second, and third passivation layers may be deposited to improve the electric field distribution between the gate electrode and the drain electrode. The method includes performing a low-temperature annealing process for the enhancement of interfaces formed between the first, second, and third passivation layers. The method includes etching one or more openings through the first, second, and third passivation layers to establish electrical contact with underlying metal contacts, and thickening the source and drain electrodes by depositing a conductive metal and optionally forming one or more field plates, where the one or more field plates may be any or a combination of drain-connected field plates, source-connected field plates, or gate-connected field plates.
[0023] In an embodiment, the ohmic metal stack structure may include one or more metal layers selected from any or a combination of titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), nickel (Ni), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), and gold (Au).
[0024] In an embodiment, the one or more schottky metal stacks may be selected from any or a combination of nickel (Ni), platinum (Pt), palladium (Pd), and gold (Au).
[0025] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0027] FIGs. 1A and 1B illustrate cross-sectional views of a conventional Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) with a standard passivation, and a conventional GaN HEMT with a single p-type passivation, respectively.
[0028] FIG. 2 illustrates a cross-sectional view of a GaN HEMT with a graded p-type passivation structure, in accordance with an embodiment of the present disclosure.
[0029] FIGs. 3A and 3B illustrate graphical representations depicting a comparison of the dynamic ON resistance (RON) of different devices, in accordance with an embodiment of the present disclosure.
[0030] FIGs. 4A, 4B, and 4C illustrate graphical representations depicting switching frequency-dependent ΔRON for different devices, in accordance with an embodiment of the present disclosure.
[0031] FIGs. 5A and 5B illustrate graphical representations depicting a comparison of three terminal off-state breakdowns of different devices, and an Electroluminescence (EL) intensity for different devices, in accordance with an embodiment of the present disclosure.
[0032] FIGs. 6A–6G illustrate cross-sectional views of GaN power HEMT structures with graded p-type passivation of different configurations, in accordance with an embodiment of the present disclosure.
[0033] FIG. 7 illustrates a flowchart of a method of fabricating a semiconductor device, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0034] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0035] The ensuing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as set forth.
[0036] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.
[0037] Also, it is noted that individual embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.
[0038] The word “exemplary” and/or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.
[0039] Reference throughout this specification to “one embodiment” or “an embodiment” or “an instance” or “one instance” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout 8 this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
[0041] The present disclosure relates to Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT) including a graded p-type passivation structure, and a method of fabricating a semiconductor device.
[0042] In an aspect, the present disclosure relates to GaN HEMT. The GaN HEMT includes a source electrode, a drain electrode formed over a barrier layer, and a gate electrode positioned between the source electrode and the drain electrode. The GaN HEMT includes a graded p-type passivation structure formed over at least one of the barrier layer or a GaN cap layer. The graded p-type passivation structure includes a plurality of layers formed of a p-type oxide material. Each of the plurality of layers is configured with p-type doping concentration to form junctions at the interface of the plurality of layers. The junctions at the interface may redistribute channel electric field between the gate electrode and the drain electrode, reduce peaking of the channel electric field, suppress dynamic ON resistance (ΔRON), enhance breakdown voltage, suppress electro-luminescence (EL) intensity, indicating a reduced and uniformly distributed channel electric field in the GaN HEMT, and improve reliability of the GaN HEMT under real power converter operation.
[0043] In an aspect, the present disclosure relates to a method of fabricating a semiconductor device. The method includes forming ohmic contacts on a source electrode and a drain electrode by depositing an ohmic metal stack structure followed by an annealing process. The method includes performing a mesa etching process to define active regions and electrically isolate individual devices on a semiconductor substrate. The method includes depositing a gate metal, including one or more Schottky metal stacks over a gate electrode, depositing a first passivation layer, including a low-doped p-type semiconductor material, using a deposition technique, and depositing a second passivation layer, including a p-type semiconductor material, using the deposition technique. The second passivation layer is formed of a doping concentration different from the first passivation layer. The method includes depositing a third passivation layer including a p-type semiconductor material using the deposition technique, where the third passivation layer is formed of a doping concentration different from the first and second passivation layers. The method includes performing a low-temperature annealing process for the enhancement of interfaces formed between the first, second, and third passivation layers. The method includes etching one or more openings through the first, second, and third passivation layers to establish electrical contact with underlying metal contacts, and thickening the source and drain electrodes by depositing a conductive metal and optionally forming one or more field plates.
[0044] Various embodiments of the present disclosure will be explained in detail with reference to FIGs. 2-7.
[0045] FIGs. 2 illustrates a cross-sectional view of a GaN HEMT with a graded p-type passivation structure, in accordance with an embodiment of the present disclosure.
[0046] With reference to FIG. 2, the GaN HEMT (200) may include a source electrode (202a), a drain electrode (202b), and a gate electrode (202c) deposited on a GaN layer or a GaN cap layer (204). In an embodiment, the source electrode (202a) and the drain electrode (202b) may be formed over an Aluminium Gallium Nitride (AlGaN) barrier layer (206). The gate electrode (202c) may be positioned between the source electrode (202a) and the drain electrode (202b). The AlGaN barrier layer (206) may be formed on a GaN channel layer (208). An interface between the GaN channel layer (208) and the AlGaN barrier layer (206) may form a two-dimensional electron gas (2DEG). The AlGaN barrier layer (206) may be deposited over the GaN channel layer (208). The GaN channel layer (208) may be deposited over a buffer layer (210). The buffer layer (210) may be selected from any or a combination of carbon-doped buffer layer, iron-doped buffer layer, or carbon-iron co-doped buffer layers.
[0047] In an embodiment, the buffer layer (210) may be deposited over a substrate (212). The substrate may be composed of a material selected from any or a combination of Silicon (Si), Silicon Carbide (SiC), sapphire, Diamond, GaN, and Qromis substrate technology (QST).
[0048] In an embodiment, the GaN HEMT (200) may include a graded p-type passivation structure including a plurality of graded p-type passivation layers (214a, 214b, 214c). The graded p-type passivation structure may be formed over the AlGaN barrier layer (206) or the GaN cap layer (204). The plurality of graded p-type passivation layers (214a, 214b, 214c) may be formed of a p-type oxide material. The p-type oxide material may be a single material selected from a group consisting of Aluminium Titanium Oxide (AlTiO) or other p-type semiconducting oxides, including Copper Oxide or Nickel Oxide. Though the present disclosure discloses the graded p-type passivation structure with three stacked layers, any number of layers may be stacked in the graded p-type passivation structure. The layers may be made up of AlTiO, with different doping levels, namely a highly doped p-type (P+) layer (214a), which may be integrated with a medium-doped p-type layer (P) (214b), and a lightly doped p-type layer (P-) (214c). The order of the doping may be varied based on the requirement.
[0049] In an embodiment, each of the plurality of graded p-type passivation layers (214a, 214b, 214c) may be configured with p-type doping concentration to form junctions at the interface of the plurality of graded p-type passivation layers (214a, 214b, 214c). The p-type doping concentration of each of the graded p-type passivation layers (214a, 214b, 214c) may be varied by altering the ratio of deposition cycles of Aluminium Oxide (Al₂O₃) to Titanium Dioxide (TiO₂) during the deposition technique. The deposition technique may include, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), evaporation deposition, and sputtering deposition. The junctions at the interface of the graded p-type passivation layers (214a, 214b, 214c) may redistribute channel electric field between the gate electrode (202c) and the drain electrode (202b), reduce peaking of the channel electric field, suppress dynamic ON resistance (ΔRON), enhance breakdown voltage, suppress electro-luminescence (EL) intensity, indicating a reduced and uniformly distributed channel electric field in the GaN HEMT (200), and improve reliability of the GaN HEMT (200) under real power converter operation. The junctions at the interface of the graded p-type passivation layers (214a, 214b, 214c) may form a plurality of depletion regions to suppress the peaking of the channel electric field at the edge of the gate electrode (202c), a field plate, and the drain electrode (202b).
[0050] The dynamic ON resistance (ΔRON) may be characterized using a custom switching circuit. The measurement procedure of the dynamic ON resistance (ΔRON) may involve pulsing the gate electrode (202c) at a specific frequency (fs) from OFF (stress) to ON (measurement) state while a fixed DC voltage (Vsupply) was applied across a series combination of a resistor and the GaN HEMT (200). An evolution of the dynamic ON resistance (ΔRON) may be calculated by measuring drain voltage and current using Tektronix IsoVu probes. The dynamic ON resistance (ΔRON) may also be measured in the off-state of the GaN HEMT (200). The dynamic ON resistance (ΔRON) may be calculated as follows:

[0051] Finally, the breakdown voltage of the source electrode (202a), the drain electrode (202b), and the gate electrode (202c) may be measured. Further, Electroluminescence (EL) microscopy may be used to capture the EL intensity in semi-on state at a drain voltage of 50 V, and thus estimate the channel electric field profile of the GaN HEMT (200).
[0052] In an embodiment, the graded p-type passivation structure may be applicable to GaN HEMTs incorporating various buffer configurations, including but not limited to, carbon-doped, iron-doped, and carbon-iron co-doped buffer layers. Furthermore, the graded p-type passivation structure may also be implemented in GaN HEMTs devoid of a buffer region. In an embodiment, the graded p-type passivation structure may be further applicable to GaN HEMTs incorporating various barrier and cap layer configurations, including but not limited to, AlN barriers, graded AlGaN barriers, GaN cap layers, p-GaN gated HEMTs, and GaN HEMTs with back barrier structures.
[0053] FIGs. 3A and 3B illustrate graphical representations (300A, 300B) depicting comparison of the dynamic ON resistance (ΔRON) of a conventional GaN HEMT with a standard passivation layer G1 (as illustrated in FIG. 1A), a conventional GaN HEMT with a single p-type passivation G2 (as illustrated in FIG. 1B), and the proposed GaN HEMT with the multi-layered graded p-type passivation structure G3 (as illustrated in FIG. 2) under a switching circuit and off-state DC conditions, respectively. It is evident that G3 which has the p-type passivation structure shows the least dynamic ON resistance (ΔRON) compared to G1 and G2 under both switching and DC off-state conditions, thereby depicting an excellent dynamic performance.
[0054] FIGs. 4A-4C illustrate graphical representations (400A-400C) depicting variation of switching frequency dependent ∆RON for the conventional GaN HEMT with the standard passivation layer G1 (as illustrated in FIG. 1A), the conventional GaN HEMT with the single p-type passivation G2 (as illustrated in FIG. 1B), and the proposed GaN HEMT with the multi-layered graded p-type passivation structure G3 (as illustrated in FIG. 2), respectively, under hard-switching conditions with a supply voltage of 100 V and a duty cycle of 50%. FIGs. 4A-4C depicts that the G3 shows frequency-independent ∆RON, which is highly desirable for a transistor-based switch in power converters. Therefore, G3 showcases a robust circuit-based performance.
[0055] FIG. 5A illustrates a graphical representation (500A) depicting a comparison of three terminal off-state breakdown of the conventional GaN HEMT with the standard passivation layer G1 (as illustrated in FIG. 1A), the conventional GaN HEMT with the single p-type passivation G2 (as illustrated in FIG. 1B), and the proposed GaN HEMT with the multi-layered graded p-type passivation structure G3 (as illustrated in FIG. 2), respectively. FIG. 5A depicts an improved breakdown performance of G3 over the conventional G1 and G2 devices.
[0056] FIG. 5B illustrates EL intensity for the conventional GaN HEMT with the standard passivation layer G1 (as illustrated in FIG. 1A), the conventional GaN HEMT with the single p-type passivation G2 (as illustrated in FIG. 1B), and the proposed GaN HEMT with the multi-layered graded p-type passivation structure G3 (as illustrated in FIG. 2), respectively, captured at a drain voltage of 50 V and a drain current of 10 mA/mm. FIG. 5B depicts highly suppressed EL intensity for G3. EL intensity is a direct estimation of the channel electric field. Therefore, the channel electric field is highly suppressed in G3 compared to G1 and G2 devices.
[0057] FIGs. 6A-6G illustrate cross-sectional views of GaN power HEMT structures (600A-600F) with graded p-type passivation of different configurations, in accordance with an embodiment of the present disclosure.
[0058] With reference to FIGs. 6A-6G, the GaN power HEMT structures (600A-600F) with graded p-type passivation of different configurations are depicted. FIG. 6A depicts the GaN power HEMT structure (600A) having graded p-type passivation layers with p-type concentration of similar or different materials. FIGs. 6B and 6C depict the GaN power HEMT structures (600B, 600C) having graded p-type passivation layers in which a highly doped layer is deposited at the top or in the middle. FIG. 6D depicts the GaN power HEMT structure (600D) having the graded p-type passivation layers deposited directly on top of the GaN cap layer (204) or on top of the barrier with no cap region/layer. FIG. 6E depicts the GaN power HEMT structure (600E) having graded passivation layers that may be deposited under a gate contact as a gate dielectric with lesser thickness. FIG. 6F depicts the GaN power HEMT structure (600F) having graded passivation layers that may be deposited on top of the existing passivation layer (216) like Al₂O₃, SiNX/SiO2, or similar other materials conventionally used as passivation for GaN HEMTs. FIG. 6G depicts the GaN power HEMT structure (600G) having graded passivation layers that may be deposited directly on top of the barrier layer.
[0059] FIG. 7 illustrates a flowchart of a method (700) of fabricating a semiconductor device, in accordance with an embodiment of the present disclosure.
[0060] The fabrication of the semiconductor device (for example, GaN HEMT) may start with formation of source and drain electrodes with Ti/Al/Ni/Au metal stack, followed by 820° C 30 s rapid thermal annealing in N2 ambient temperature. The method (700) may carry out device isolation using Cl2/BCl3-based plasma etching up to the buffer region. The method (700) may include depositing Ni/Au based Schottky contacts using evaporation and annealing the Ni/Au based Schottky contacts at 300°C for 10 minutes in forming gas ambient. Further, the method (700) may include deposition of the passivation layers, where ICP-CVD may be used for the deposition of 50 nm SiO2 on G1 (i.e., the conventional GaN HEMT with the standard passivation layer). 50 nm of AlTiO may be deposited on G2 (i.e., the conventional GaN HEMT with the single p-type passivation) using a deposition technique, for example, but not limited to, Atomic Layer Deposition (ALD). AlTiO may be deposited using a cyclic deposition of Al2O3 followed by TiO2 at 250° C. The number of cycles deposited of each Al2O3 and TiO2 may determine the p-type nature and the stoichiometry of AlTiO, and as the TiO2 cycles are increased, the p-type nature of the oxide decreases. For sample G3 (i.e., the proposed GaN HEMT with the multi-layered graded p-type passivation structure), three layers of AlTiO may be deposited with varying cycles corresponding to different p-type concentrations. Firstly, a 20 nm layer may be deposited on the GaN cap layer (204) having a ratio of deposition cycles of Al2O3:TiO2 as 1:3 (P+), followed by the deposition of 20 nm AlTiO with the ratio of Al2O3:TiO2 as 1:7 (P), and finally, a 10 nm layer of AlTiO with the ratio of Al2O3:TiO2 as 1:12 (P-). Thus, using the three different cycles of Al2O3:TiO2 may achieve a graded p-type passivation for device G3. Finally, the contact opening at the source, drain, and gate electrodes may be carried out using reactive ion etching.
[0061] With reference to FIG. 7, at 702, the method (700) may include forming ohmic contacts on the source electrode (202a) and the drain electrode (202b) by depositing an ohmic metal stack structure followed by an annealing process. The ohmic metal stack structure may be a drain-source metal stack structure. The ohmic metal stack structure may include one or more metal layers selected from any or a combination of titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), nickel (Ni), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), and gold (Au).
[0062] At 704, the method (700) may include performing a mesa etching process to define active regions and electrically isolate individual devices on the semiconductor substrate (212). At 706, the method (700) may include depositing a gate metal including one or more schottky metal stacks over the gate electrode (202c). The one or more schottky metal stacks may be gate metal stacks and selected from any or a combination of nickel (Ni), platinum (Pt), palladium (Pd), and gold (Au).
[0063] At 708-1, the method (700) may include depositing a first passivation layer (214a) including a low-doped p-type semiconductor material using the ALD. At 708-2, the method (700) may include depositing a second passivation layer (214b) including a p-type semiconductor material using the ALD. The second passivation layer (214b) may be formed of a doping concentration different from the first passivation layer (214a). At 708-3, the method (700) may include depositing a third passivation layer (214c) including a p-type semiconductor material using the ALD. The third passivation layer (214c) may be formed of a doping concentration different from the first and second passivation layers (214a, 214b). By depositing the first passivation layer (214a), the second passivation layer (214b), and the third passivation layer (214c), the electric field distribution between the gate electrode (202c) and the drain electrode (202b) may be improved.
[0064] At 710, the method (700) may include performing a low temperature annealing process for enhancement of interfaces formed between the first, second, and third passivation layers (214a, 214b, 214c). At 712, the method (700) may include etching one or more openings through the first, second, and third passivation layers (214a, 214b, 214c) to establish electrical contact with underlying metal contacts. At 714, the method (700) may include thickening the source and drain electrodes (202a, 202b) by depositing a conductive metal and optionally forming one or more field plates for fabricating the GaN HEMT.
[0065] Therefore, the GaN HEMT may be fabricated with minimal dynamic ON resistance (ΔRON), enhanced breakdown voltage, and robust circuit operation. The GaN HEMTs with low dynamic ON resistance (ΔRON) and high breakdown voltage may have the potential to completely transform power electronics, resulting in a rapid adoption of the GaN HEMTs in data centers, telecommunications, renewable energy, and electric vehicles. The GaN HEMTs may be further stimulated by ongoing developments in manufacturing and material science, establishing GaN as a crucial facilitator of next-generation power applications as well as Radio Frequency (RF) applications. The graded p-type passivation layers of the GaN HEMT may enhance the reliability and dynamic performance of the GaN HEMTs under real power converter operation. The graded p-type passivation layers made of same material having different p-type concentrations may result in improved dynamic performance, enhanced breakdown voltage, and robust circuit operation of the GaN HEMTs.
[0066] While the foregoing describes various embodiments of the disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof. The scope of the disclosure is determined by the claims that follow. The disclosure is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the disclosure when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0067] The present disclosure provides graded p-type passivation layers for Gallium Nitride (GaN) based High Electron Mobility Transistors (HEMTs), significantly enhancing performance and reliability of the GaN HEMTs.
[0068] The present disclosure provides the graded p-type passivation layers that suppress dynamic RON, resulting in frequency-independent dynamic RON, and improve the breakdown voltage of the GaN HEMTs.
[0069] The present disclosure provides a multi-layer passivation structure with different p-type concentrations that results in a junction formation at the interface of layers, thereby relaxing the channel electric field peak near the gate/field plate edge.
[0070] The present disclosure provides a graded P-type passivation layer that enhances the reliability of the GaN HEMTs under real power converter operation.
[0071] The present disclosure provides a graded P-type passivation layer that suppresses Electro-Luminescence (EL) intensity, indicating a reduced and uniformly distributed channel electric field in the GaN HEMT.
, Claims:1. A Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) (200) comprising:
a graded p-type passivation structure formed over at least one of: a barrier layer (206) or a GaN cap layer (204), wherein the graded p-type passivation structure comprises a plurality of layers (214a, 214b, 214c) formed of a p-type oxide material,
wherein each of the plurality of layers (214a, 214b, 214c) is configured with p-type doping concentration to form junctions at the interface of the plurality of layers (214a, 214b, 214c), and
wherein the junctions at the interface redistribute channel electric field between a gate electrode (202c) and a drain electrode (202b), reduce peaking of the channel electric field, suppress dynamic ON resistance (ΔRON), enhance breakdown voltage, suppress electro-luminescence (EL) intensity, indicating a reduced and uniformly distributed channel electric field in the GaN HEMT (200), and improve reliability of the GaN HEMT (200) under real power converter operation.

2. The GaN HEMT (200) as claimed in claim 1, wherein the p-type oxide material comprises a single material selected from a group consisting of Aluminium Titanium Oxide (AlTiO) or other p-type semiconducting oxides comprising Copper Oxide or Nickel Oxide.

3. The GaN HEMT (200) as claimed in claim 2, wherein the p-type doping concentration of each of the plurality of layers (214a, 214b, 214c) is varied by altering a ratio of deposition cycles of Aluminium Oxide (Al₂O₃) to Titanium Dioxide (TiO₂) during at least one of: atomic layer deposition (ALD), chemical vapor deposition (CVD), evaporation deposition, and sputtering deposition.

4. The GaN HEMT (200) as claimed in claim 1, wherein the graded p-type passivation structure comprises at least three layers (214a, 214b, 214c) comprising a highly doped p-type layer, a medium doped p-type layer, and a lightly doped p-type layer, and wherein the graded p-type passivation structure is deposited under the gate electrode (202c) and configured as a gate dielectric.

5. The GaN HEMT (200) as claimed in claim 1, wherein the graded p-type passivation structure is deposited over a passivation layer composed of any or a combination of: Aluminium Oxide (Al₂O₃), Silicon Nitride (SiNx) and Silicon Dioxide (SiO₂).

6. The GaN HEMT (200) as claimed in claim 1, wherein the junctions at the interface of the plurality of layers (214a, 214b, 214c) form a plurality of depletion regions to suppress the peaking of the channel electric field at an edge of at least one of: the gate electrode (202c), a field plate, and the drain electrode (202b).

7. The GaN HEMT (200) as claimed in claim 1, wherein the dynamic ON resistance (ΔRON) is frequency-independent across switching frequencies under switching circuit conditions.

8. The GaN HEMT (200) as claimed in claim 1, wherein the barrier layer (206) composed of at least one of: Aluminium Nitride (AlN), graded Aluminium Gallium Nitride (AlGaN), or back barrier structures is deposited over a GaN channel layer (208), wherein the GaN channel layer (208) is deposited over a buffer layer (210) selected from any or a combination of: carbon-doped buffer layer, iron-doped buffer layer, or carbon-iron co-doped buffer layers, and wherein the buffer layer (210) is deposited over a substrate (212) composed of a material selected from Silicon (Si), Silicon Carbide (SiC), sapphire, Diamond, GaN, or Qromis substrate technology (QST).
9. A method (700) of fabricating a semiconductor device (200), the method (700) comprising:
forming (702) ohmic contacts on a source electrode (202a) and a drain electrode (202b) by depositing an ohmic metal stack structure followed by an annealing process;
performing (704) a mesa etching process to define active regions and electrically isolate individual devices on a semiconductor substrate (212);
depositing (706) a gate metal comprising one or more schottky metal stacks over a gate electrode (202c);
depositing (708-1) a first passivation layer (214a) comprising a low-doped p-type semiconductor material using a deposition technique;
depositing (708-2) a second passivation layer (214b) comprising a p-type semiconductor material using the deposition technique, wherein the second passivation layer (214b) is formed of a doping concentration different from the first passivation layer (214a);
depositing (708-3) a third passivation layer (214c) comprising a p-type semiconductor material using the deposition technique to improve electric field distribution between the gate electrode (202c) and the drain electrode (202b), wherein the third passivation layer (214c) is formed of a doping concentration different from the first and second passivation layers (214a, 214b);
performing a low temperature annealing process for enhancement of interfaces formed between the first, second, and third passivation layers (214a, 214b, 214c);
etching one or more openings through the first, second, and third passivation layers (214a, 214b, 214c) to establish electrical contact with underlying metal contacts; and
thickening the source and drain electrodes (202a, 202b) by depositing a conductive metal and optionally forming one or more field plates, wherein the one or more field plates are any or a combination of drain-connected field plates, source-connected field plates, or gate-connected field plates.
10. The method (200) as claimed in claim 9, wherein the ohmic metal stack structure comprises one or more metal layers selected from any or a combination of titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), nickel (Ni), platinum (Pt), palladium (Pd), molybdenum (Mo), chromium (Cr), and gold (Au), and wherein the one or more schottky metal stacks are selected from any or a combination of nickel (Ni), platinum (Pt), palladium (Pd), and gold (Au).