Description:FIELD OF THE INVENTION
The present invention belongs to the domain of power electronics and semiconductor device modeling, with a specific focus on scaled power devices in high-power VLSI circuits. It introduces a circuit-compatible, real-time self-heating characterization model for power transistors, enabling accurate thermal analysis, power loss prediction, and thermal optimization. This invention is applicable to various high-power electronic systems, including electric vehicles (EVs), industrial motor drives, power inverters, renewable energy systems, and aerospace electronics, ensuring enhanced efficiency and reliability in VLSI power integration.
BACKGROUND OF THE INVENTION
The present invention introduces an environment-adaptive self-heating model for scaled power devices, addressing the critical impact of thermal effects on power dissipation in high-power VLSI (Very Large-Scale Integration) electronic circuits. The proposed model integrates a compact electro-thermal network that accurately characterizes self-heating behaviour by incorporating external environmental conditions, thereby improving power dissipation analysis and thermal reliability in VLSI power electronic systems.
By implementing a dynamic thermal resistance-capacitance (Rth-Cth) model, the invention enables real-time computation of thermal resistance and capacitance, allowing precise thermal behaviour prediction during circuit operation. The proposed system offers a computationally efficient, scalable, and adaptable approach for modeling self-heating effects, significantly enhancing thermal management, energy efficiency, and reliability of high-power VLSI circuits.
The increasing miniaturization and integration of power devices in VLSI systems have significantly intensified in-package self-heating effects, critically impacting thermal management, power dissipation, and device reliability. However, existing thermal models used in power semiconductor simulations suffer from the following limitations:
a. Inaccurate Self-Heating Estimations – Conventional models fail to dynamically capture real-time self-heating effects, leading to incorrect power loss estimations.
b. Limited Electro-Thermal Integration – Existing thermal models do not effectively account for external thermal resistances, such as junction-to-case and case-to-ambient pathways, which significantly affect power dissipation.
c. High Computational Complexity – Traditional electro-thermal simulations are computationally expensive as all of these try to capture with a physical model, making them costly solutions for real-time analysis in large-scale VLSI circuits.
d. Device Reliability Issues – Excessive self-heating contributes to thermal degradation, reduced switching efficiency, and shortened device lifespan in high-power VLSI circuits. To overcome these limitations, the present invention introduces an environment-adaptive circuit-compatible self-heating model that enables real-time thermal characterization, ensuring precise power loss calculations and improved reliability for scaled power devices in high-power VLSI electronic circuits.
OBJECTIVES OF THE INVENTION
The primary objectives of this invention are:
I. To develop an advanced circuit-compatible self-heating model for scaled power devices, enabling accurate real-time power loss estimations.
II. To incorporate an electro-thermal network that models thermal resistance (Rth) and thermal capacitance (Cth) for self-heating characterization.
III. To integrate external thermal pathways, such as junction-to-ambient and heatsink thermal resistance modeling, for realistic power dissipation analysis.
IV. To provide a computationally efficient simulation framework suitable for real-time circuit analysis and electronic design automation (EDA) tools.
V. To enhance device reliability and thermal performance by optimizing heat dissipation mechanisms in high-power VLSI circuits.
STATEMENT OF INVENTION
The present invention introduces a self-heating model for scaled power devices, integrating a compact resistor-capacitor (RC) thermal network to characterize thermal behaviour and power loss effects in high-power circuits. The invention specifically:
A. Models self-heating effects arising from high-frequency switching operations in VLSI power transistors.
B. Defines thermal resistance (Rth) and capacitance (Cth) parameters, enabling real-time thermal characterization.
C. Integrates external heat dissipation pathways, improving thermal stress analysis and power device reliability.
D. Provides a computationally efficient model, suitable for SPICE, MATLAB, and circuit simulation tools. This invention is applicable to power electronic circuits, including electric vehicle (EV) inverters, renewable energy power grids, aerospace systems, and industrial motor drives.
SUMMARY OF THE INVENTION
This summary is provided to introduce a selection of concepts, in a simplified format, that are further described in the detailed description of the invention.
This summary is neither intended to identify key or essential inventive concepts of the invention and nor is it intended for determining the scope of the invention.
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings.
The invention presents a novel environment-adaptive self-heating model for scaled power devices, introducing:
i. A real-time electro-thermal network to simulate self-heating effects and power loss dynamics.
ii. A compact resistor-capacitor (RC) model integrating thermal resistance (Rth) and capacitance (Cth).
iii. A computationally efficient framework that can be used in high-frequency power circuit simulations.
iv. Enhanced thermal management and device reliability, making the invention suitable for large-scale industrial applications.

BRIEF DESCRIPTION OF THE DRAWINGS
The illustrated embodiments of the subject matter will be understood by reference to the drawings, wherein like parts are designated by like numerals throughout. The following description is intended only by way of example, and simply illustrates certain selected embodiments of devices, systems, and methods that are consistent with the subject matter as claimed herein, wherein:
Fig. 1: Thermal resistance network model (Rth-Cth) for power device self-heating analysis with Approach ∞
Fig. 2: Simulation setup with external thermal pathways, including junction-to-case and heatsink thermal resistance with Approach β.
The figures depict embodiments of the present subject matter for the purposes of illustration only. A person skilled in the art will easily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.
DETAILED DESCRIPTION OF THE INVENTION
The detailed description of various exemplary embodiments of the disclosure is described herein with reference to the accompanying drawings. It should be noted that the embodiments are described herein in such details as to clearly communicate the disclosure. However, the amount of details provided herein is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure as defined by the appended claims.
It is also to be understood that various arrangements may be devised that, although not explicitly described or shown herein, embody the principles of the present disclosure. Moreover, all statements herein reciting principles, aspects, and embodiments of the present disclosure, as well as specific examples, are intended to encompass equivalents thereof.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a",” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
In addition, the descriptions of "first", "second", “third”, and the like in the present invention are used for the purpose of description only, and are not to be construed as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" and "second" may include at least one of the features, either explicitly or implicitly.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The invention utilizes a self-heating model for scaled power devices, incorporating:
a) A compact electro-thermal network that models power device self-heating under dynamic conditions, enabling accurate real-time thermal characterization and optimization. The model accounts for self-heating effects arising from high-frequency switching and integrates external environmental conditions to refine power loss estimation.
b) Thermal resistance (Rth) and capacitance (Cth) components, allowing real-time computation of heat propagation pathways. The self-heating effect is analyzed using an electro-thermal network, where the junction-to-case thermal resistance (Rjunc) and the case-to-ambient resistance (Rc-a) are considered based on power device datasheets.
c) Integration with circuit simulation tools, enabling real-time power loss prediction and thermal optimization. Two modeling approaches have been considered: ‘Approach-α’ (Fig.1) includes external thermal networks, while ‘Approach-β’ (Fig.2) replaces them with an equivalent single thermal voltage, facilitating computational efficiency. The steady-state temperature of the heatsink remains nearly constant, significantly impacting heat dissipation characteristics. Simulation studies of the two approaches reveal nearly identical self-heating rise (ΔT) and switching power losses (Psw), confirming model validity.
This model is computationally efficient, making it suitable for EDA tools, real-time thermal management, and large-scale VLSI circuit simulations. It provides an opportunity to analyse power devices in high-power circuits with enhanced accuracy by incorporating external thermal effects and measured heatsink temperatures using infrared thermography. The invention significantly improves power dissipation modeling, optimizing thermal propagation and reducing device failure risks in VLSI power electronic systems.

, Claims:1. An environment-adaptive dynamic self-heating model for scaled power devices in high-power VLSI electronic circuits, comprising:
a compact electro-thermal network configured to model self-heating effects under dynamic operating conditions;
wherein said network incorporates thermal resistance and capacitance components for real-time computation of heat propagation pathways, and further integrates external environmental conditions to refine power loss estimation.
2. The model as claimed in claim 1, wherein the electro-thermal network includes junction-to-case thermal resistance (Rjunc) and case-to-ambient resistance (Rc-a), derived from device datasheets, for accurate modeling of thermal pathways in scaled power devices.
3. The model as claimed in claim 1, wherein said compact electro-thermal network is integrated with circuit simulation tools, enabling real-time prediction of switching power losses and thermal optimization during operation of high-power VLSI circuits.
4. The model as claimed in claim 1, wherein two distinct modeling approaches are provided:
Approach-α incorporating external thermal networks, and Approach-β replacing said networks with an equivalent single thermal voltage source, thereby achieving improved computational efficiency without loss of accuracy in thermal prediction.