Description:TECHNICAL FIELD
The present disclosure relates generally to the field of fabrication of semiconductor devices. Moreover, the present disclosure relates to a method for fabricating air bridge metal interconnects on a semiconductor device.
BACKGROUND
Recently, the semiconductor industry has witnessed increasing demand for high-frequency, high-power devices, particularly in the field of Radio Frequency (RF) applications, which has driven the requirement for reliable interconnect structures that minimize parasitic effects. One widely adopted structure is an air bridge structure, which provides crossover connections between electrodes or signal lines without relying on insulating dielectric layers. The air bridges are particularly beneficial in devices, such as Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs), where performance is highly sensitive to parasitic capacitance and signal interference. However, existing air bridge fabrication methods involve multiple complex processing steps, including repeated lithography, sacrificial layer deposition, seed layer patterning, and etching processes. The multiple processing steps not only increase manufacturing cost and complexity but also introduce risks of structural damage during subsequent processes, such as wafer thinning, dicing, and cleaning.
While conventional fabrication methods have enabled the integration of air bridges in various RF devices, they remain limited in several key aspects. For instance, commonly used etching processes to remove seed layers result in either over-etching or incomplete residue removal, compromising the structural and electrical reliability of the air bridge. The delicate and multi-step nature of the conventional processes also affects manufacturing yield, making them unsuitable for large-scale, high-throughput production.
Certain improvements have been proposed to simplify air bridge fabrication, such as dry etching alternatives and simplified masking techniques, but such solutions still face challenges in process integration, structural robustness, and compatibility with post-fabrication processes. The conventional methods also fall short in providing a streamlined, etch-free fabrication process that avoids mechanical instability and ensures strong anchoring of the air bridge structure. Thus, there exists a technical problem of how to develop a robust, simplified, etch-free air bridge fabrication method that can maintain structural integrity during post-processing steps, ensure compatibility with a variety of substrates, and eliminate the complexities and limitations associated with existing manufacturing approaches.
Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional air bridge fabrication methods.
SUMMARY
The present disclosure provides a method for fabricating an air bridge metal interconnect on a semiconductor device. The present disclosure provides a solution to the technical problem of how to develop a robust, simplified, and etch-free air bridge fabrication method that can maintain structural integrity during post-processing steps, ensure compatibility with a variety of substrates, and eliminate the complexities and limitations associated with existing manufacturing approaches. The present disclosure aims to provide a solution that overcomes the problems encountered in the prior art and provides a method of fabricating the air bridge and the integration of the air bridge with semiconductor devices. The disclosed fabrication method offers technical advancements and manufacturing benefits by enabling scalable, substrate-agnostic, and mechanically stable interconnect solutions for high-frequency semiconductor applications.
One or more objectives of the present disclosure are achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.
In one aspect, the present disclosure provides a method for fabricating an air bridge metal interconnect on a substrate of a semiconductor device. The method comprises forming a first resist layer on a substrate comprising at least two metal pads to be electrically interconnected. Further, the method comprises patterning the first resist layer to generate support regions between and adjacent to the at least two metal pads and subjecting the patterned first resist layer to a controlled thermal reflow operation to generate an arced support structure spanning between the at least two metal pads. Further, the method comprises depositing a continuous seed layer of conductive material over the reflowed first resist layer and exposed portions of the substrate, including at least two metal pads, and forming a second resist layer over the continuous seed layer. The method further comprises patterning the second resist layer to define a bridge span region connecting at least two metal pads and electroplating a metal layer onto exposed portions of the continuous seed layer within the defined bridge span region to form an air bridge structure. Furthermore, the method comprises removing both the first and second resist layers along with portions of the continuous seed layer not covered by the electroplated metal layer in a single lift-off step, thereby generating a free-standing air bridge metal interconnect electrically connecting at least two metal pads on the substrate without any dry or wet etching steps.
Advantageously, the disclosed method for fabricating the air bridge metal interconnect is configured to simplify the manufacturing process, enhance structural reliability, and improve compatibility with various semiconductor substrates. The formation of the arced support structure through thermal reflow of the patterned resist layer allows precise control over the bridge height and shape, contributing to mechanical stability during and after fabrication. Moreover, the use of a continuous conductive seed layer over both the resist layers and metal pads, followed by the application and patterning of the second resist layer. Furthermore, the electroplating of metal exclusively on exposed seed layer regions provides a cost-effective and selective deposition of the air bridge structure, while the final lift-off process removes both resist layers and excess seed material in a single step. Moreover, the disclosed fabrication method leverages a robust and simplified two-step lithographic process with electroplating and the single lift-off technique that avoids complex dry or wet etching of seed layers, making it compatible with various semiconductor substrates and metallization schemes. The overall method enables the fabrication of robust, free-standing air bridges that maintain structural integrity during post-processing operations, such as ultrasonication, grinding, and thermal cycling, thereby offering a highly efficient and scalable solution for next-generation RF and semiconductor device integration.
In another aspect, there is provided a semiconductor device comprising a substrate, a plurality of source pads disposed on the substrate and spaced apart from one another and an air bridge metal interconnect electrically connecting two or more of the plurality of source pads, where the air bridge metal interconnect is free-standing between the two or more of the plurality of source pads and spaced apart from the substrate to define an air gap beneath the air bridge metal interconnect.
The disclosed semiconductor device manifests several advantages required for advanced microelectronic and RF device performance. The unique structure, where the air bridge is suspended above the substrate with a defined air gap, significantly reduces parasitic capacitance and enhances high-frequency signal integrity. The air bridge is fabricated using a streamlined two-step optical lithography process and a single electroplating step, eliminating the requirement for complex seed layer etching. This not only reduces fabrication cost and time but also enhances compatibility with various semiconductor materials, including GaN and SiC.
It is to be appreciated that all the implementation forms can be combined. All steps that are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities, are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.
Additional aspects, advantages, features, and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations are construed in conjunction with the appended claims that follow.
BRIEF DESCRIPTION OF THE DRAWINGS
The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those skilled in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.
Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:
FIGs. 1A and 1B collectively, is a flowchart illustrating a method of fabricating an air bridge metal interconnect on a substrate of a semiconductor device, in accordance with an embodiment of the present disclosure;
FIG. 2 illustrates a fabrication process of a free-standing air bridge metal interconnect, in accordance with an embodiment of the present disclosure;
FIGs. 3A and 3B are diagrams illustrating Scanning Electron Microscope (SEM) micrographs of a resist profile used in the fabrication of air bridge metal interconnects, in accordance with an embodiment of the present disclosure;
FIG. 4A diagram illustrating an effect of a without thermal reflow operation on a resist profile, in accordance with an embodiment of the present disclosure;
FIG. 4B showing the effect with thermal reflow operation on a resist profile, in accordance with an embodiment of the present disclosure;
FIGs. 5A and 5B are diagrams illustrating SEM micrographs of air bridge metal interconnects, in accordance with an embodiment of the present disclosure;
FIG. 6 is a diagram illustrating a fabricated gold air bridge interconnect after the substrate grinding process, in accordance with an embodiment of the present disclosure;
FIGs. 7A and 7B are diagrams illustrating SEM micrographs of milling an air bridge metal interconnect using a Focused Ion Beam (FIB), in accordance with an embodiment of the present disclosure; and
FIGs. 8A and 8B are diagrams illustrating a Gallium Nitride (GaN) High-Electron-Mobility Transistor (HEMT) device fabricated on a Silicon Carbide (SiC) substrate, in accordance with an embodiment of the present disclosure.
In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.
DETAILED DESCRIPTION OF EMBODIMENTS
The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.
FIGs. 1A and 1B collectively, is a flowchart illustrating a method of fabricating an air bridge metal interconnect on a substrate of a semiconductor device, in accordance with an embodiment of the present disclosure. With reference to FIGs. 1A and 1B, there is shown a method 100 for fabricating an air bridge metal interconnect on a semiconductor device. The method 100 includes steps 102 to 116.
There is provided the method 100 for fabricating an air bridge metal interconnect on the semiconductor device. The method 100 employs a streamlined fabrication approach using just two optical lithography steps and a single electroplating process, eliminating the requirement for complex seed layer etching. This not only simplifies manufacturing but also enhances yield and repeatability across various semiconductor platforms. The resulting air bridge structures exhibit excellent mechanical integrity, having withstood rigorous processes, such as ultrasonic cleaning and substrate grinding without structural degradation.
At step 102, the method 100 includes forming a first resist layer on a substrate comprising at least two metal pads to be electrically interconnected. The substrate may be a semiconductor wafer, such as silicon or silicon carbide, and the metal pads are typically pre-patterned contact points that require electrical connection through an air bridge. The resist material used at this stage is a thick, light-sensitive polymer that is uniformly applied over the surface of the substrate using spin-coating techniques to ensure consistent layer thickness. Moreover, the selected resist exhibits properties suitable for thermal reflow, enabling it later to form a curved support structure for the air bridge. Applying the first resist layer ensures that the regions around and between the two metal pads are properly coated, providing a base for defining the vertical height of the air bridge structure. Additionally, the step 102 is configured to ensure precise alignment with the underlying metal pads to facilitate accurate interconnection in later steps. In an implementation, the thickness of the first resist layer is optimized to achieve the height of the air bridge approximately 6 micrometres (µm) after the reflow process, contributing to low parasitic capacitance and improved high-frequency performance. Furthermore, the resist material is selected to maintain structural integrity during subsequent thermal and chemical processing, ensuring compatibility with standard semiconductor fabrication workflows and substrate materials. In an implementation scenario, the first resist layer can be made of a photoresist material, including positive and negative photoresist material, suitable for defining the arced support structure through optical lithography and thermal reflow. In another implementation scenario, the first resist layer can be formed using an electron-beam (e-beam) resist material. In other implementation scenarios, the first resist layer can be formed using either Deep Ultraviolet (DUV) resist material, or nanoimprint resist material, or chemically amplified resist material, and the like, offering compatibility with different lithography techniques and enabling process flexibility across various device integration platforms.
In accordance with an embodiment, the method 100 comprises cleaning the substrate comprising at least two metal pads using a standard cleaning solvent selected from a group of: acetone, isopropyl alcohol, or deionized water. The cleaning step is performed prior to the spin-coating of the first resist layer to eliminate surface contaminants, such as organic residues, particulate matter, and ionic impurities that may be present on the semiconductor substrate or metal pads. The cleaning of the substrate may be carried out by sequentially immersing or rinsing the substrate in acetone to dissolve organic contaminants, followed by IsoPropyl Alcohol (IPA) to remove remaining solvent residues and moisture, and finally rinsing with De-Ionized (DI) water to ensure ionic and particulate cleanliness. The use of solvents (such as acetone, isopropyl alcohol, or deionized water) ensures that the surface of the substrate is chemically and physically prepared to promote uniform adhesion and coverage of the first resist layer during spin coating. By removing contaminants before any photolithographic or deposition step, the method 100 reduces the risk of lift-off failure or seed layer cracking, leading to the formation of a structurally reliable and electrically robust air bridge with clean interfaces and high process yield.
In accordance with an embodiment, the substrate is made of a semiconductor material selected from a group comprising: Silicon (Si), Silicon Carbide (SiC), Sapphire (Al2O3), Gallium Nitride on Silicon Carbide (GaN-on-SiC), Gallium Nitride on Silicon (GaN-on-Si), free-standing Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Oxide (Ga2O3), etc. The use of semiconductor materials enables the wide applicability of the fabrication method across various device platforms, including high-frequency, high-power, and optoelectronic applications. The selection of the substrate material directly influences thermal conductivity, chemical resistance, and device performance characteristics. For instance, high-resistivity (HR) Silicon (Si) and SiC substrates support superior RF performance, while GaN-on-SiC substrates are particularly suited for microwave power transistors due to their high thermal conductivity and breakdown voltage. The compatibility with a broad range of substrate materials eliminates the requirement to customize the process for different semiconductor types, thereby simplifying integration across diverse device architectures and reducing fabrication complexity while ensuring consistent mechanical stability and electrical performance of the air bridge.
At step 104, the method 100 includes patterning the first resist layer to generate support regions between and adjacent to the at least two metal pads. The step 104 involves using photolithography, a process in which UltraViolet (UV) light is shined to expose specific areas of the resist-coated substrate. The exposed areas of the resist become chemically altered, allowing them to be selectively removed during a development step, while the unexposed regions remain intact. As a result, the first resist layer is selectively shaped to form structural posts or arches between and beside the at least two metal pads. The patterned regions serve as the mechanical foundation or support columns for the air bridge span that will be built in later steps. Moreover, the patterning step defines the footprint and spacing of the support structures, which in turn control the positioning, width, and height of the final air bridge. Thus, step 104 is performed for creating a well-defined, resist-based framework that guides the formation of a free-standing, elevated air bridge interconnect in subsequent fabrication steps.
At step 106, the method 100 includes subjecting the patterned first resist layer to a controlled thermal reflow operation to generate an arced support structure spanning between the at least two metal pads. Step 106 involves heating the previously patterned first resist layer to a specific temperature, typically below its decomposition point but above its softening point, so that the resist material partially melts and reshapes due to surface tension. During the reflow process, the flat or angular edges of the patterned first resist layer gradually smooth out and form a curved or lens-shaped profile, resulting in a gentle arch or dome-like bridge between and around the support regions. The curved structure defines the vertical clearance and shape of the eventual air bridge, effectively acting as a temporary mould that supports the bridge span to be formed in later steps. Moreover, the reflowed resist layer serves several key purposes: it provides a smooth contour for metal deposition, reduces the likelihood of cracks in subsequent layers, and ensures that the height of the air bridge is consistent and mechanically stable. In an implementation, the thermal reflow is performed at a carefully controlled temperature (e.g., around 150°C for 10 minutes), which promotes strong cross-linking within the resist, enhancing its thermal and chemical resistance during later fabrication steps. Additionally, the arced geometry resulting from the controlled thermal reflow contributes to the mechanical integrity of the final air bridge by reducing sharp corners and stress points. Thus, the step 106 plays a significant role in shaping the support structure that determines the height, curvature, and overall robustness of the air bridge interconnect in the semiconductor device.
At step 108, method 100 includes depositing a continuous seed layer of conductive material over the reflowed first resist layer and exposed portions of the substrate, including at least two metal pads. Step 108 involves applying a very thin, uniform metal film, commonly composed of materials such as nickel and gold (Ni/Au), using a Physical Vapor Deposition (PVD) technique, such as e-beam evaporation or sputtering. The continuous seed layer serves as a conductive base layer required for the upcoming electroplating process. The continuous seed layer provides the electrical continuity required for metal ions to deposit and grow only in specific regions during electroplating. Because the continuous seed layer is deposited across the entire surface, it covers both the curved (reflowed) resist areas and the exposed substrate areas, including the at least two metal pads. Importantly, the continuous seed layer is conformally deposited, meaning it follows the contour of the thermal reflowed resist without altering its shape. By covering the top, sides, and exposed pad areas, the seed layer creates a conductive pathway that enables precise and uniform metal growth in the subsequent electroplating step. In an implementation, the thickness of the continuous seed layer is kept very thin (typically in the range of 30 nm to 60 nm). This allows for a lift-off-based removal later in the process, avoiding the use of wet or dry etching techniques that can damage the air bridge or the semiconductor device. Thus, step 108 is for preparing the surface for selective metal deposition, ensuring electrical contact with the metal pads, and enabling a chemically simplified and mechanically gentle fabrication process for forming the air bridge interconnect.
At step 110, the method 100 includes forming a second resist layer over the continuous seed layer. Step 110 involves applying a new layer of resist material, using the spin-coating technique to ensure a uniform and even coating over the entire surface, including the curved contours of the reflowed support structure. The second resist layer is formed to enable the definition of the bridge span region, which is the part of the air bridge that will directly connect the two metal pads. Unlike the first resist layer, which shapes the support structure and defines the bridge’s height, the second resist layer acts as a patterning mask for controlling where the electroplated metal will be selectively deposited on the continuous seed layer. In an implementation, the thickness and viscosity of the second resist layer are carefully selected to ensure complete coverage over the curved surfaces created during the reflow process, while maintaining the required resolution for accurate patterning in the next step. The second resist layer must also adhere well to the underlying continuous seed layer without causing delamination or voids, which could disrupt the subsequent electroplating process. By forming the second resist layer, the method 100 creates a temporary structure that precisely controls where the conductive material will grow to form the air bridge, while protecting areas that should remain free of plating.
Similar to the first resist layer, the second resist layer can be made of either the photoresist material or e-beam resist material or DUV resist material, or nanoimprint resist material, or chemically amplified resist material, and the like, offering compatibility with different lithography techniques and enabling process flexibility across various device integration platforms.
At step 112, the method 100 includes patterning the second resist layer to define a bridge span region connecting the at least two metal pads. Step 112 involves a photolithography process, where UV light is projected onto the second resist layer to expose specific regions that correspond to the desired shape and position of the air bridge spanning the actual metal interconnect that will be formed between at least two metal pads. After exposure, the substrate is subjected to a development process, which removes the exposed areas of the second resist layer, thereby creating an open channel or trench directly above the seed layer in the shape of the intended bridge. This exposed continuous seed layer within the patterned region serves as the base for electroplating in the next step, while the unexposed resist remains intact to act as a protective mask, preventing metal deposition outside the designated area. The precise patterning of the second resist layer is for defining the width, length, and placement of the bridge span. The patterning ensures that the air bridge will be accurately aligned with the underlying metal pads and properly suspended above the substrate without unwanted electrical shorts or misalignments. In an implementation, the dimensions of the patterned span region are optimized to provide both mechanical stability and electrical performance, especially for high-frequency applications where parasitic effects must be minimized. Thus, the step 112 provides the formation of a well-controlled cavity for electroplating the bridge structure, ensuring that the air bridge interconnect has the required shape, position, and electrical connectivity between the target metal pads.
Referring to FIG. 1B, at step 114, the method 100 includes electroplating a metal layer onto exposed portions of the continuous seed layer within the defined bridge span region to form an air bridge structure. The step 114 involves using the electroplating process, which is an electrochemical technique for building up a layer of metal on a conductive surface. During electroplating, the substrate is immersed in a metal plating solution (such as a gold sulphite bath), and an electric current is applied. The exposed continuous seed layer acts as the cathode, attracting metal ions from the solution, which are deposited as a solid metal layer precisely within the patterned span region. The second resist layer protects the surrounding areas, so metal only accumulates where the continuous seed layer is uncovered. As the metal builds up, it gradually forms the physical structure of the air bridge, extending from one metal pad to the other while remaining suspended above the reflowed first resist layer. The thickness of the electroplated metal, often around 4 µm, is carefully controlled by adjusting the plating time, temperature, and current density to ensure the bridge is strong enough to maintain mechanical integrity and provide low-resistance electrical conduction. The step 114 is particularly advantageous because electroplating is both cost-effective and selective, eliminating the requirement for complicated etching or lift-off procedures during metal deposition. It also allows for the formation of thicker, more durable bridge structures than would be practical with other deposition methods, such as evaporation or sputtering.
At step 116, the method 100 includes removing both the first and second resist layers along with portions of the continuous seed layer not covered by the electroplated metal layer in a single lift-off step, thereby generating a free-standing air bridge metal interconnect electrically connecting the at least two metal pads on the substrate. The step 116 involves the chemical lift-off process, typically using a solvent that dissolves the resist layers. As both the first (support) and second (span-defining) resist layers dissolve, they detach from the substrate and carry away with them the overlying or adjacent unwanted portions of the seed metal layer that are covered by the resists. The lift-off process is highly selective and clean because the electroplated metal only adheres to the continuous seed layer in the exposed span region. The continuous seed layer on top of the resist, which did not receive electroplated metal, lifts off effortlessly with the resist material, leaving behind only the intended, robust air bridge securely anchored to at least two metal pads. Step 116 provides the fabrication of a mechanically resilient and electrically functional air bridge that is completely suspended above the substrate, with no underlying dielectric material, making it ideal for high-frequency and other intended applications.
In accordance with an embodiment, the at least two metal pads, the continuous seed layer and the electroplated metal layer, each comprises one or more metals selected from a group comprising: Gold (Au), Nickel (Ni), Titanium (Ti), Chromium (Cr), Aluminum (Al), and Copper (Cu). The use of this specific group of metals enhances the electrical, chemical, and mechanical performance of the fabricated air bridge by leveraging their material characteristics, such as Gold’s superior conductivity and corrosion resistance, Nickel’s good adhesion and diffusion barrier properties, and Titanium’s strong adhesion to oxide surfaces. The group of metals is deposited using standard techniques like sputtering or e-beam evaporation for the seed layer and electroplating for the bridge formation, ensuring compatibility with the fabrication sequence involving the patterned resist layers (i.e., the first resist layer and the second resist layer). Because the metals exhibit excellent adhesion to various semiconductor substrates and maintain structural integrity during high-temperature processes, they enable clean lift-off and robust bridge formation. The ability to flexibly choose from a defined set of reliable conductive materials allows the air bridge process to be tailored to the electrical and thermal requirements of different device architectures, while also maintaining uniformity and consistency across fabrication batches, thereby improving overall yield and performance stability of the resulting interconnects.
In accordance with an embodiment, each of the first resist layer and the second resist layer comprise a resist material independently selected from one or more of: a photoresist material, an electron-beam resist material, a deep ultra-violet resist material, or a chemically amplified resist material and where each resist material is of a thickness in a range of 1 µm to 10 µm. The first resist layer and the second resist layer, both of which comprise the resist material, such as AZ4562. The thickness of each resist layer in the range of, for example, 1 µm to 10 µm is selected to achieve two outcomes: firstly, it allows the first resist layer, after reflow, to define a sufficiently elevated arched support structure, typically around 6 µm height, which determines the vertical clearance of the air bridge from the substrate; secondly, it enables the second resist layer to accommodate electroplated metal growth with a thickness of approximately 1 µm to 10 µm without risk of overflow, deformation, or surface stress. Because the resist profile can accommodate taller electroplated features, the resulting bridge structure demonstrates improved current-carrying capacity and mechanical durability. Additionally, using the resist material in both resist layers promotes uniform exposure and development characteristics, streamlining the fabrication process while ensuring precise dimensional control and structural consistency in the final air bridge interconnect.
In accordance with an embodiment, the single lift-off step comprises immersing the substrate in an organic solvent solution heated to a temperature between 60°C and 75°C for a specified duration to remove the first and second resist layers and covered portions of the continuous seed layer present adjacent to the at least two metal pads, without employing any dry etching or wet chemical etching operations. The removal process is based purely on solvent dissolution and thermal activation, avoiding the use of dry etching (plasma-based) or wet chemical etching (acidic or basic solutions), both of which can damage the electroplated metal, degrade substrate materials, or leave behind etching residues. The effectiveness of this lift-off method results from the controlled softening and breakdown of the resist layers under 65 – 70°C temperature, which allows the overlying seed metal to detach cleanly as the resist dissolves. By eliminating aggressive etching steps, the method 100 preserves the surface quality and geometry of the electroplated air bridge, maintaining smooth sidewalls and preventing pitting or roughness caused by chemical attack. This solvent-based lift-off also ensures minimal contamination and high selectivity, contributing to the structural integrity and electrical reliability of the air bridge while enabling a cleaner, safer, and more substrate-compatible process workflow across different semiconductor platforms.
In accordance with an embodiment, the free-standing air bridge metal interconnect is configured to remain structurally intact when subjected to at least one of: an ultrasonic cleaning operation at a specified frequency and time duration, a substrate thinning operation comprising reducing a thickness of the substrate, and a Focused Ion Beam (FIB) milling operation comprising removing a portion of the free-standing air bridge structure. The ultrasonic cleaning operation, performed at a frequency of approximately 40 kHz for a duration exceeding 1 hour in deionized water, (ii) the substrate thinning operation involving the backside grinding of the substrate from an initial thickness of about 500 µm to approximately 100 µm without the use of a carrier wafer, and (iii) the FIB milling operation, wherein a section of the electroplated air bridge is either bisected or a hole is milled at its center. The mechanical robustness of the air bridge under these stress conditions results from the optimized process steps, including the reflow-formed arched profile of the first resist layer, the precise electroplating of a 4 µm-thick metal span over the continuous seed layer, and the clean lift-off achieved at step 112 of the method 100. These parameters ensure that the air bridge manifests not only sufficient height clearance and adhesion to the at least two metal pads, but also structural integrity under physical, thermal, and vibrational stress.
In accordance with an embodiment, the free-standing air bridge metal interconnect has a structural configuration selected from a group of: a T-shaped structure, a star-shaped structure, and a multi-layer bridge structure. The ability to fabricate the T-shaped configuration, as implemented in the integration of air bridges with 8 × 125 μm GaN HEMTs, results from the precise patterning of the second resist layer and the conformal electroplating process over the reflow-shaped support resist. In the T-structure, the foot of the "T" connects to a central source pad, while the head spans laterally to connect the at least two metal ground pads of a coplanar waveguide (CPW), thereby allowing symmetrical current distribution and reducing series resistance in multi-finger transistor layouts. The T-shaped geometry proves especially useful in layouts with an even number of gate fingers, where traditional linear bridges would leave middle source pads unconnected. The star-shaped and multi-layer bridge configurations are similarly enabled by the seed layer and dual-lithography process, which allows vertically stacked or radially distributed bridge elements to be fabricated in a single plating step. The consistency in layer thickness and the mechanical resilience achieved through reflow and electroplating allow for the formation of such complex geometries without compromising bridge integrity or lift-off performance during the step 112 of method 100. By facilitating the advanced configurations, Method 100 supports more flexible circuit designs, effective space utilization, and uniform current spreading, which are vital for high-performance RF and microwave device applications.
The steps 102 to 116 are only illustrative, and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.
FIG. 2 illustrates a fabrication process of a free-standing air bridge, in accordance with an embodiment of the present disclosure. FIG. 2 is described in conjunction with elements from FIGs. 1A and 1B. With reference to FIG. 2, there is shown a fabrication process 200 of the free-standing air bridge. The fabrication process 200 illustrates the formation of an air bridge metal interconnect 218 on a substrate 202 made of, for example, Silicon (Si) material having size, for example, 1cm × 1cm. The fabrication process 200 includes steps 220 to 234.
The substrate 202 serves as a foundational platform on which various semiconductor device structures, such as interconnects, transistors, and circuit elements, are fabricated. The substrate 202 is typically a high-resistivity (HR) silicon wafer, chosen for its excellent electrical insulation properties and compatibility with RF and microwave device applications. The substrate 202 supports the deposition of at least two metal pads 204, the formation of resist layers, and subsequent fabrication steps, while also providing mechanical stability throughout the fabrication process 200.
At step 220, the fabrication process 200 begins with thorough cleaning of the substrate 202 using standard solvents, such as acetone, IPA, and DI water to remove organic and particulate contaminants. Following this, the at least two metal pads 204, for example, Ni/Au (30/200nm) metal pads are deposited on the substrate 202 via either e-beam evaporation or sputtering, forming the contact points to be interconnected by the air bridge. The at least two metal pads 204 are patterned using standard lithography.
At step 222, a first resist layer 206 is formed on the substrate 202 comprising the at least two metal pads 204. For example, a thick layer of AZ4562 resist material is spin-coated over the substrate 202 to achieve a thickness of approximately 8 µm.
At step 224, the first resist layer 206 is patterned using Mask Writer µPG501 with a dose of 250 milliseconds (ms) and a defocus value of –4 to define regions where the bridge supports are to be formed. The patterned first resist layer is developed using MIF 726A for about 2 minutes, followed by a descum process at 48W RF power with an oxygen flow rate of 24-27 standard cubic centimetres per minute (sccm) for about 6-8 minutes in order to remove residual resist. Thereafter, a controlled thermal reflow of the patterned first resist layer is performed at for example, 150°C for about 10 minutes to achieve intense cross-linking in the patterned first resist layer and reducing its sensitivity to illumination. By virtue of developing and reflowing, an arced support structure 208 (e.g., a curved or lens-shaped structure) spanning the at least two metal pads 204 is formed. The arced support structure 208 has a thickness of approximately 6 µm. Moreover, the arced support structure 208 serves as a temporary support structure and defines an air gap height between the air bridge metal interconnect and the substrate 202.
At step 226, a thin continuous seed layer 210 of conductive material, for example, Ni/Au (of thickness 30 nm / 30 nm) is deposited via e-beam evaporation across the reflowed resist and exposed at least two metal pad regions, serving as a conductive base for electroplating.
At step 228, a second resist layer 212 of AZ4562 resist (~8 µm thickness) is spin-coated over the thin continuous seed layer 210, using the same lithography setup (µPG501 with the specified dose and defocus settings).
At step 230, the second resist layer 212 is patterned to define a bridge span region 214 where the metal bridge is to be formed. The second resist layer 212 is developed with MIF 726A, and descummed using oxygen plasma, under the same conditions as the first resist layer 206 is coated.
At step 232, a metal layer 216 is electroplated onto exposed portions of the thin continuous seed layer 210 within the defined bridge span region to form an air bridge structure. For electroplating the metal layer 216, the sample is immersed in TSG 250 gold sulphite plating solution at 60°C, and a current density of 4 mA/cm² is applied for 30 minutes. This step results in the electroplating of a gold bridge with a thickness of ~4 µm, precisely in the exposed trench defined by the second resist layer. The electroplating ensures that metal deposits only on the exposed seed layer, avoiding accumulation on resist sidewalls, which makes the lift-off clean and defect-free.
At step 234, following the electroplating, the entire structure undergoes a single lift-off process by immersion in MLO-07 solution heated to 65–70°C for about 5 minutes. The single lift-off process removes both the first resist layer 206 and the second resist layer 212 along with the thin continuous seed layer 210 covering them and leaving behind the electroplated metal bridge suspended across the at least two metal pads 204. Consequently, the air bridge metal interconnect 218 with a well-defined air gap and suspended above the substrate 202 is formed which is configured to electrically connect the at least two metal pads 204. The air bridge metal interconnect 218 maintains a defined air gap and exhibits high structural integrity, capable of withstanding harsh post-processing conditions, such as ultrasonic cleaning, substrate thinning, and focused ion beam (FIB) milling.
FIGs. 3A and 3B are diagrams illustrating Scanning Electron Microscope (SEM) micrographs of a resist profile used in the fabrication of air bridge metal interconnects, in accordance with an embodiment of the present disclosure. FIGs. 3A and 3B are described in conjunction with elements from FIGs. 1A-1B and 2. With reference to FIG. 3A, there is shown a diagram 300A illustrating a first SEM micrograph 302 of the resist profile before subjecting the patterned first resist layer to the controlled thermal reflow operation. Similarly, with reference to FIG. 3B, there is shown a diagram 300B illustrating a second SEM micrograph 304 of the resist profile after subjecting the patterned first resist layer to the controlled thermal reflow operation.
Typically, the SEM is a technique in which a focused beam of electrons is used to scan the surface of a sample and generate high-resolution images. The secondary electrons emitted from the sample are detected, and the resulting signal is used to create a detailed, three-dimensional image of the sample's surface topography.
In the FIG. 3A, the resist profile is shown immediately after photolithographic patterning and development, but before performing the controlled thermal reflow operation. The measured height of the resist structure is approximately 7.86 µm, which is consistent with the spin-coated thickness of the first resist layer 206 (i.e., AZ4562). The edges of the first resist layer 206 appear steep and angular, typical of unmodified positive resist profiles after standard development. The vertical structure may be configured to serve later as the support mould for the air bridge metal interconnect, but without reflow, the resist structure retains sharp corners, prone to seed layer cracking and high sensitivity to subsequent illumination or process stress
Referring to FIG. 3B, the resist material after being subjected to the controlled thermal reflow operation at 150°C for about 10 minutes. The reflow process causes the resist structure to soften and reconfigure under surface tension, resulting in a smooth, curved, and lens-like profile. The resist height decreases from 7.86 µm to approximately 6.23 µm, indicating a collapse and redistribution of the material into a more arched geometry. This shape is highly desirable for the air bridge fabrication process, as it enables the formation of a well-defined air gap and contributes to the structural stability of the air bridge metal interconnect during electroplating and the lift-off process.
The comparison between FIGs. 3A and 3B highlight the role of the controlled thermal reflow operation in modifying the mechanical and structural properties of the support resist material. The first SEM micrograph 302 of the resist profile before the controlled thermal reflow operation, the resist is prone to cracking or stress-related deformation during seed layer deposition or electroplating. And, the second SEM micrograph 304 of the resist profile after the controlled thermal reflow operation, the curved geometry not only improves adhesion and thermal stability but also defines the height and contour of the suspended air bridge with greater precision and mechanical integrity.
FIG. 4A is a diagram illustrating an effect of a without thermal reflow operation on a resist profile, in accordance with an embodiment of the present disclosure. FIG. 4B is a diagram illustrating an effect of a with thermal reflow operation on a resist profile, in accordance with an embodiment of the present disclosure. FIGs. 4A and 4B are described in conjunction with elements from FIGs. 1A-1B, 2 and 3A-3B. With reference to FIG. 4A, a diagram 400A illustrating the continuous seed layer with cracks 402 is shown without applying the controlled thermal reflow operation. With reference to FIG. 4B, there is shown a diagram, 400B, illustrating the continuous seed layer without cracks 404 after applying the controlled thermal reflow operation.
Referring to FIG. 4A, the patterned first resist layer has not undergone thermal reflow before the deposition of the Ni/Au seed layer. As a result, numerous cracks and stress lines are visible in the metal film, especially at the edges and junctions of the patterned structures. These cracks arise due to solvent outgassing and thermal mismatch stress during the continuous seed layer deposition, since the un-reflowed resist retains residual solvents and exhibits poor dimensional stability. The presence of sharp resist profiles further contributes to mechanical stress concentration, causing fracturing of the thin continuous seed layer. Such cracking leads to poor adhesion, unreliable electroplating, and potential discontinuities in the final air bridge metal interconnect, which significantly reduces semiconductor device yield and performance.
Referring to FIG. 4B, the patterned first resist layer is subjected to the controlled thermal reflow operation at 150°C for about 10 minutes prior to the seed layer deposition. The result is a smooth, stable surface with no visible cracks or mechanical defects in the continuous seed layer. The reflow process removes residual solvents, promotes cross-linking in the resist structure, and results in a curved profile that supports the deposition of conformal metal layers. As a result, the continuous seed layer remains uniform and intact, ensuring reliable electroplating and high-quality formation of the air bridge metal interconnect.
Moreover, implementing the controlled thermal reflow operation and avoiding seed layer etching significantly improves the structural and electrical quality of fabricated air bridges. When seed layer etching is used, the electroplated gold (i.e., the electroplated metal), being of lower density and more porous compared to sputtered or e-beam deposited gold (i.e., the seed layer), is attacked more aggressively by the etchant. This results in a visibly roughened surface, which can degrade electrical conductivity and weaken mechanical stability. Additionally, incomplete etching leaves behind residual metal fragments that pose a high risk of shorting adjacent features, severely compromising device reliability and yield.
In contrast, employing the controlled thermal reflow process prior to electroplating enhances the resist’s structural integrity by inducing cross-linking, stabilizing its shape, and preventing solvent-related defects. This reflowed resist forms a smoother and more uniform support structure, enabling the clean formation of air bridges through the lift-off process rather than etching. As a result, the air bridges exhibit superior surface quality, mechanical robustness, and electrical isolation, making the process both simpler and more reliable for high-performance semiconductor device fabrication.
FIGs. 5A and 5B are diagrams illustrating SEM micrographs of air bridge metal interconnects, in accordance with an embodiment of the present disclosure. FIGs. 5A and 5B are described in conjunction with elements from FIGs. 1A-1B, 2, 3A, 3B, 4A, and 4B. With reference to FIG. 5A, there is shown a diagram 500A illustrating a first SEM micrograph 502 of an array of air bridges. With reference to FIG. 5B, there is shown a diagram 500B illustrating a second SEM micrograph 504 of isolated air bridges.
Referring to FIG. 5A, the first SEM micrograph 502 of the array of air bridges having uniformly spaced structure is shown. Each air bridge spans between at least two metal contact pads, elevated above the substrate 202 surface, and exhibits a consistent arched geometry. The first SEM micrograph 502 demonstrates the process's repeatability and scalability, showcasing the ability to fabricate high-density air bridge networks with excellent geometric uniformity. The smooth curvature and uniform height of each air bridge result from the controlled thermal reflow of the first resist layer 206 and the precision in electroplating achieved using the defined span region in the second resist layer 212. Such arrayed configurations are required in RF and microwave integrated circuits, where multiple signal or source interconnections are required in parallel.
Referring to FIG. 5B, the second SEM micrograph 504 of the isolated air bridge is depicted, each separated by a considerable distance from its neighbours. This configuration showcases the process's versatility and resolution, confirming that air bridge formation is highly localized and not dependent on proximity effects. The ability to fabricate standalone bridges without affecting adjacent regions highlights the selectivity of the electroplating process, the effectiveness of the lift-off process, and the mechanical integrity of the resulting structure. This configuration is particularly useful in applications where only a few interconnects are required per die or where isolation between signal lines is significant. The consistent arch shape, defect-free structure, and clean suspension over the substrate 202 demonstrate the method's (i.e., the method 100) reliability, process control, and application flexibility for various semiconductor device architectures, including high-frequency GaN HEMTs and RF MEMS.
FIG. 6 is a diagram illustrating a fabricated gold air bridge interconnect after the substrate grinding process, in accordance with an embodiment of the present disclosure. FIG. 6 is described in conjunction with elements from FIGs. 1A-1B, 2, 3A, 3B, 4A, 4B, 5A, and 5B. With reference to FIG. 6, there is shown a diagram 600 illustrating a fabricated gold air bridge interconnect 602 and surface grinding marks 604 obtained when the substrate 202 is subjected to a grinding process.
The fabricated gold air bridge interconnect 602 may be referred to as a specifically engineered and electroplated metallic structure designed to provide an elevated electrical connection between two or more contact pads on the semiconductor device. The interconnect is made of Gold (Au) due to its excellent electrical conductivity, corrosion resistance, and compatibility with high-frequency applications.
The surface grinding marks 604 may be referred to as the visible linear or textured pattern present on the surface of the substrate 202 (e.g., a SiC substrate) following a mechanical thinning or back-side grinding process. The surface grinding marks 604 are generated during the substrate thinning operation, where the wafer is reduced from its original thickness (e.g., from 500 µm to approximately 100 µm) using abrasive grinding tools. The grinding is performed to reduce overall device thickness for improved thermal management, enhanced packaging compatibility, or wafer-level integration. The presence of surface grinding marks 604 confirms that material has been mechanically removed, and these marks serve as evidence of successful thinning.
Referring to FIG. 6, there are shown two GaN HEMT device structures with multiple air bridge interconnects. These bridges are formed using electroplated gold and are suspended over the device surface using the resist-reflow and the single lift-off-based method described in the FIGs. 1A-1B and 2. The bridges interconnect contact the at least two metal pads 204, such as source terminals, while maintaining a defined air gap above the substrate 202. At the center of the FIG. 6, the surface grinding marks 604 are visible, showing clear physical evidence of mechanical back-side grinding used to thin the SiC substrate. This aggressive post-fabrication process introduces substantial mechanical stress, often leading to deformation or delamination of delicate structures if they are not sufficiently robust. However, as observed in the FIG. 6, the air bridges remain structurally intact even after such substrate thinning process.
FIGs. 7A and 7B are diagrams illustrating SEM micrographs of milling an air bridge metal interconnect using a Focused Ion Beam (FIB), in accordance with an embodiment of the present disclosure. FIGs. 7A and 7B are described in conjunction with elements from FIGs. 1A-1B, 2, 3A, 3B, 4A, and 4B. With reference to FIG. 7A, there is shown a diagram 700A illustrating a first SEM micrograph of milling a hole 702 in the air bridge using FIB and FIG. 7B is a diagram 700B illustrating a second SEM micrograph of a bisection 704 of the air bridge using FIB.
Referring to FIG. 7A, the hole 702 has been precisely milled into the center of the free-standing gold air bridge using FIB processing. The FIB process involves directing a highly focused gallium ion beam at a specific location on the bridge to sputter away material, enabling nanoscale modification or inspection. Despite the invasive nature of the FIB process, the rest of the air bridge structure remains completely intact, suspended, and undeformed. The lack of cracking, delamination, or collapse around the milled hole confirms that the air bridge has sufficient thickness (~4 µm), ductility, and mechanical strength to endure high-energy ion bombardment without compromising its structural stability.
Referring to FIG. 7B, the air bridge has been fully bisected (cut through) using the FIB process. The air bridge is cleanly separated into two parts, demonstrating the precision and controllability of the FIB technique. Specifically, even after being cut, both segments of the air bridge maintain their suspended form, with no signs of downward collapse or warping. This indicates strong anchoring at both ends and uniform material integrity throughout the span of the air bridge.
FIGs. 8A and 8B are diagrams illustrating a GaN high-electron-mobility transistor (HEMT) device fabricated on a SiC substrate, in accordance with an embodiment of the present disclosure. FIGs. 8A and 8B are described in conjunction with elements from FIGs. 1A-1B, 2, 3A, 3B, 4A, 4B, 5A, 5B, 6, 7A, and 7B. With reference to FIG. 8A, there is shown a diagram 800A illustrating a SEM micrograph of the air bridge implemented on a semiconductor device 802 (e.g., a GaN HEMT device) fabricated on a SiC substrate, and FIG. 8B is a diagram 800B illustrating a side view of the air bridge implemented on the GaN HEMT device fabricated on the SiC substrate.
Referring to FIG. 8A, the SEM micrograph of the air bridge implemented on the GaN HEMT device with an 8 × 125 µm gate terminal configuration is shown. The source, drain, and gate contacts are clearly labelled as shown in the FIG. 8A, along with the metal interconnect bars and bus structures. Notably, multiple free-standing air bridges are visible, used to connect individual source terminals back to a common source bus or pad, ensuring uniform potential and reducing source inductance. Further, a "T"-shaped air bridge highlighted as "T Air Bridge" which connects the central source pad to two adjacent regions, forming the "head" and "foot" of the T-shaped air bridge. This design is particularly significant in symmetric HEMT layouts where an even number of gate terminals (such as 8 terminals) lead to a central source terminal that cannot be connected using a traditional linear bridge. The T-shaped geometry ensures symmetrical current flow, enhances grounding, and minimizes resistance and parasitic effects in high-frequency operations.
Referring to FIG. 8B, the side view of the air bridge implemented on the GaN HEMT device fabricated on the SiC is shown. The bridges are clearly elevated with well-defined air gaps, formed through the controlled thermal reflow operation and electroplating process. The arch-like geometry confirms the successful resist shaping and reflow prior to metal deposition. The air bridges appear mechanically robust, properly anchored at both ends, and uniformly elevated, features essential for ensuring low parasitic capacitance and high-frequency signal integrity.
The semiconductor device 802 (i.e., the GaN HEMT device) comprises the substrate 202, a plurality of source pads disposed on the substrate 202 which are spaced apart from one another and a number of air bridge metal interconnects electrically connecting two or more of the plurality of source pads, where the air bridge metal interconnect is free-standing between the two or more of the plurality of source pads and spaced apart from the substrate 202 to define an air gap beneath the air bridge metal interconnect. The semiconductor device 802 is fabricated on the high-resistivity Si or SiC substrate, where the plurality of source pads are patterned and spaced apart to support multi-finger GaN HEMT structures, such as the 8 × 125 μm gate periphery device. To achieve minimized parasitic effects in high-frequency operation, the free-standing air bridge metal interconnects are employed to electrically connect two or more of the spaced-apart source pads. Each of the air bridges is formed using a reflowed resist support structure, which, after thermal treatment at 150°C for 10 minutes, assumes a curved profile that defines the height of the air bridge and creates a clear air gap beneath it. The Ni/Au seed layer is deposited conformally, followed by electroplating of gold in a precisely defined region, after which the underlying resist and excess seed layer are removed in the single lift-off step, resulting in a mechanically stable, elevated metal span. The air bridge interconnect remains suspended above the substrate 202, ensuring that it does not contact the surface, thereby forming a defined air gap that significantly reduces substrate coupling and supports reliable, high-performance RF device operation.
In accordance with an embodiment, the semiconductor device 802 comprises the air bridge metal interconnect comprising a T-shaped configuration in which both a head portion and a foot portion of the T-shaped configuration are suspended above the substrate 202, and where the air bridge metal interconnect is configured to connect the two or more of the plurality of source pads to one or more ground planes of a coplanar waveguide structure of the semiconductor device 802. The air bridge metal interconnects can be multi-layer bridges or even like a star network. The T-shaped configuration is fabricated using the method 100 (have been described in detail, for example, in FIGs. 1A-1B) which enables dual lithography, controlled thermal reflow of the first resist layer, seed layer deposition, and selective electroplating, followed by solvent-based lift-off, ensuring that the full span of the bridge remains free-standing without relying on any underlying dielectric support. The head of the T-shaped interconnect extends laterally to contact two ground planes of a coplanar waveguide (CPW), while the foot connects to a central source pad, thus linking the middle source finger of the multi-finger GaN HEMT device to ground symmetrically. This design is particularly beneficial in layouts with an even number of gate fingers, such as 4 × 125 µm or 8 × 125 µm devices, where a conventional bridge would leave inner source fingers unconnected. The ability to fabricate the entire T-structure in a single electroplating step, with both arms of the “T” suspended, is achieved by optimizing the resist thickness and bridge geometry, which also allows for extensions into more complex topologies, such as multi-layer bridges or star-shaped networks interconnecting several pads to a central node. This suspended and centrally anchored T-shaped configuration reduces current crowding, enables uniform signal return paths, and maintains minimal capacitive coupling to the substrate, resulting in consistent high-frequency performance and improved thermal reliability across RF and power device architectures.
In an exemplary scenario, a commercially available GaN HEMT device on a SiC wafer is diced into 1 cm × 1 cm pieces. One of the diced samples is selected for fabrication of multi-finger GaN HEMT device featuring an 8 × 125 μm gate periphery. The process begins with standard solvent cleaning of the substrate 202 to ensure surface cleanliness and adhesion for subsequent steps. The ohmic contact pads are patterned using e-beam lithography with a bilayer resist stack comprising copolymer Electron-beam Lithography Resist, Type 9 (EL9) and Poly (methyl methacrylate) (PMMA) resists. The metal stack of Ti/Al/Ni/Au (20/120/30/50 nm) is deposited via thermal evaporation, followed by rapid thermal annealing at 800°C for 60 seconds in a nitrogen atmosphere to form low-resistance Ohmic contacts. The Transmission Line Method (TLM) measurements revealed the ohmic contact resistance of 0.52 Ω·mm. The source-to-drain spacing is maintained at approximately 4 µm. The device isolation is achieved using Reactive Ion Etching (RIE) with a gas mixture of Boron Trichloride (BCl₃) and Chlorine (Cl₂) chemistry, and gate fingers are patterned using e-beam lithography with bilayer PMMA resist, achieving a gate length (Lg) of approximately 220 nm. A Ni/Au (30/100 nm) metal stack is used for the gate, deposited using e-beam evaporation. The gate-to-source distance is maintained at approximately 700 nm. A 100 nm Silicon Nitride (SiNx) passivation layer is then deposited using Plasma-Enhanced Chemical Vapor Deposition (PECVD). The ohmic contact openings are defined using RIE etching (e.g., a gas mixture of trifluoromethane (CHF₃) and oxygen (O₂)). To further enhance performance, the source-connected field plates may be added using e-beam lithography and Ni/Au (30/100 nm) deposition via e-beam evaporation. The CPW probing pads are patterned using optical lithography with AZ5214E resist using the image reversal technique, and Ni/Au (30/200 nm) is deposited using sputtering. To enable microwave power measurements, this is required to thicken the source/drain fingers and probing pads, and also to electrically connect all individual source pads. This is accomplished using electroplating, through which source pads are connected to the ground planes of the CPW structure using free-standing air bridge interconnects. This approach not only thickened the metal for RF performance but also allowed the air bridges to be fabricated in the same step, thus streamlining the process. However, in configurations with an even number of gate fingers, such as the 8 × 125 µm layout, one central source finger remains unconnected if only linear bridges are used. To address this, a “T” air bridge structure, where the foot of the T connects to the center-most source pad, and the head of the T spans both CPW ground pads, completing the interconnection symmetrically. This solution is specifically required for even-numbered gate finger configurations (e.g., 4×125 µm, 8×125 µm), but not for odd configurations (e.g., 6×125 µm, 10×125 µm), where traditional bridge arrangements are sufficient. The fabrication of the “T” air bridge follows the same process flow as described previously for standard air bridges.
Advantageously, the method 100 for fabricating the air bridge metal interconnect on the semiconductor device 802 is configured to enable a simplified, etch-free, and high-precision fabrication of the free-standing interconnect structure that electrically connects the at least two metal pads on the substrate 202. The method 100 includes forming the first resist layer 206 on the substrate 202 comprising the at least two metal pads 204, and patterning the first resist layer 206 to create support regions between and adjacent to the pads. Subjecting the patterned first resist layer to a controlled thermal reflow operation causes it to form an arced support structure 208, which defines the vertical clearance and structural profile of the resulting air bridge. Moreover, depositing the thin continuous seed layer 210 of conductive material, such as Ni/Au, over both the reflowed resist and exposed substrate regions, including the at least two metal pads 204, provides a uniform base for subsequent metal deposition. Furthermore, the second resist layer 212 is applied and patterned to define the bridge span region that connects the at least two metal pads 204, allowing selective electroplating of a metal layer, such as gold, onto the exposed seed layer to form the air bridge. Additionally, the single lift-off step using a heated solvent removes both resist layers along with the covered portions of the seed layer, resulting in a clean and precisely formed free-standing air bridge structure. The method 100 eliminates the requirement for any dry or wet etching processes, thereby reducing fabrication complexity, improving structural fidelity, and enabling seamless integration into RF and power semiconductor devices.
The method 100 for fabricating the air bridge metal interconnect 218 presents a significant advancement in semiconductor manufacturing by offering a simplified yet robust process that minimizes complexity without compromising performance. Unlike conventional approaches that rely on multiple lithography steps, harsh seed layer etching, or complex sacrificial materials, the method 100 utilizes only two optical lithography steps combined with a straightforward electroplating and lift-off process. By eliminating the need for seed layer etching which often introduces surface roughness and residual metal particles that risk shorting devices the method 100 ensures a cleaner, more reliable interconnect structure. Additionally, the incorporation of the controlled thermal reflow step enhances the mechanical stability of the resist support, leading to defect-free air bridges with consistent height and curvature.
The air bridges fabricated using the method 100 exhibit excellent resilience under various stress conditions, including prolonged ultrasonic cleaning, substrate thinning down to ~100 µm, and FIB milling. These tests demonstrate the durability and structural integrity of the air bridges, which is vital for their integration into high-performance devices. Furthermore, the ability to fabricate complex structures, such as "T"-shaped air bridges for symmetric connection in multi-finger GaN HEMTs, highlights the method's adaptability and design flexibility. The process is material-agnostic, making it compatible with a wide range of semiconductor platforms including GaN on SiC and high-resistivity silicon substrates.
From a practical utility perspective, the method 100 directly addresses key challenges in RF and high-power semiconductor devices by enabling low-parasitic, mechanically robust, and thermally stable interconnects. The air bridges play a vital role in minimizing capacitive coupling, improving signal integrity, and allowing for high-density layouts in integrated circuits. The proposed fabrication technique is not only scalable for industrial implementation but also cost-effective due to its minimal process steps and avoidance of specialized etching chemistries. Moreover, its application in GaN HEMTs and similar devices positions it as a vital enabler for next-generation wireless communication, radar systems, and power electronics, where reliability, frequency response, and thermal performance are paramount.
Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as “including”, “comprising”, “incorporating”, “have”, “is” used to describe, and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.
, Claims:CLAIMS
We claim:
1. A method (100) for fabricating an air bridge metal interconnect (218) on a substrate (202) of a semiconductor device (802), comprising:
forming a first resist layer (206) on the substrate (202) comprising at least two metal pads (204) to be electrically interconnected.
patterning the first resist layer (206) to generate support regions between and adjacent to the at least two metal pads (204);
subjecting the patterned first resist layer to a controlled thermal reflow operation to generate an arced support structure (208) spanning between the at least two metal pads (204);
depositing a continuous seed layer of conductive material over the reflowed first resist layer and exposed portions of the substrate (202), including the at least two metal pads (204);
forming a second resist layer (212) over the continuous seed layer;
patterning the second resist layer (212) to define a bridge span region (214) connecting the at least two metal pads (204);
electroplating a metal layer (216) onto exposed portions of the continuous seed layer within the defined bridge span region to form an air bridge structure; and
removing both the first and second resist layers along with portions of the continuous seed layer not covered by the electroplated metal layer in a single lift-off step, thereby generating a free-standing air bridge metal interconnect electrically connecting the at least two metal pads (204) on the substrate (202).

2. The method (100) as claimed in claim 1, wherein the substrate (202) is made of a semiconductor material selected from a group comprising: Silicon, Silicon Carbide, Sapphire, Gallium Nitride on Silicon Carbide, Gallium Nitride on Silicon, Free-standing Gallium Nitride, Gallium Arsenide, Indium Phosphide, Gallium Oxide, etc.

3. The method (100) as claimed in claim 1, wherein at least two metal pads (204), the continuous seed layer, and the electroplated metal layer, each comprises one or more metals selected from a group comprising: Gold, Nickel, Titanium, Chromium, Aluminum, and Copper etc.

4. The method (100) as claimed in claim 1, wherein each of the first resist layer (206) and the second resist layer (212) comprises a resist material independently selected from one or more of: a photoresist material, an electron-beam resist material, a deep ultra-violet resist material, or a chemically amplified resist material and wherein each resist material is of a thickness in a range of 1 micrometre (µm) to 10 µm.

5. The method (100) as claimed in claim 1, wherein the single lift-off step comprises immersing the substrate (202) in an organic solvent solution heated to a temperature between 60°C and 75°C for a specified duration to remove the first and second resist layers and covered portions of the continuous seed layer present adjacent to the at least two metal pads (204), without employing any dry etching or wet chemical etching operations.

6. The method (100) as claimed in claim 1, wherein the free-standing air bridge metal interconnect is configured to remain structurally intact when subjected to at least one of: an ultrasonic cleaning operation at a specified frequency and time duration, a substrate thinning operation comprising reducing a thickness of the substrate (202), and a Focused Ion Beam, FIB milling operation comprising removing a portion of the free-standing air bridge structure.

7. The method (100) as claimed in claim 1, wherein the free-standing air bridge metal interconnect has a structural configuration selected from a group of: a T-shaped structure, a star-shaped structure, and a multi-layer bridge structure.
8. A semiconductor device (802) comprising:
a substrate (202);
a plurality of source pads disposed on the substrate (202) and spaced apart from one another; and
an air bridge metal interconnect (218) electrically connecting two or more of the plurality of source pads,
wherein the air bridge metal interconnect (218) is free-standing between the two or more of the plurality of source pads and spaced apart from the substrate (202) to define an air gap beneath the air bridge metal interconnect (218).
9. The semiconductor device (802) as claimed in claim 9, comprises the air bridge metal interconnect (218) comprising a T-shaped configuration in which both a head portion and a foot portion of the T-shaped configuration are suspended above the substrate (202), and wherein the air bridge metal interconnect (218) is configured to connect the two or more of the plurality of source pads to one or more ground planes of a coplanar waveguide structure of the semiconductor device (802).