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Design And Analysis Of Optimized Cmos Receiver S Parameters For Ultra Wide Bandwidth In Wireless Applications

Abstract: ABSTRACT OF THE INVENTION Title: Design and Analysis of Optimized CMOS Receiver S-Parameters for Ultra-Wide Bandwidth in Wireless Applications The invention provides a low-power, low-noise CMOS UWB receiver front-end integrating an active balun for efficient single-ended-to-differential signal conversion. Implemented in 45 nm technology, it achieves flat gain ≈ 6 dB, noise < 4 dB, and phase ≈ 180°, while consuming ≈ 5.45 mW. The design ensures balanced S-parameters and compact integration for next-generation wireless transceivers, enhancing signal integrity and system efficiency.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
11 October 2025
Publication Number
46/2025
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
Parent Application

Applicants

Pradeep Kumar S
Pradeep Kumar S Assistant Professor, Department of Electronics and Communications Engineering, Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore pradeepkumar.s@nmit.ac.in
Parameshachari B D
Parameshachari B D Professor & Head, Department of Electronics and Communications Engineering, Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore Email: drparamesh81@gmail.com
Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore
Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore Email: drparamesh81@gmail.com

Inventors

1. Pradeep Kumar S
Pradeep Kumar S Assistant Professor, Department of Electronics and Communications Engineering, Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore pradeepkumar.s@nmit.ac.in
2. Parameshachari B D
Parameshachari B D Professor & Head, Department of Electronics and Communications Engineering, Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore Email: drparamesh81@gmail.com
3. Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore
Nitte Meenakshi Institute of Technology, Nitte (Deemed to be University), Yelahanka, Bangalore Email: drparamesh81@gmail.com

Specification

Description:TITLE OF THE INVENTION
Design and Analysis of Optimized CMOS Receiver S-Parameters for Ultra-Wide Bandwidth in Wireless Applications

FIELD OF INVENTION
The present invention relates to semiconductor circuit design for wireless communication systems.
More particularly, it pertains to a CMOS-based ultra-wideband (UWB) receiver front-end employing an optimized active-balun architecture that delivers balanced gain, low noise, and minimal power consumption across the 3–4 GHz frequency range.
The invention ensures high-efficiency signal conversion for next-generation UWB and 5 G transceivers.

BACKGROUND OF THE INVENTION
Ultra-wideband (UWB) receivers are integral to modern high-speed wireless links. Conventional balun designs face limitations such as narrow bandwidth, phase imbalance, and high power consumption.
• Prior Art 1: Fang et al., 2020—a varactor-tuned planar balun with adjustable frequency, but limited fixed-gain control and noise optimization.
• Prior Art 2: Pietron et al., 2021—an active balun with a Gilbert mixer achieving moderate gain but high noise figure (7.7 dB).
• Prior Art 3: Pakasiri et al., 2023—a compact inductor-shared balun emphasizing isolation but lacking phase linearity.
• Prior Art 4: Meaamar et al., 2011—a 3.1–8 GHz receiver front-end showing fluctuating noise (5.4–8.3 dB).
• Prior Art 5: Razavi et al., 2005—a direct-conversion transceiver with good gain but excessive 105 mW power draw.
From these, it is evident that a compact, low-power, low-noise CMOS balun with stable S-parameters and balanced phase output is needed for UWB front-end applications.

OBJECT OF THE INVENTION
The primary objective is to provide an optimized CMOS UWB receiver front-end with:
1. Balanced single-ended-to-differential conversion.
2. Flat gain (> 6 dB) and low noise figure (< 4 dB).
3. Phase balance close to 180° with mismatch < 1 dB.
4. Reduced power consumption (< 5.5 mW).
5. Impedance matching at 50 Ω for minimal reflection.

SUMMARY OF THE INVENTION
The invention discloses a common-gate/common-source hybrid active-balun implemented in 45 nm CMOS technology.
The design combines a dual-path amplifier topology providing complementary outputs: one preserving phase (common-gate) and another inverted (common-source).
This yields differential outputs with ~180° phase difference, gain > 15 dB (LNA + balun chain), and noise < 4 dB, while drawing ≈ 5.45 mW.
Simulated S-parameters show S₁₁ < –10 dB and flat S₂₁ ≈ 6 dB across 3–4 GHz.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWING
Figure 1: Block diagram of the proposed UWB Receiver Front-End showing signal flow from input to differential output.

DETAILED DESCRIPTION OF THE INVENTION
The proposed receiver front-end comprises sequential functional blocks: LNA → Active Balun → Mixer → Buffer.
1. Low Noise Amplifier (LNA): Amplifies 3–4 GHz RF signals with 15 dB gain and noise < 3 dB, setting overall sensitivity.
2. Active Balun: Combines a common-gate path (non-inverting) and a common-source path (inverting 180°) using transistors M₁ and M₂, load resistors R₁–R₂, and bias network R₃–Cdc.
 • Provides < 0.3 dB gain mismatch and phase deviation ≈ 177°.
 • Power gain ≈ 6 dB and NF < 4 dB.
3. Mixer Stage: Down-converts the balanced RF to IF using a dual-phase LO.
4. Output Buffer: Ensures 50 Ω matching for test and system integration.
Fabricated in 45 nm CMOS, simulations verified S₁₁ < –10 dB, S₂₁ flat 6 dB, and overall power < 5.45 mW.
The design achieves efficient energy use with compact silicon footprint and high UWB fidelity.

CLAIMS
I/We Claim
1. A CMOS-based receiver front-end system for ultra-wideband communication comprising a low-noise amplifier, an active balun, and a double-balanced mixer, characterized in that it provides differential outputs with phase difference ≈ 180°, gain > 15 dB, and total power consumption < 5.5 mW.
2. The system as claimed in claim 1, wherein the active balun comprises a common-gate and common-source amplifier arranged to produce complementary outputs with gain mismatch < 1 dB and noise figure < 4 dB.
3. The system as claimed in claim 1, wherein the input and output return losses are less than –10 dB across 3–4 GHz frequency band, ensuring stable S-parameter performance.
4. The system as claimed in claim 1, wherein the transistor sizing and biasing are optimized in 45 nm CMOS process to reduce parasitic capacitance and enhance frequency response.
5. The system as claimed in claim 1, wherein the output buffer maintains a 50 Ω impedance for measurement compatibility and signal integrity in UWB applications.

ABSTRACT OF THE INVENTION
Title: Design and Analysis of Optimized CMOS Receiver S-Parameters for Ultra-Wide Bandwidth in Wireless Applications
The invention provides a low-power, low-noise CMOS UWB receiver front-end integrating an active balun for efficient single-ended-to-differential signal conversion.
Implemented in 45 nm technology, it achieves flat gain ≈ 6 dB, noise < 4 dB, and phase ≈ 180°, while consuming ≈ 5.45 mW.
The design ensures balanced S-parameters and compact integration for next-generation wireless transceivers, enhancing signal integrity and system efficiency.

, Claims:CLAIMS
I/We Claim
1. A CMOS-based receiver front-end system for ultra-wideband communication comprising a low-noise amplifier, an active balun, and a double-balanced mixer, characterized in that it provides differential outputs with phase difference ≈ 180°, gain > 15 dB, and total power consumption < 5.5 mW.
2. The system as claimed in claim 1, wherein the active balun comprises a common-gate and common-source amplifier arranged to produce complementary outputs with gain mismatch < 1 dB and noise figure < 4 dB.
3. The system as claimed in claim 1, wherein the input and output return losses are less than –10 dB across 3–4 GHz frequency band, ensuring stable S-parameter performance.
4. The system as claimed in claim 1, wherein the transistor sizing and biasing are optimized in 45 nm CMOS process to reduce parasitic capacitance and enhance frequency response.
5. The system as claimed in claim 1, wherein the output buffer maintains a 50 Ω impedance for measurement compatibility and signal integrity in UWB applications.

Documents

Application Documents

# Name Date
1 202541098121-FORM 1 [11-10-2025(online)].pdf 2025-10-11
2 202541098121-FIGURE OF ABSTRACT [11-10-2025(online)].pdf 2025-10-11
3 202541098121-DRAWINGS [11-10-2025(online)].pdf 2025-10-11
4 202541098121-COMPLETE SPECIFICATION [11-10-2025(online)].pdf 2025-10-11
5 202541098121-FORM-9 [23-10-2025(online)].pdf 2025-10-23