1. A low-power current-based physically unclonable function (PUF) device (100), comprising: plurality of process-sensitive current generator (PCG) units (102), wherein each of the PCG unit (102) comprises a MOSFET-based current source biased to operate in a subthreshold or near-threshold region and sharing common biasing conditions including a gate bias voltage (VG), wherein the plurality of PCG units (102) are nominally identical in structure and are configured to generate mutually variant output currents under identical biasing conditions due to inherent semiconductor fabrication process variations; at least one challenge input unit (104) configured to receive a digital challenge signal; a current steering and selection module (106) operatively coupled to the plurality of PCG units (102) and to the challenge input unit (104), wherein the current steering and selection module (106) comprises a plurality of transistor-based switching elements configured to selectively route, mirror, and combine output currents of selected PCG units (102) in accordance with the received digital challenge signal so as to form differential current paths; a sense-amplifier-based evaluation unit (108) operatively coupled to the current steering and selection module (106), wherein the sense-amplifier-based evaluation unit (108) comprises a regenerative cross-coupled latch configured to compare the differential current paths and generate a corresponding digital response bit based on a polarity of current difference; and a low-power trigger module (110) configured to activate the sense-amplifier-based evaluation unit (108) only during response evaluation, wherein the digital response bit is derived from process-sensitive current differentials generated by the plurality of PCG units (102) and is reproducible for a given digital challenge under identical operating conditions, wherein the PCG units (102) operate in a subthreshold or near-threshold region such that the low-power current-based PUF device (100) exhibits a total power consumption between 12.7 µW and 20.2 µW across a supply voltage range of 1.2 V to 1.4 V.

2. The low-power current-based PUF device (100) as claimed in claim 1, wherein each of the PCG unit (102) comprises an NMOS transistor structure configured with identical channel geometry and biased using a common gate bias voltage (VG), and wherein the PCG units (102) are configured to generate output currents that differ from one another under identical biasing conditions due to variations in threshold voltage, carrier mobility, oxide thickness, channel dimensions, or doping concentration.

3. The low-power current-based PUF device (100) as claimed in claim 1, wherein the current steering and selection module (106) comprises current mirror structures and transistor-based switching elements configured to implement challenge-dependent differential current routing, and wherein the current steering and selection module (106) further comprises a tuning input configured to adjust bias conditions to compensate for environmental variations including temperature fluctuations, supply voltage variations, and aging effects.

4. The low-power current-based PUF device (100) as claimed in claim 1, wherein the sense-amplifier-based evaluation unit (108) is configured to amplify small current differences into a stable full-swing digital output using positive feedback of the cross-coupled latch.

5. The low-power current-based PUF device (100) as claimed in claim 1, wherein the low-power trigger module (110) comprises a pulse-based activation circuit configured to switch the sense-amplifier-based evaluation unit (108) ON only during a comparison interval to minimize static power consumption.

6. The low-power current-based PUF device (100) as claimed in claim 1, wherein the low-power current-based PUF device (100) is configured to exhibit reproducible digital response output under ±10% variation of supply voltage and gate bias voltage within the operational range.

7. The low-power current-based PUF device (100) as claimed in claim 1, wherein the plurality of PCG units (102) comprise at least four PCG units configured to generate differential current pairs in response to different digital challenges.

8. The low-power current-based PUF device (100) as claimed in claim 1, wherein the digital response bit is usable for cryptographic key generation, authentication, device identity verification, or secure boot of an electronic system.

9. A method of generating a unique PUF response in a low-power current-based physically unclonable function (PUF) device (100), comprising: generating plurality of process-sensitive current outputs using plurality of process-sensitive current generator (PCG) units (102); receiving a digital challenge signal by at least one challenge input unit (104); steering and combining the generated currents based on the received digital challenge by a current steering and selection module (106); and triggering a sense-amplifier-based evaluation unit (108) for current evaluation and generating a digital response bit corresponding to a magnitude difference of the combined currents.

Description:DESCRIPTION:
Field of the invention:
[0001] The present disclosure generally relates to the technical field of hardware security in integrated circuit (IC) design, and in specific relates to current-based physical unclonable functions (PUFs) that exploit semiconductor process variations to generate unique, device-specific responses for secure authentication and cryptographic key generation.
Background of the invention:
[0002] In recent years, widespread deployment of electronic devices in applications such as Internet of Things (IoT), embedded systems, and consumer electronics has substantially increased the demand for secure hardware authentication and cryptographic key protection. Physical Unclonable Functions (PUFs) have emerged as a lightweight hardware security primitive by exploiting inherent manufacturing variations in semiconductor devices to generate unpredictable and device-unique responses. Existing PUF architectures include ring-oscillator (RO) PUFs, SRAM-based PUFs, and delay-based PUFs. However, these architectures suffer from critical limitations such as high-power consumption, larger circuit complexity, limited challenge–response pair (CRP) space, and sensitivity to environmental variations including temperature and voltage fluctuations.
[0003] Current-based PUF architectures have been proposed to leverage transistor leakage characteristics in the subthreshold region to reduce power and area. Yet several prior implementations incur additional limitations such as poor reliability under supply voltage variations, limited robustness against machine-learning modeling attacks, and requirement of large comparator or sense-amplifier circuitry at each PUF cell, leading to increased area overhead. PUFs implemented using complementary cascode current mirrors also exhibit reduced output stability due to environmental dependency, limiting their use as strong PUFs with scalable CRP generation.
[0004] The increasing ubiquity of electronics in smart infrastructure, autonomous devices, healthcare systems, and industrial automation has heightened the vulnerability of hardware to cloning, counterfeiting, and unauthorized access. Security keys stored in non-volatile memory can be exposed through invasive attacks, side-channel analysis, and reverse engineering. To counter such threats, hardware security primitives like Physically Unclonable Functions (PUFs) have gained recognition for enabling silicon-intrinsic trust, where authentication keys are generated on demand and never stored permanently in the device.
[0005] A prior art document, US11108572B2, discloses a physically unclonable function PUF device comprising a plurality of PUF cells, each including a sense amplifier and load circuit configured to generate bit line and complementary bit line outputs. However, such prior art architecture primarily relies on voltage-mode sensing, which requires charging and discharging of bit line capacitances, resulting in increased dynamic power consumption and slower response generation. Further, the inclusion of sense amplifiers and load circuits within each PUF cell increases circuit complexity, silicon area, and static power consumption. As a result, the prior art lacks the ability to achieve ultra-low-power operation, efficient current-mode entropy extraction, and improved robustness under process, voltage, and temperature variations.
[0006] Among known PUF architectures, ring-oscillator PUFs require frequency comparison across multiple oscillators and consume higher dynamic power. SRAM PUFs depend on unpredictable memory start-up states but require additional error-correction hardware to manage response instability. Arbiter and delay-based PUFs provide a stronger challenge–response space yet exhibit susceptibility to temperature variations and machine learning-based modeling attacks that can predict responses with high accuracy. These issues constrain their applicability in low-power resource-limited environments such as RFID tags, smart sensors, and IoT edge devices.
[0007] Therefore, there exists a clear need for a low-power, high-reliability, and environmentally robust current-based PUF solution that consumes significantly lower energy than conventional architectures, maintains output stability across diverse operating voltages, supports a scalable challenge space to bolster resistance against ML attacks, and reduces circuit complexity while preserving uniqueness and response reproducibility.
Objectives of the invention:
[0008] The primary objective of the invention is to design and implement a low-power current-based Physically Unclonable Function (PUF) that enables secure and reliable hardware authentication using inherent semiconductor process variations.
[0009] The other objective of the invention is to reduce power consumption by utilizing subthreshold leakage currents and an automatic current cut-off mechanism, making the PUF suitable for battery-powered and passive devices.
[0010] The other objective of the invention is to enhance response stability and repeatability across variations in supply voltage, gate bias voltage, and environmental operating conditions such as temperature.
[0011] Another objective of the invention is to improve uniqueness and randomness of the generated challenge–response pairs (CRPs) by leveraging sensitive current differentials derived from transistor-level mismatches.
[0012] The other objective of the invention is to minimize circuit complexity and area overhead by employing a simplified current-steering architecture that can be easily integrated into existing IC designs.
[0013] Yet another objective of the invention is to provide scalability in the challenge space, supporting a strong PUF implementation capable of resisting machine learning-based modeling or prediction attacks.
[0014] Another objective of the invention is to enable flexible mixed-signal integration allowing seamless deployment of the PUF within analog, digital, and RF security modules in System-on-Chip (SoC) environments.
Summary of the invention:
[0015] The present disclosure proposes a low-power current-based physically unclonable function (PUF) device. The following presents a simplified summary in order to provide a basic understanding of some aspects of the claimed subject matter. This summary is not an extensive overview. It is not intended to identify key/critical elements or to delineate the scope of the claimed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
[0016] In order to overcome the above deficiencies of the prior art, the present disclosure is to solve the technical problem to provide current-based physical unclonable functions (PUFs) that exploit semiconductor process variations to generate unique, device-specific responses for secure authentication and cryptographic key generation.
[0017] According to an aspect, the invention provides a low-power current-based physically unclonable function (PUF) device comprises plurality of process-sensitive current generator (PCG) units, at least one challenge input unit, a current steering and selection module, a sense-amplifier-based evaluation unit, and a low-power trigger module.
[0018] The PUF device is configured to operate at low power by utilizing current-mode operation and process-sensitive current differentials for response generation. The PUF device exhibits a power consumption between 12.7 μW and 20.2 μW during operation across a supply voltage range of 1.2 V to 1.4 V. The PUF device exhibits identical digital response output for ±10% variation in supply voltage and gate bias voltage within the operational range.
[0019] In one embodiment, the PCG units are configured to generate mutually variant output currents based on inherent semiconductor process variations. Each of the plurality of PCG units comprises a MOSFET-based current source biased to operate in a subthreshold or near-threshold region to enhance process-variation sensitivity and reduce power consumption.
[0020] In one embodiment, the challenge input unit is configured to receive a digital challenge signal. The current steering and selection module is operatively coupled to the challenge input unit and the plurality of PCG units. The current steering and selection module is configured to selectively route and combine the output currents of the plurality of PCG units in accordance with the received challenge signal. The current steering and selection module comprises a plurality of transistor-based switching elements configured to implement challenge-dependent current mirroring or differential current routing. The current steering and selection module further comprises a tuning input configured to adjust current biasing and compensate for environmental or process drifts.
[0021] In one embodiment, the sense-amplifier-based evaluation unit is configured to compare the routed and combined output currents and generate a corresponding digital response bit. The sense-amplifier-based evaluation unit comprises a cross-coupled latch configured to detect a polarity of current difference and generate a stable digital output. The output of the sense-amplifier-based evaluation unit is used for cryptographic key generation, authentication, device identity verification, or secure boot of an electronic system.
[0022] In one embodiment, the low-power trigger module is configured to activate the sense-amplifier-based evaluation unit only during comparison. The low-power trigger module comprises a pulse-based activation circuit configured to minimize static power consumption by switching the sense-amplifier-based evaluation unit ON only during response evaluation.
[0023] According to another aspect, the invention provides a method of generating a unique PUF response in the low-power current-based physically unclonable function device. The method comprises generating a plurality of process-sensitive current outputs using the PCG units, receiving a digital challenge signal by the challenge input unit, steering and combining the generated currents based on the received digital challenge by the current steering and selection module, and triggering the sense-amplifier-based evaluation unit for current evaluation and generating a digital response bit corresponding to a magnitude difference of the combined currents.
[0024] Further, objects and advantages of the present invention will be apparent from a study of the following portion of the specification, the claims, and the attached drawings.
Detailed description of drawings:
[0025] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, explain the principles of the invention.
[0026] FIG. 1 illustrates a block diagram of a low-power current-based physically unclonable function (PUF) device, in accordance to an exemplary embodiment of the invention.
[0027] FIG. 2 illustrates a circuit-level implementation of the current-based PUF device is illustrated, in accordance to an exemplary embodiment of the invention.
[0028] FIG. 3 illustrates a flowchart a method of generating a unique PUF response in the low-power current-based physically unclonable function device, in accordance to an exemplary embodiment of the invention.
[0029] FIG. 4 illustrates a graphical comparison of the power consumption of different Physically Unclonable Function (PUF) types is illustrated, in accordance to an exemplary embodiment of the invention.
[0030] FIGs. 5A – 5C illustrate graphs a variation of output currents Ia and Ib with respect to different challenge inputs for three gate voltage (Vg) conditions, in accordance to an exemplary embodiment of the invention.
[0031] FIG. 6 illustrates a graph that illustrates the digital output response (SO) of the current-source-based PUF for 16 different input challenge indices, in accordance to an exemplary embodiment of the invention.
[0032] FIGs. 7A- 7C illustrate graphs the variation of the differential branch currents Ia and Ib across 16 challenge indices for three different gate voltages (VG) while keeping the supply voltage constant at 1.4 V, in accordance to an exemplary embodiment of the invention.
[0033] FIG. 8 illustrates a graph illustrates the relationship between the input challenge index and the corresponding PUF output bit (SO) for a fixed supply voltage under three different gate bias voltages, in accordance to an exemplary embodiment of the invention.
[0034] FIG. 9A- 9B illustrate graphs shows the power consumption, in accordance to an exemplary embodiment of the invention.
Detailed invention disclosure:
[0035] Various embodiments of the present invention will be described in reference to the accompanying drawings. Wherever possible, same or similar reference numerals are used in the drawings and the description to refer to the same or like parts or steps.
[0036] The present disclosure has been made with a view towards solving the problem with the prior art described above, and it is an object of the present invention to provide current-based physical unclonable functions (PUFs) that exploit semiconductor process variations to generate unique, device-specific responses for secure authentication and cryptographic key generation.
[0037] According to an exemplary embodiment of the invention, FIG. 1 refers to a block diagram a low-power current-based physically unclonable function (PUF) device 100. The PUF device 100 comprises plurality of process-sensitive current generator (PCG) units 102, at least one challenge input unit 104, a current steering and selection module 106, a sense-amplifier-based evaluation unit 108, and a low-power trigger module 110.
[0038] The PUF device 100 is configured to operate at low power by utilizing current-mode operation and process-sensitive current differentials for response generation. The PUF device 100 exhibits a power consumption between 12.7 μW and 20.2 μW during operation across a supply voltage range of 1.2 V to 1.4 V. The PUF device 100 exhibits identical digital response output for ±10% variation in supply voltage and gate bias voltage within the operational range. In one embodiment, the PCG units 102 are configured to generate mutually variant output currents based on inherent semiconductor process variations. Each of the plurality of PCG units 102 comprises a MOSFET-based current source biased to operate in a subthreshold or near-threshold region to enhance process-variation sensitivity and reduce power consumption.
[0039] In an exemplary embodiment, the PUF device 100 comprises at least four PCG units 102. In one embodiment, the PCG units 102 are configured to generate mutually variant current outputs under substantially identical biasing conditions. Although the PCG units 102 are nominally identical in design and share common bias voltages, including a common gate voltage Vg, inherent semiconductor fabrication process variations cause measurable differences in their electrical characteristics. Such process variations include, but are not limited to, variations in threshold voltage, carrier mobility, oxide thickness, channel dimensions, and doping concentration. As a result, the output currents generated by the plurality of PCG units 102 are mutually variant even when subjected to identical biasing conditions. In certain embodiments, the output currents of the PCG units 102 differ from one another by at least 0.1 percent under identical biasing conditions, thereby ensuring sufficient entropy for reliable physically unclonable function operation.
[0040] The PUF device 100 is constructed using the PCG units 102. The MOSFET-based current source structure biased in the subthreshold or near-threshold operating region to enhance sensitivity to process variations while reducing power consumption. The PCG units 102 share common biasing nodes, including the gate bias voltage Vg, such that the observed differences in output currents arise primarily from intrinsic and uncontrollable fabrication variations rather than externally introduced bias differences. These process-sensitive current outputs constitute the fundamental entropy source of the PUF device 100.
[0041] The current outputs generated by the PCG units 102 are operatively coupled to the current steering and selection module 106, which is controlled by the challenge input unit 104. The challenge input unit 104 is configured to receive a digital challenge signal and to selectively control the routing configuration of the current steering and selection module 106 in response thereto. The current steering and selection module 106 selectively routes, mirrors, and combines the output currents of selected PCG units 102 in accordance with the received challenge signal, thereby forming differential current paths corresponding to the applied challenge.
[0042] The combined currents are supplied to the sense-amplifier-based evaluation unit 108, which is configured to detect and evaluate the magnitude and polarity of the differential current. The sense-amplifier-based evaluation unit 108 comprises a regenerative cross-coupled latch configured to amplify small current differences and resolve them into a stable digital response bit. Because the evaluated currents originate from the PCG units 102, the resulting digital response is inherently device-specific and resistant to cloning or prediction.
[0043] In certain embodiments, the current steering and selection module 106 further comprises a tuning input configured to adjust bias conditions to compensate for environmental variations, including temperature fluctuations, supply voltage variations, and long-term aging effects. This tuning capability enhances the reliability, repeatability, and stability of the generated PUF responses without degrading uniqueness.
[0044] In accordance with the present invention, the architecture relies exclusively on process-sensitive current generation through the plurality of PCG units 102. Although both process-sensitive voltage and current generation mechanisms were initially considered, the present invention employs a current-based architecture to simplify circuit implementation, reduce structural complexity, and improve robustness. The PCG units 102 comprise matched MOS transistor structures configured to amplify intrinsic process-induced electrical mismatches into measurable current differentials. These current differentials are selectively routed, combined, and evaluated by the current steering and selection module 106 and the sense-amplifier-based evaluation unit 108, respectively, to produce a robust, stable, and unique digital response corresponding to the applied challenge.
[0045] Accordingly, the PUF device 100 provides a reliable, low-power, and process-variation-driven hardware security primitive capable of generating unique and reproducible digital responses suitable for secure authentication, cryptographic key generation, and device identity verification applications. In a preferred embodiment, the PCG units 102 include NMOS devices configured with identical geometry and biasing but yielding different current outputs due to unavoidable variations introduced during fabrication. These current outputs form the analog foundation of randomness for generating the PUF response bits.
[0046] In one embodiment, the challenge input unit 104 is configured to receive a digital challenge signal. The current steering and selection module 106 is operatively coupled to the challenge input unit 104 and the plurality of PCG units 102. The current steering and selection module 106 is configured to selectively route and combine the output currents of the plurality of PCG units 102 in accordance with the received challenge signal. The current steering and selection module 106 comprises a plurality of transistor-based switching elements configured to implement challenge-dependent current mirroring or differential current routing. The current steering and selection module 106 further comprises a tuning input configured to adjust current biasing and compensate for environmental or process drifts.
[0047] In one embodiment, the sense-amplifier-based evaluation unit 108 is configured to compare the routed and combined output currents and generate a corresponding digital response bit. The sense-amplifier-based evaluation unit 108 comprises a cross-coupled latch configured to detect a polarity of current difference and generate a stable digital output. The output of the sense-amplifier-based evaluation unit 108 is used for cryptographic key generation, authentication, device identity verification, or secure boot of an electronic system.
[0048] In one embodiment, the low-power trigger module 110 is configured to activate the sense-amplifier-based evaluation unit 108 only during comparison. The low-power trigger module 110 comprises a pulse-based activation circuit configured to minimize static power consumption by switching the sense-amplifier-based evaluation unit 108 ON only during response evaluation. Referring to FIG. 1, there is illustrated a block diagram of a current-source-based PUF architecture 100 in accordance with an embodiment of the present invention. The design focuses on the implementation of a current-mode PUF for low-power applications.
[0049] In the first stage, process-sensitive voltages and/or currents are generated. These quantities are preferably highly sensitive to semiconductor process variations, while remaining substantially insensitive to environmental factors such as temperature, supply voltage fluctuations, and aging effects. Such sensitivity to process parameters, coupled with robustness against environmental variations, ensures high levels of response stability and repeatability. The PCG units 102 thus form the foundation of the PUF and are configured to generate output currents that reflect intrinsic device-level physical variations.
[0050] The challenge input unit 104 receives a plurality of digital challenge bits (e.g., logic “1” or “0”) that determine which PCG units 102 are selected for participation in response generation. Based on the received challenge, the current steering and selection module 106 selectively routes and combines the output currents of the PCG units 102. This programmability enables the generation of a large number of Challenge-Response Pairs (CRPs), thereby substantially enhancing the security strength of the PUF. The tuning input provided to the current steering and selection module 106 enables fine adjustment of biasing parameters within the selection and combining circuitry to compensate for manufacturing variations or optimize performance. In an embodiment, current mirrors and switching elements are used to steer the currents, enabling a unique response to be produced for each distinct challenge due to the unique characteristics of each PCG unit 102.
[0051] In one embodiment, the PCG units 102 are configured to operate in the near-threshold region instead of the subthreshold region in order to achieve an improved balance between energy efficiency, operational stability, and robustness. In the subthreshold region, MOS transistors operate in a weak inversion mode, wherein the drain current exhibits an exponential dependence on the gate voltage and the threshold voltage. As a result, even small variations in threshold voltage or gate bias caused by fabrication process variations, temperature fluctuations, or electrical noise can produce disproportionately large variations in the generated current. Such exponential sensitivity, while beneficial for enhancing entropy, may adversely affect the stability, repeatability, and reliability of the generated current under varying environmental and operating conditions.
[0052] Although operation in the subthreshold region provides extremely low power consumption, it is associated with reduced drive strength, slower response time, increased susceptibility to noise, and higher variability, which may degrade the robustness of the PUF response in certain implementations. These limitations may adversely affect the performance of the sense-amplifier-based evaluation unit 108 and reduce the consistency of the generated digital response bit. In contrast, operating the PCG units 102 in the near-threshold region places the MOS transistors in a moderate inversion operating regime, wherein the drain current exhibits a reduced exponential dependence and a stronger quadratic dependence on the gate voltage. This operating condition reduces the sensitivity of the generated current to small variations in threshold voltage, bias voltage, and environmental conditions. As a result, the PCG units 102 produce more stable and predictable current outputs while still preserving sufficient process-dependent variation to ensure uniqueness.
[0053] Operating in the near-threshold region further improves the signal-to-noise ratio of the generated currents, increases current drive capability, and enables faster response during current evaluation by the sense-amplifier-based evaluation unit 108. This improves the reliability and repeatability of the digital response generated by the PUF device 100. Additionally, near-threshold operation facilitates improved compatibility with low-power digital circuitry, including the challenge input unit 104, the current steering and selection module 106, and the low-power trigger module 110, thereby simplifying mixed-signal integration.
[0054] Accordingly, in embodiments requiring improved robustness across process, voltage, and temperature variations, enhanced operational stability, and reliable bias generation, near-threshold operation of the PCG units 102 provides significant technical advantages over subthreshold operation, while still maintaining substantially low power consumption relative to strong inversion operation. This operating mode enables the PUF device 100 to achieve improved reliability, stability, and performance while preserving the inherent uniqueness derived from semiconductor process variations.
[0055] In this stage, the current steering and selection module 106 is configured to selectively receive and process the output currents generated by the PCG units 102 based on the digital challenge signal received from the challenge input unit 104. The digital challenge signal comprises one or more binary inputs representing logic states of 0 or 1, which determine the selection, routing, and combination of the output currents from the PCG units 102. Based on the applied challenge signal, specific PCG units 102 are selectively enabled, and their corresponding output currents are routed through predetermined current paths within the current steering and selection module 106.
[0056] The current steering and selection module 106 comprises a plurality of transistor-based switching elements and current mirror structures configured to steer, replicate, and combine the selected currents in accordance with the received challenge signal. The selected currents may be combined to form differential current paths that are subsequently provided to the sense-amplifier-based evaluation unit 108 for comparison and response generation. This programmable current selection mechanism enables the PUF device 100 to support a large number of challenge-response pairs, thereby significantly enhancing the security strength and unpredictability of the PUF device 100. Because each PCG unit 102 exhibits inherently unique electrical characteristics due to uncontrollable semiconductor fabrication variations, each unique combination of selected PCG units 102 produces a distinct differential current profile, resulting in a unique and device-specific response.
[0057] The current steering and selection module 106 further comprises a tuning input configured to adjust internal operating parameters, including bias conditions and current balancing characteristics, in order to optimize performance, improve response stability, and compensate for manufacturing variations, environmental fluctuations, and aging effects. The tuning input enables calibration of the current steering and selection module 106 without altering the inherent process-dependent characteristics of the PCG units 102. Accordingly, the selective routing and combination of process-sensitive currents through challenge-dependent switching and current mirroring mechanisms ensures that the generated response of the PUF device 100 remains unique, reliable, and resistant to prediction or cloning.
[0058] In one embodiment of the present invention, the PCG units 102 are configured to exploit inherent leakage current variations present in MOS transistors to generate unique and stable electrical signatures. These leakage current variations arise naturally due to uncontrollable semiconductor fabrication process variations, including differences in threshold voltage, oxide thickness, channel dimensions, and doping concentration. As a result, each PCG unit 102 produces a distinct process-dependent current even under identical biasing conditions.
[0059] The generated process-sensitive analog currents are selectively routed and combined by the current steering and selection module 106 in response to a digital challenge signal received from the challenge input unit 104, and subsequently evaluated by the sense-amplifier-based evaluation unit 108. The sense-amplifier-based evaluation unit 108 converts the analog current differences into corresponding digital response bits, thereby producing stable and reproducible digital identifiers unique to the PUF device 100.
[0060] An advantage of the present invention is that the use of leakage and near-threshold current variations enables inherently low-power operation, as the PCG units 102 operate under low bias conditions with minimal current consumption. This significantly improves the energy efficiency of the PUF device 100 while preserving sufficient entropy for secure response generation. Furthermore, the differential current evaluation performed by the sense-amplifier-based evaluation unit 108 improves robustness against electrical noise, supply voltage fluctuations, and environmental variations.
[0061] Additionally, the present invention minimizes reliance on auxiliary circuitry, as the entropy source is derived directly from intrinsic device-level electrical characteristics of the PCG units 102. This reduces overall circuit complexity, silicon area, and implementation cost, while improving scalability and integration compatibility with existing semiconductor fabrication processes. Accordingly, the PUF device 100 provides a power-efficient, reliable, and robust hardware security primitive capable of generating unique digital identifiers, making it particularly suitable for energy-constrained and resource-limited electronic systems.
[0062] A common gate voltage is applied to the PCG units 102, with controlled variations introduced through the supply voltage. Each PCG unit 102 is designed to be nominally identical. However, unavoidable variations in threshold voltage, channel length, mobility, oxide thickness, and doping concentration result in slight differences in their electrical characteristics. These variations manifest as distinct current outputs for each PCG unit 102. Although both process-sensitive voltage generators and current generators were initially considered, the design was narrowed to current-based generation for simplicity, improved power efficiency, and enhanced sensitivity to process variations.
[0063] The current steering and selection module 106 serves as the second stage of the PUF. Based on the applied digital challenge, one or more of the PCG unit 102 output currents are selected, routed, and combined to generate two differential current values for comparison. This stage incorporates a plurality of switching devices and current mirrors to steer currents. In addition to providing programmability of CRPs, the module includes tuning capability to calibrate or compensate for device mismatches, aging effects, or environmental deviations.
[0064] The sense-amplifier-based evaluation unit 108 constitutes the final stage of the PUF. The evaluation unit 108 compares the combined currents routed by the current steering and selection module 106 and produces a corresponding digital response bit. The comparative output reflects the unique combination of selected PCG units 102 based on the challenge and the inherent manufacturing variations within the currents generated. The sense-amplifier-based evaluation unit 108 converts these analog current differences into a stable digital logic value, forming the response bit.
[0065] The overall PUF architecture 100 leverages intrinsic semiconductor manufacturing randomness to generate unpredictable yet repeatable responses when stimulated with different challenges. This architecture enables reliable generation of CRPs that serve as the basis for secure authentication, cryptographic key derivation, and device identity. The design also enables performance evaluation across a range of parameters, including uniqueness, reliability, randomness, and power consumption, thus justifying the advantages of the current-based PUF approach.
[0066] According to another exemplary embodiment of the invention, FIG. 2 refers to a circuit-level implementation 200 of the current-based PUF device 100 is illustrated. The circuit is developed and simulated using LT-Spice, and the performance is validated using MATLAB post-processing. The individual circuit elements are assigned distinct reference numerals for clarity and consistency in description.
[0067] A gate-biasing voltage source 112 (Vg) is provided to supply a fixed DC bias voltage to the gate terminals of NMOS transistors M1 202 and M4 204 which form part of the process-sensitive current source branches. During simulations, the gate-bias voltage is varied across different operating points, including 0.7VDD, 0.8VDD, and 0.9VDD. In one example as shown in FIG. 2, the applied bias voltage is 1.08 V, corresponding to 0.9 × 1.2 V. The gate-bias voltage establishes the operating point of the M1 202 and the M4 204, thereby influencing the magnitude of generated process-sensitive currents.
[0068] The M1 202 and the M4 204, in combination with the gate-bias voltage, form core current-generating devices configured to operate in the saturation region to produce nominally constant current outputs. In one embodiment, each of the M1 202 and the M4 204 is dimensioned with a channel width W = 120 nm and channel length L = 100 nm. Due to inherent semiconductor manufacturing variations, the electrical characteristics of the M1 202 and the M4 204 deviate from one another, thereby causing current mismatch which contributes to the uniqueness of the PUF response.
[0069] A set of biasing voltage sources 118, including Vca1, Vcb1, Vca2, and Vcb2, is provided to supply fixed DC bias voltages to the gate terminals of NMOS transistors M9 206, M5 208, M8 210, and M6 212, respectively. In the illustrated embodiment, each of the bias voltage sources 118 is set to a nominal value of 1.2 V. These biasing voltages define the operating region of the respective NMOS transistors, enabling stable current flow for process-variation-dependent current generation.
[0070] The M9 206 and the M5 208 are arranged to form a first process-sensitive current branch, while NMOS transistors M8 210 and M6 212 form a second process-sensitive current branch. Each of the M9 206, the M5 208, the M8 210, and the M6 212 is sized with W = 120 nm and L = 100 nm to maintain structural symmetry. These transistors generate four distinct process-sensitive currents, respectively. Due to microscopic variations in doping concentration, threshold voltage, and mobility differences, the generated current levels vary uniquely across devices, providing entropy for PUF bit generation.
[0071] NMOS transistors M2 214 and M3 216 act as differential current-steering switches configured to route the generated currents based on an applied challenge signal. The challenge signal controls the conduction state of the M2 214 and the M3 216, thereby determining the current flow path between the output nodes. Accordingly, the steering mechanism selects and combines specific current branches to generate combined current outputs. The challenge-dependent steering performed by the M2 214 and the M3 216 forms the core mechanism for producing different Challenge-Response Pairs (CRPs) in the PUF device 100.
[0072] PMOS transistors M10 218, M11 220, M7 222, and M12 224 are arranged to form a cross-coupled latch-based sense-amplifier circuit forming part of the evaluation unit 108. This sense-amplifier-based evaluation unit 108 compares the combined current outputs 305 and 306 and employs positive feedback to amplify the differential current into a full-swing digital output. The sense-amplifier outputs are provided at output node SO and complementary output node SO_bar. The output at node represents the PUF response bit corresponding to the applied challenge signal, while the output at node is its logical inverse.
[0073] A supply voltage source 114 (VDD) provides the main operating voltage to the PUF circuit. In simulation analysis, the value of the supply voltage 114 is tested at different magnitudes, such as 1.2 V and 1.4 V, to analyze the supply sensitivity and robustness of the PUF output. The supply voltage source 114 powers all active transistors and circuit nodes associated with the PUF device 100.
[0074] A trigger voltage source 116 implemented as a piece-wise linear (PWL) source provides a time-dependent trigger signal to activate the sense-amplifier-based evaluation unit 108. The trigger voltage source 116 is configured with time-varying parameters including time [1] = 0 ns, value[1] = 0 V; time[2] = 10 ns, value[2] = 0 V; time[3] = 10.001 ns, value[3] = VDD; and time[4] = 20 ns, value[4] = VDD. When the trigger signal transitions low, the sense-amplifier-based evaluation unit 108 initiates current comparison and resolves the outputs at nodes to a stable state.
[0075] In summary, the circuit employs process-dependent current generation, challenge-dependent current steering, and latch-based current comparison to generate a stable digital PUF response. Each circuit component described herein contributes to the transformation of nanoscale semiconductor variations into robust and reproducible binary output values, suitable for secure device authentication.
[0076] According to another exemplary embodiment of the invention, FIG. 3 refers to a flowchart 300 a method of generating a unique PUF response in the low-power current-based physically unclonable function device 100. At step 302, the process-sensitive current outputs are generated using the PCG units 102. At step 304, a digital challenge signal is received by the challenge input unit 104. At step 306, the generated currents based on the received digital challenge are steered and combined by the current steering and selection module 106. At step 308, the sense-amplifier-based evaluation unit 108 is triggered for current evaluation and generating a digital response bit corresponding to a magnitude difference of the combined currents.
[0077] In one embodiment, a method is illustrated for designing, simulating, and evaluating the current-based Physically Unclonable Function (PUF) device 100. The flow diagram outlines the sequence of operations performed to verify the functionality, performance, and robustness of the PUF architecture under varying operating conditions. The method begins with constructing the current-based PUF circuit in an electronic design and simulation environment. In one example, the LT-Spice simulator is utilized for designing the circuit, configuring device parameters, and analyzing the resulting electrical waveforms. The PUF circuit 100 includes the process-sensitive current generator units 102, the challenge input unit 104, the current steering and selection module 106, the sense-amplifier-based evaluation unit 108, and the low-power trigger module 110. The initial step involves defining the transistor sizing, bias points, and interconnections necessary to implement the low-power current-based PUF architecture.
[0078] Once the circuit is constructed, transient simulation analysis is performed for a predefined time duration to observe the dynamic response of the PUF device 100. In one embodiment, a 100 ns transient simulation is carried out. During this phase, systematic variations are introduced in the gate bias voltage (Vg) and the supply voltage 114 (VDD) to assess the effect of these variations on the process-sensitive currents generated by the PCG units 102. The purpose of this step is to evaluate the PUF’s stability, sensitivity, and response behavior under different electrical biasing conditions.
[0079] The next stage of the method includes examining the output responses, current levels, and power dissipation for multiple challenge inputs applied through the challenge input unit 104. For each challenge, the behavior of the current steering and selection module 106 is observed, along with the digital output produced by the sense-amplifier-based evaluation unit 108. The current consumption and energy usage of the circuit are analyzed to confirm its suitability for ultra-low-power hardware security applications such as embedded systems, IoT nodes, and RFID devices. Finally, the performance parameters obtained for each challenge are analyzed to evaluate the effectiveness of the PUF device 100. Key performance metrics observed include uniqueness of responses across devices, repeatability of responses on the same device, randomness, and robustness against variations in Vg and VDD. Based on these observations, the performance characteristics of the current-based PUF architecture are concluded.
[0080] According to another exemplary embodiment of the invention, FIG. 4 refers to a graphical comparison 400 of the power consumption of different Physically Unclonable Function (PUF) types is illustrated. The FIG. 4 compares three conventional PUF architectures—namely Ring Oscillator-based PUFs, SRAM-based PUFs, and Delay-based PUFs—with the proposed current-based PUF device 100. The comparison is presented on a logarithmic scale to clearly highlight the difference in power consumption across the various PUF types.
[0081] The power consumption of the Ring Oscillator PUF is shown to be relatively high, typically in the order of hundreds of nanowatts. This elevated consumption arises from the continuous oscillation of multiple ring oscillator stages required to generate a stable response, resulting in dynamic power dissipation even when the PUF is not actively being queried. Similarly, the SRAM-based PUF demonstrates high power consumption, also in the range of several hundred nanowatts. SRAM PUFs require powering up memory cells to allow the metastability effect to produce a response at start-up. Further, repeated invocation or refresh cycles cause additional power usage, making SRAM PUFs less suitable for low-power or battery-constrained environments.
[0082] The Delay-based PUF, which relies on differences in propagation delay across matched routing paths or logic stages, exhibits a power consumption level comparable to Ring Oscillator and SRAM PUFs. Despite not constantly oscillating, delay-based PUFs require precise timing measurement circuitry that contributes to non-negligible static and dynamic power overheads. In contrast, the proposed current-based PUF device 100 demonstrates a significantly lower power consumption, at least one order of magnitude lower than the conventional PUF architectures shown in FIG. 4. The proposed design consumes power in the low nanowatt range due to its current-mode operation, sub-threshold biasing of transistors, and the activation of the sense-amplifier-based evaluation unit 108 only during the response generation interval. This enables ultra-low power operation suitable for passive or semi-passive devices, including IoT nodes, RFID tags, and on-chip hardware security modules with limited power budgets.
[0083] FIG. 4 clearly highlights the advantage of the proposed PUF design 100 in achieving extremely low power consumption, making it well-suited for resource-constrained and energy-harvesting-based secure hardware applications.
[0084] Table 1:
PUF Type Power Consumption Stability Uniqueness Design Complexity
Ring Oscillator PUF High Medium High High
SRAM PUF Medium High Medium Medium
Delay-Based PUF Medium Medium High Medium
Proposed PUF 100 Low Medium High Low

[0085] Further, the influence of the supply voltage (VDD) and the gate bias voltage (VG) are examined on the output characteristics of the proposed PUF circuit. The simulations were conducted across a range of voltage conditions to emulate realistic operational fluctuations that may occur due to environmental or system-level variations. Evaluating the PUF’s sensitivity to such variations is essential to ensure consistent performance, reliability, and predictability under non-ideal operating conditions.
[0086] The simulation outcomes establish a clear dependency between VDD, VG, and the resultant differential branch currents (Ia and Ib). As anticipated, an increase in either VDD or VG results in a proportional rise in the current magnitudes. However, the degree of influence is not uniform—VDD and VG impact Ia and Ib differently, which directly affects the strength of the differential current and, consequently, the bit decision boundary of the PUF. The applied challenge inputs serve as the key differentiating factor, as they steer the current through different branches, causing measurable variations in Ia and Ib. This behavior is central to the uniqueness and randomness of the PUF output, making it critical to analyze current sensitivity at various voltage levels.
[0087] To facilitate a clear comparison, the simulation results for various combinations of VDD and VG are presented in the following tables and plots. These visualizations enable direct observation of current variations and their corresponding impact on the stability of the output bit (SO) across the tested voltage ranges.
[0088] Table 2
Vca1 Vcb1 Vca2 Vcb2 Ia Ib SO SO̅ I(VDD) Power
0 0 0 0 14.7 pA 14.7 pA 1 1 9.8 pA 11.5 pW
0 0 0 1 9.7 pA 4.8 µA 0 1 4.8 µA 5.76 µW
0 0 1 0 4.8 µA 9.7 pA 1 0 4.8 µA 5.76 µW
0 0 1 1 3.0 µA 3.0 µA 1 1 6.1 µA 7.32 µW
0 1 0 0 9.0 pA 4.8 µA 0 1 4.8 µA 5.76 µW
0 1 0 1 9.0 pA 7.2 µA 0 1 7.2 µA 8.64 µW
0 1 1 0 4.2 µA 4.2 µA 1 1 8.5 µA 10.20 µW
0 1 1 1 3.18 µA 5.7 µA 0 1 8.9 µA 10.68 µW
1 0 0 0 4.8 µA 9.7 pA 1 0 4.8 µA 5.76 µW
1 0 0 1 4.2 µA 4.2 µA 1 1 8.5 µA 10.20 µW
1 0 1 0 7.2 µA 9.2 pA 1 0 7.2 µA 8.64 µW
1 0 1 1 5.7 µA 3.18 µA 1 0 8.9 µA 10.64 µW
1 1 0 0 3.0 µA 3.0 µA 1 1 6.17 µA 7.404 µW
1 1 0 1 5.7 µA 5.7 µA 0 1 8.9 µA 10.68 µW
1 1 1 0 3.1 µA 3.1 µA 1 0 8.9 µA 10.68 µW
1 1 1 1 4.7 µA 4.7 µA 1 1 9.5 µA 11.40 µW

[0089] Table 2 presents the measured results for an electronic circuit operating at a supply voltage (VDD) of 1.2V and a gate voltage (VG) of 0.84V. It shows how different combinations of four input signals (Vca1, Vcb1, Vca2, Vcb2) affect the circuit's behaviour. For each input state, the table records two internal currents (branch currents Ia, Ib) and two output logic states (SO, SO_bar). It also lists the total current drawn from the power supply, I(VDD). Lastly, the calculated power consumption for each input condition is also provided.
[0090] Table 3:
Vca1 Vcb1 Vca2 Vcb2 Ia Ib SO SO̅ I(Vdd) Power
0 0 0 0 12 pA 12 pA 1 1 9.63 pA 11.55 pW
0 0 0 1 11.9 pA 5.1 μA 0 1 5.11 μA 6.13 μW
0 0 1 0 5.1 pA 11.9 pA 1 0 5.11 μA 6.13 μW
0 0 1 1 3.38 μA 3.38 μA 1 1 6.7 μA 8.04 μW
0 1 0 0 11.9 pA 5.1 μA 0 1 5.1 μA 6.13 μW
0 1 0 1 9.2 pA 7.5 μA 0 1 7.5 μA 9 μW
0 1 1 0 4.4 μA 4.4 μA 1 1 8.9 μA 10.68 μW
0 1 1 1 3.3 μA 6.04 μA 0 1 9.4 μA 11.28 μW
1 0 0 0 5.1 μA 11.9 pA 1 0 5.1 μA 6.13 μW
1 0 0 1 4.48 μA 4.48 μA 1 1 8.9 μA 10.68 μW
1 0 1 0 7.5 μA 9.2 pA 1 0 7.5 μA 9 μW
1 0 1 1 6.04 μA 3.37 μA 1 0 9.4 μA 11.28 μW
1 1 0 0 3.3 μA 3.3 μA 1 1 6.7 μA 8.04 μW
1 1 0 1 3.3 μA 6.04 μA 0 1 9.4 μA 11.28 μW
1 1 1 0 6.04 μA 3.3 μA 1 0 9.4 μA 11.28 μW
1 1 1 1 5.07 μA 5.07 μA 1 1 10.15 μA 12.18 μW

[0091] Table 3 presents the measured results for an electronic circuit operating at a supply voltage (VDD) of 1.2V and a gate voltage (VG) of 0.96V. It shows how different combinations of four input signals (Vca1, Vcb1, Vca2, Vcb2) affect the circuit's behaviour. For each input state, the table records two internal currents (Ia, Ib) and two output logic states (SO, SO_bar). It also lists the total current drawn from the power supply, I(VDD). Lastly, the calculated power consumption for each input condition is also provided.
[0092] Table 4:
Vca1 Vcb1 Vca2 Vcb2 Ia Ib SO SO̅ I(Vdd) Power
0 0 0 0 20.7 pA 20.7 pA 1 1 9.62 pA 11.54 pW
0 0 0 1 6.14 pA 5.37 μA 0 1 5.3 μA 6.36 μW
0 0 1 0 5.37 μA 6.14 pA 1 0 5.3 μA 6.36 μW
0 0 1 1 3.62 μA 3.26 μA 1 1 7.2 μA 8.64 μW
0 1 0 0 6.14 pA 5.3 μA 0 1 5.37 μA 6.36 μW
0 1 0 1 9.26 pA 7.8 μA 0 1 7.8 μA 9.36 μW
0 1 1 0 4.65 μA 4.65 μA 1 1 9.3 μA 11.16 μW
0 1 1 1 3.5 μA 6.3 μA 0 1 9.8 μA 11.76 μW
1 0 0 0 5.37 μA 6.14 μA 1 0 5.3 μA 6.36 μW
1 0 0 1 4.65 μA 4.65 μA 1 1 9.3 μA 11.16 μW
1 0 1 0 7.8 μA 9.2 pA 1 0 7.8 μA 9.36 μW
1 0 1 1 6.3 μA 3.5 μA 1 0 9.8 μA 11.76 μW
1 1 0 0 3.6 μA 3.6 μA 1 1 7.2 μA 8.64 μW
1 1 0 1 3.5 μA 6.3 μA 0 1 9.8 μA 11.76 μW
1 1 1 0 6.3 μA 3.5 μA 1 0 9.8 μA 11.76 μW
1 1 1 1 5.3 μA 5.3 μA 1 1 10.6 μA 12.73 μW

[0093] Table 4 presents the measured results for an electronic circuit operating at a supply voltage (VDD) of 1.2V and a gate voltage (VG) of 1.08V. It shows how different combinations of four input signals (Vca1, Vcb1, Vca2, Vcb2) affect the circuit's behaviour. For each input state, the table records two internal currents (Ia, Ib) and two output logic states (SO, SO_bar). It also lists the total current drawn from the power supply, I(VDD). Lastly, the calculated power consumption for each input condition is also provided.
[0094] According to another exemplary embodiment of the invention, FIGs. 5A – 5C refer graphs (500, 502, 504) a variation of output currents Ia and Ib with respect to different challenge inputs for three gate voltage (Vg) conditions, while the supply voltage (Vdd) is fixed at 1.2 V. Each plot corresponds to a different Vg value: 0.84 V, 0.96 V, and 1.08 V. The x-axis represents the Challenge Index (from 1 to 16), and the y-axis represents the current magnitude in microamperes (µA).
[0095] Across all three graphs (500, 502, 504): Two current outputs, Ia (blue) and Ib (orange), are shown for each challenge value, highlighting how the challenge inputs influence current steering between the two branches. For every challenge index, either Ia or Ib dominates, demonstrating the differential nature of the PUF’s current response.
[0096] Referring to FIG. 5A, at lower gate bias (Vg = 0.84 V), both branch currents Ia and Ib show modest current levels, generally within the 0–7 µA range. The current switching behavior across challenges displays clear alternation between branch currents Ia and Ib for most challenge inputs, indicating sensitivity to challenge bits. Some challenge indices exhibit near-equal current values, suggesting lower differential separation at this bias level.
[0097] Referring to FIG. 5B, increasing Vg strengthens current drive (Vg = 0.96 V), leading to slightly higher current values on average compared to 0.84 V. The distinction between branch currents Ia and Ib becomes more pronounced for several challenge indices, improving output contrast.The alternating pattern of dominance between branch currents Ia and Ib persists, showing consistent challenge-dependent current steering.
[0098] Referring to FIG. 5C, with further increased Vg (Vg = 1.08 V), both output currents rise visibly, reaching up to approximately 7–8 µA. The current separation between branch currents Ia and Ib becomes more prominent for a majority of challenge inputs, enabling clearer bit differentiation. The higher gate voltage enhances overall transconductance, leading to stronger differential behavior.
[0099] FIGs. 5A – 5C display the relationship between two internal currents, Ia and Ib and a 'Challenge Index' ranging from 0 to 15. The Challenge Index likely corresponds to the 16 different input combinations shown in the previous table. The measurements were performed with a constant supply voltage (VDD) of 1.2V. The figure consists of three subplots, each illustrating the current behaviour under a different gate voltage (VG): 0.84V, 0.96V and 1.08V. The vertical axis represents the current magnitude in microamperes (µA). These plots visualize how variations in the gate voltage influence the circuit's current response (specifically branch currents Ia and Ib) to different operational challenges or input states.
[00100] According to another exemplary embodiment of the invention, FIG. 6 refers to a graph 600 that illustrates the digital output response (SO) of the current-source-based PUF for 16 different input challenge indices, where the supply voltage (Vdd) is fixed at 1.2 V and the gate voltage (Vg) is varied across 0.84 V, 0.96 V, and 1.08 V. The output alternates between ‘0’ and ‘1’ across different challenge indices, demonstrating that the PUF generates distinct binary responses based on the applied challenge. For most challenge inputs, the output is ‘1’, indicating a stronger current response from one branch over the other. Only specific challenge indices (such as 1, 4, 5, 7, and 13) result in an output of ‘0’, indicating the opposite branch current dominance. The plotted result represents a stable and consistent challenge–response behavior across the three Vg values, meaning that varying Vg does not alter the digital output, thus confirming reliability and robustness of the PUF output under gate voltage variation.
[00101] The above figure illustrates the digital output response (SO) of the PUF circuit for 16 different input challenge values, measured at a fixed supply voltage (VDD = 1.2 V). The resulting SO pattern remained identical for all the evaluated gate voltage (VG) values of 0.84 V, 0.96 V, and 1.08 V, indicating that the PUF output is stable and insensitive to VG variations within this range at VDD = 1.2 V.
[00102] The SO output bit is generated based on the comparative magnitudes of the differential branch currents and is defined as follows:

[00103] Table 5:
Vca1 Vcb1 Vca2 Vcb2 Ia Ib SO SO_bar I(Vdd) Power
0 0 0 0 15.3 pA 15.3 pA 1 1 11.2 pA 15.68 pW
0 0 0 1 12.9 pA 6.5 µA 0 1 6.5 µA 9.1 µW
0 0 1 0 6.5 µA 12.9 µA 1 0 6.5 µA 9.1 µW
0 0 1 1 4.2 µA 4.2 µA 1 1 8.4 µA 11.76 µW
0 1 0 0 12.9 pA 6.5 µA 0 1 6.5 µA 9.1 µW
0 1 0 1 12.1 pA 9.8 µA 0 1 9.8 µA 13.76 µW
0 1 1 0 5.7 µA 5.7 µA 1 1 11.5 µA 16.1 µW
0 1 1 1 4.3 µA 7.78 µA 0 1 12.1 µA 16.94 µW
1 0 0 0 6.5 µA 12.9 µA 1 0 6.5 µA 9.1 µW
1 0 0 1 5.7 µA 5.7 µA 1 1 11.5 µA 16.1 µW
1 0 1 0 9.8 µA 12.1 pA 1 0 9.8 µA 13.72 µW
1 0 1 1 7.7 µA 4.3 µA 1 0 12.1 µA 16.94 µW
1 1 0 0 4.2 µA 4.2 µA 1 1 8.4 µA 11.76 µW
1 1 0 1 4.3 µA 7.7 µA 1 1 12.1 µA 16.94 µW
1 1 1 0 7.7 µA 4.3 µA 1 0 12.1 µA 16.91 µW
1 1 1 1 6.5 µA 6.5 µA 1 1 13.0 µA 18.2 µW

[00104] Table 5 presents the measured results for an electronic circuit operating at a supply voltage (VDD) of 1.4V and a gate voltage (VG) of 0.98V. It shows how different combinations of four input signals (Vca1, Vcb1, Vca2, Vcb2) affect the circuit's behaviour. For each input state, the table records two internal currents (Ia, Ib) and two output logic states (SO, SO_bar). It also lists the total current drawn from the power supply, I(VDD). Lastly, the calculated power consumption for each input condition is also provided.
[00105] Table 6:
Vca1 Vcb1 Vca2 Vcb2 Ia Ib SO SO_bar I(Vdd) Power
0 0 0 0 21.9 pA 21.9 pA 1 1 11.2 pA 15.68 pW
0 0 0 1 15.8 µA 6.96 µA 0 1 6.9 µA 9.66 µW
0 0 1 0 6.96 µA 15.8 µA 1 0 6.9 µA 9.66 µW
0 0 1 1 4.6 µA 4.6 µA 1 1 9.2 µA 12.88 µW
0 1 0 0 15.8 pA 6.96 µA 0 1 6.9 µA 9.66 µW
0 1 0 1 12.2 pA 10.31 µA 0 1 10.31 µA 14.43 µW
0 1 1 0 6.0 µA 6.0 µA 1 1 12.1 µA 16.94 µW
0 1 1 1 4.95 µA 8.22 µA 0 1 12.8 µA 17.92 µW
1 0 0 0 6.96 µA 15.8 pA 1 0 6.96 µA 9.66 µW
1 0 0 1 6.0 µA 6.0 µA 1 1 12.1 µA 16.94 µW
1 0 1 0 10.3 µA 12.2 pA 1 0 10.31 µA 14.43 µW
1 0 1 1 8.2 µA 4.59 µA 1 0 12.8 µA 17.92 µW
1 1 0 0 4.6 µA 4.6 µA 1 1 9.2 µA 12.88 µW
1 1 0 1 4.6 µA 8.2 µA 0 1 12.8 µA 17.92 µW
1 1 1 0 8.2 µA 4.5 µA 1 0 12.8 µA 17.92 µW
1 1 1 1 6.91 µA 6.9 µA 1 1 13.8 µA 19.32 µW

[00106] Table 6 presents the measured results for an electronic circuit operating at a supply voltage (VDD) of 1.4V and a gate voltage (VG) of 1.12V. It shows how different combinations of four input signals (Vca1, Vcb1, Vca2, Vcb2) affect the circuit's behaviour. For each input state, the table records two internal currents (Ia, Ib) and two output logic states (SO, SO_bar). It also lists the total current drawn from the power supply, I(VDD). Lastly, the calculated power consumption for each input condition is also provided.
[00107] Table 7:
Vca1 Vcb1 Vca2 Vcb2 Ia Ib SO SO_bar I(Vdd) Power
0 0 0 0 27 pA 27 pA 1 1 11.2 pA 15.68 pW
0 0 0 1 7.8 pA 7.2 µA 0 1 7.3 µA 10.22 µW
0 0 1 0 7.2 µA 7.8 pA 1 0 7.3 µA 10.22 µW
0 0 1 1 4.9 µA 4.9 µA 1 1 9.8 µA 13.72 µW
0 1 0 0 7.8 pA 7.3 µA 0 1 7.3 µA 10.22 µW
0 1 0 1 12.2 pA 10.6 µA 0 1 10.6 µA 14.84 µW
0 1 1 0 6.3 µA 6.3 µA 1 1 12.6 µA 17.64 µW
0 1 1 1 4.8 µA 8.5 µA 0 1 13.3 µA 18.62 µW
1 0 0 0 7.2 µA 7.8 pA 1 0 7.3 µA 10.22 µW
1 0 0 1 6.3 µA 6.3 µA 1 1 12.6 µA 17.64 µW
1 0 1 0 10.6 µA 12.2 pA 1 0 10.6 µA 14.84 µW
1 0 1 1 8.5 µA 4.8 µA 1 0 13.3 µA 18.62 µW
1 1 0 0 9.8 µA 9.8 µA 1 1 9.8 µA 13.72 µW
1 1 0 1 4.8 µA 8.5 µA 0 1 13.3 µA 18.62 µW
1 1 1 0 8.5 µA 4.8 µA 1 0 13.3 µA 18.62 µW
1 1 1 1 7.2 µA 7.2 µA 1 1 14.4 µA 20.16 µW

[00108] Table 7 presents the measured results for an electronic circuit operating at a supply voltage (VDD) of 1.4V and a gate voltage (VG) of 1.26V. It shows how different combinations of four input signals (Vca1, Vcb1, Vca2, Vcb2) affect the circuit's behaviour. For each input state, the table records two internal currents (Ia, Ib) and two output logic states (SO, SO_bar). It also lists the total current drawn from the power supply, I(VDD). Lastly, the calculated power consumption for each input condition is also provided.
[00109] According to another exemplary embodiment of the invention, FIGs. 7A- 7C illustrates graphs (700,702,704) the variation of the differential branch currents Ia and Ib across 16 challenge indices for three different gate voltages (VG) while keeping the supply voltage constant at VDD = 1.4 V. The x-axis represents the Challenge Index (1 to 16), and the y-axis shows the corresponding current magnitude in microamperes (µA). Each plot compares the current responses of Ia (blue) and Ib (orange) for the same challenge vector, providing insight into the challenge-dependent behavior of the PUF.
[00110] Referring to FIG. 7A, VDD = 1.4 V, VG = 0.98 V. At this VG level, both branch currents Ia and Ib exhibit moderate current values in the range of ~0-8 µA. A distinct alternation between Ia-dominant and Ib-dominant responses is visible across challenges, indicating proper current steering behavior. Certain challenges exhibit narrow current separation, suggesting slightly weaker differential distinction at this VG.
[00111] Referring to FIG. 7B, VDD = 1.4 V, VG = 1.12 V. Increasing VG enhances the current drive strength, pushing current values higher compared to 0.98 V, with peaks reaching up to ~10 µA. The separation between branch currents Ia and Ib improves for several challenge indices, resulting in more robust decision margins for SO bit generation. The challenge-dependent alternation remains consistent, demonstrating stable PUF behavior at higher VG.
[00112] Referring to FIG. 7C, VDD = 1.4 V, VG = 1.26 V. Further increase in VG elevates the current magnitudes, with both branch currents Ia and Ib showing higher peak values. The differential gap between branch currents Ia and Ib becomes more pronounced for most challenges, enabling clearer and more reliable current-based bit decision. The outputs show strong sensitivity to challenge inputs, reinforcing the uniqueness property of the PUF.
[00113] FIGs. 7A – 7C displays the relationship between two internal currents, Ia and Ib, and a 'Challenge Index' ranging from 0 to 15. The Challenge Index likely corresponds to the 16 different input combinations shown in the previous table. The measurements were performed with a constant supply voltage (VDD) of 1.4V. The figure consists of three subplots, each illustrating the current behaviour under a different gate voltage (Vg): 0.98V, 1.12V (middle), and 1.26V (bottom). The vertical axis represents the current magnitude in microamperes (µA). These plots visualize how variations in the gate voltage influence the circuit's current response (specifically branch currents Ia and Ib) to different operational challenges or input states.
[00114] According to another exemplary embodiment of the invention, FIG. 8 refers to a graph 700 illustrates the relationship between the input challenge index (0–15) and the corresponding PUF output bit (SO) for a fixed supply voltage (VDD = 1.4 V) under three different gate bias voltages (VG = 0.98 V, 1.12 V, and 1.26 V). The output behavior remains stable and consistent across the varying VG values, indicating strong reliability of the PUF response under gate voltage variations. The SO output is binary (0 or 1), plotted on the y-axis, with the challenge index on the x-axis. For most challenge inputs, the output SO remains 1, while specific challenge indices produce 0. Output “0” is observed at challenge indices: 1, 4, 5, 7, and 13. The output pattern shows a distinct and reproducible response to challenge variations, reflecting good uniqueness in the PUF behavior. The consistent pattern across all VG values confirms that the PUF response remains unchanged with gate voltage variation, and the design achieves robustness and stability with respect to VG fluctuations.
[00115] FIG. 8 plots the digital output response (SO) of the PUF circuit against the 16 different input challenges. The measurements were taken with a fixed supply voltage (VDD) of 1.4V. Here resulting SO pattern was identical for the varying gate voltages (VG) tested: 0.98V, 1.12V and 1.26V. This demonstrates output stability across this VG range at VDD=1.4V. Crucially, the generation of the SO output follows the below equation:

[00116] According to another exemplary embodiment of the invention, FIG. 9A- 9B refers to graphs (900, 902) shows the power consumption. FIGs. 9A- 9B analyses the power consumption characteristics of the proposed Current-Based PUF circuit under varying operational conditions. Understanding power consumption is crucial not only for energy efficiency but also for assessing potential vulnerabilities to side-channel attacks. The analysis investigates the impact of supply voltage (Vdd), control gate voltage (Vg), and the specific applied input challenge on the overall power drawn by the circuit.
[00117] The power consumption was evaluated across all 16 possible input challenges (represented by decimal equivalents 0-15) for two different supply voltages: Vdd = 1.2V and Vdd = 1.4V. Within each Vdd setting, the gate voltage (Vg) was swept across three distinct values (i.e 0.7VDD,0.8VDD and 0.9VDD).
[00118] FIG. 9A refers to Power Consumption vs. Input Challenge at VDD = 1.2 V for VG = 0.84 V, 0.96 V, and 1.08 V. This plot 900 illustrates the variation in power consumption of the current-source-based PUF for all 16 input challenge combinations at a supply voltage of 1.2 V, measured across three different gate bias voltages (VG = 0.84 V, 0.96 V, and 1.08 V). The graph highlights the effect of gate voltage scaling on overall power usage and stability across challenge patterns.
[00119] FIG. 9B refers Average Power Consumption Comparison at VDD = 1.2 V Across Gate Voltages (VG = 0.84 V, 0.96 V, and 1.08 V). This figure 902 compares the average power consumed by the PUF for the full set of 16 input challenges at a supply voltage of 1.2 V, for different gate voltages. The graph 802 provides insight into how gate voltage tuning influences total energy efficiency and helps identify the optimum VG for low-power operation.
[00120] As illustrated in FIGs. 9A – 9B, at a supply voltage (VDD) of 1.2 V, the power consumption of the proposed current-based PUF varies noticeably with the applied input challenge and consistently increases with the gate voltage (VG). The maximum power recorded at VDD = 1.2 V increased from 11.4 µW at VG = 0.84 V to 12.18 µW at VG = 0.96 V, and further to 12.72 µW at VG = 1.08 V, with the highest consumption typically observed for larger challenge indices. When the supply voltage was raised to VDD = 1.4 V, a clear rise in overall power consumption was observed while preserving the same challenge-dependent characteristics and the monotonic increase with VG. Under these conditions, the maximum power measured was 18.2 µW at VG = 0.98 V, 19.32 µW at VG = 1.12 V, and 20.16 µW at VG = 1.26 V. These results confirm that both the input challenge and the selection of VDD and VG significantly influence the circuit’s power profile, offering valuable insight for performance optimization, energy-aware design, and potential side-channel leakage analysis.
[00121] The simulation outcomes verify the functional correctness of the current-based PUF. Consumption Trend: Power consumption varies across input challenges and operating voltages, with a consistent increasing trend for higher VDD and VG values. The maximum power recorded was approximately 12.7 µW at VDD = 1.2 V and 20.2 µW at VDD = 1.4 V, demonstrating the design’s suitability for low-power applications. Current Sensitivity: The internal branch currents (Ia and Ib) showed expected sensitivity to both the input challenge vector and the selected operating voltages, confirming proper current steering behavior. Output Robustness: The digital output (SO) remained functionally stable over all tested gate voltage levels for both VDD = 1.2 V and VDD = 1.4 V, indicating strong robustness of the PUF response against VG variations.
[00122] Numerous advantages of the present disclosure may be apparent from the discussion above. In accordance with the present disclosure, current-based physical unclonable functions (PUFs) that exploit semiconductor process variations to generate unique, device-specific responses for secure authentication and cryptographic key generation.
[00123] The low-power current-based Physically Unclonable Function (PUF) 100 that enables secure and reliable hardware authentication using inherent semiconductor process variations. The PUF device 100 reduces power consumption by utilizing subthreshold leakage currents and an automatic current cut-off mechanism, making the PUF suitable for battery-powered and passive devices. The PUF device 100 enhances response stability and repeatability across variations in supply voltage, gate bias voltage, and environmental operating conditions such as temperature. The PUF device 100 improves uniqueness and randomness of the generated challenge–response pairs (CRPs) by leveraging sensitive current differentials derived from transistor-level mismatches. The PUF device 100 minimizes circuit complexity and area overhead by employing a simplified current-steering architecture that can be easily integrated into existing IC designs.
[00124] The PUF device 100 provides scalability in the challenge space, supporting a strong PUF implementation capable of resisting machine learning-based modeling or prediction attacks. The PUF device 100 enables flexible mixed-signal integration allowing seamless deployment of the PUF within analog, digital, and RF security modules in System-on-Chip (SoC) environments.
[00125] The PUF device 100 that employs a plurality of process-sensitive current generator (PCG) units 102 configured to produce uniquely varying current outputs arising from inherent semiconductor process variations. A challenge-controlled current steering module 106 selectively routes the generated currents in accordance with applied challenge bits, thereby producing distinct current differentials for different challenge inputs. A sense-amplifier-based evaluation unit 108 converts the resulting current imbalance into a corresponding digital response bit, enabling secure hardware authentication. The proposed architecture operates in a current-mode, utilizes sub-threshold biasing, and achieves ultra-low power consumption in the range of 12.7 µW to 20.2 µW across a supply voltage range of 1.2 V to 1.4 V, making it highly suitable for resource-constrained security applications.
[00126] The PUF device 100 utilizes process-sensitive current differentials and selective activation mechanisms to significantly reduce power consumption, improve stability, and enhance overall hardware security performance.
[00127] It will readily be apparent that numerous modifications and alterations can be made to the processes described in the foregoing examples without departing from the principles underlying the invention, and all such modifications and alterations are intended to be embraced by this application.
, Claims:CLAIMS:
I / We Claim:
1. A low-power current-based physically unclonable function (PUF) device (100), comprising:
plurality of process-sensitive current generator (PCG) units (102), wherein each of the PCG unit (102) comprises a MOSFET-based current source biased to operate in a subthreshold or near-threshold region and sharing common biasing conditions including a gate bias voltage (VG),
wherein the plurality of PCG units (102) are nominally identical in structure and are configured to generate mutually variant output currents under identical biasing conditions due to inherent semiconductor fabrication process variations;
at least one challenge input unit (104) configured to receive a digital challenge signal;
a current steering and selection module (106) operatively coupled to the plurality of PCG units (102) and to the challenge input unit (104),
wherein the current steering and selection module (106) comprises a plurality of transistor-based switching elements configured to selectively route, mirror, and combine output currents of selected PCG units (102) in accordance with the received digital challenge signal so as to form differential current paths;
a sense-amplifier-based evaluation unit (108) operatively coupled to the current steering and selection module (106), wherein the sense-amplifier-based evaluation unit (108) comprises a regenerative cross-coupled latch configured to compare the differential current paths and generate a corresponding digital response bit based on a polarity of current difference; and
a low-power trigger module (110) configured to activate the sense-amplifier-based evaluation unit (108) only during response evaluation,
wherein the digital response bit is derived from process-sensitive current differentials generated by the plurality of PCG units (102) and is reproducible for a given digital challenge under identical operating conditions,
wherein the PCG units (102) operate in a subthreshold or near-threshold region such that the low-power current-based PUF device (100) exhibits a total power consumption between 12.7 µW and 20.2 µW across a supply voltage range of 1.2 V to 1.4 V.
2. The low-power current-based PUF device (100) as claimed in claim 1, wherein each of the PCG unit (102) comprises an NMOS transistor structure configured with identical channel geometry and biased using a common gate bias voltage (VG), and wherein the PCG units (102) are configured to generate output currents that differ from one another under identical biasing conditions due to variations in threshold voltage, carrier mobility, oxide thickness, channel dimensions, or doping concentration.
3. The low-power current-based PUF device (100) as claimed in claim 1, wherein the current steering and selection module (106) comprises current mirror structures and transistor-based switching elements configured to implement challenge-dependent differential current routing, and wherein the current steering and selection module (106) further comprises a tuning input configured to adjust bias conditions to compensate for environmental variations including temperature fluctuations, supply voltage variations, and aging effects.
4. The low-power current-based PUF device (100) as claimed in claim 1, wherein the sense-amplifier-based evaluation unit (108) is configured to amplify small current differences into a stable full-swing digital output using positive feedback of the cross-coupled latch.
5. The low-power current-based PUF device (100) as claimed in claim 1, wherein the low-power trigger module (110) comprises a pulse-based activation circuit configured to switch the sense-amplifier-based evaluation unit (108) ON only during a comparison interval to minimize static power consumption.
6. The low-power current-based PUF device (100) as claimed in claim 1, wherein the low-power current-based PUF device (100) is configured to exhibit reproducible digital response output under ±10% variation of supply voltage and gate bias voltage within the operational range.
7. The low-power current-based PUF device (100) as claimed in claim 1, wherein the plurality of PCG units (102) comprise at least four PCG units configured to generate differential current pairs in response to different digital challenges.
8. The low-power current-based PUF device (100) as claimed in claim 1, wherein the digital response bit is usable for cryptographic key generation, authentication, device identity verification, or secure boot of an electronic system.
9. A method of generating a unique PUF response in a low-power current-based physically unclonable function (PUF) device (100), comprising:
generating plurality of process-sensitive current outputs using plurality of process-sensitive current generator (PCG) units (102);
receiving a digital challenge signal by at least one challenge input unit (104);
steering and combining the generated currents based on the received digital challenge by a current steering and selection module (106); and
triggering a sense-amplifier-based evaluation unit (108) for current evaluation and generating a digital response bit corresponding to a magnitude difference of the combined currents.