1. A ferroelectric-oxide engineered gallium nitride (GaN) metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) device 100, the device (100) comprising: a substrate (102) of a pre-defined thickness and configured to transfer heat; a nucleation layer (104) of a pre-defined thickness and configured to reduce the leakage disposed over the substrate (102); a buffer layer (106) of a pre-defined thickness and configured to offer a higher breakdown strength and better heat control disposed over the nucleation layer (104); a channel layer (108) of a pre-defined thickness disposed over the buffer layer (106); a barrier layer (110) disposed over the channel layer (108), the barrier layer (110) having a pre-defined thickness and forming a two-dimensional electron gas (2DEG) at the interface between the channel layer (108) and the barrier layer (110); a gate stack (120) disposed over the barrier layer (110), the gate stack (120) further comprises: an interfacial dielectric layer (112) of pre-defined thickness in contact with the barrier layer (110); a ferroelectric oxide layer (114) of pre-defined thickness disposed over the interfacial dielectric layer (112); a gate electrode (116) disposed over the ferroelectric oxide layer (114), and a passivation layer (118) configured to thermal stability over regions of the device, wherein the device (100) is configured to operate in normally-off mode and exhibits a subthreshold swing of less than 60 mV/decade at room temperature.

2. The device (100) as claimed in claim 1, wherein the substrate (102) comprises silicon carbide (SiC) and the pre-defined thickness lies in the range of 3-7 µm.

3. The device (100) as claimed in claim 1, wherein the nucleation layer (104) comprises AlN and the pre-defined thickness lies in the range of 100-300 nm.

4. The device (100) as claimed in claim 1, wherein the buffer layer (106) comprises β-Ga₂O₃ and the pre-defined thickness lies in the range of 100-500 nm and is configured to enhance breakdown voltage and thermal conductivity compared to conventional GaN buffer layers.

5. The device (100) as claimed in claim 1, wherein the channel layer (108) comprises GaN and the pre-defined thickness lies in the range of 100-500 nm.

6. The device (100) as claimed in claim 1, wherein the barrier layer (110) comprises AlGaN and the pre-defined thickness lies in the range of 10-50 nm.

7. The device (100) as claimed in claim 1, wherein the interfacial dielectric layer (112) comprises at least one material selected from Al₂O₃ and hexagonal boron nitride (h-BN) and the pre-defined thickness lies in the range of 1-5 nm.

8. The device (100) as claimed in claim 1, wherein the ferroelectric oxide layer (114) has a thickness in the range of 2-7 nm and is configured to operate in a negative capacitance regime to enable the subthreshold swing of less than 60 mV/decade.

9. The device (100) as claimed in claim 1, further comprising a silicon nitride (Si₃N₄) passivation layer (118) covering regions surrounding the T-gate electrode (116) and access areas between the gate and source/drain electrodes.

10. A method (200) for fabricating a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device (100), the method (200) comprising: forming an AlN nucleation layer (104) over a SiC substrate layer (102); forming a β-Ga₂O₃ buffer layer (106) over the AlN nucleation layer (104); growing a GaN channel layer (108) over the β-Ga₂O₃ buffer layer (106); forming an AlGaN barrier layer (110) over the GaN channel layer (108) to induce a two-dimensional electron gas (2DEG); depositing an interfacial dielectric layer (112) over the AlGaN barrier layer (110), the interfacial dielectric layer (112) comprising at least one of Al₂O₃ and hexagonal boron nitride (h-BN); depositing a ferroelectric hafnium zirconium oxide (Hf₁₋ₓZrₓO₂) layer (114) over the interfacial dielectric layer (112); performing thermal annealing to stabilize an orthorhombic ferroelectric phase in the Hf₁₋ₓZrₓO₂ layer (114); forming a gate electrode (116) over the ferroelectric oxide layer (114); and depositing a passivation layer (118) over regions of the device, wherein the resulting device (100) is configured to operate in normally-off mode and exhibits a subthreshold swing of less than 60 mV/decade at room temperature.

Description:FIELD OF DISCLOSURE
[0001] The present disclosure generally relates to metal-oxide-semiconductor high electron mobility transistor (MOSHEMT). More specifically, it relates to a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor.
BACKGROUND OF THE DISCLOSURE
[0002] Gallium nitride-based high electron mobility transistors (HEMTs) and their metal-oxide-semiconductor (MOSHEMT) variants have attracted significant attention due to their superior material properties, including high electron mobility, large critical electric field strength, and wide bandgap, which enable high breakdown voltage, high switching frequency, and high power density compared to silicon-based devices. These characteristics make gallium nitride (GaN) transistors promising candidates for next-generation power electronics, RF/mm-wave systems, and energy-efficient logic circuits.
[0003] However, conventional gallium nitride-based high electron mobility transistors (HEMTs) and MOSHEMTs face several persistent challenges that limit their widespread adoption and reliable performance: First, most as-grown AlGaN/GaN heterostructures exhibit a normally-on (depletion-mode) characteristic due to the presence of a high-density two-dimensional electron gas (2DEG) induced by spontaneous and piezoelectric polarization. Second, conventional gate structures, including Schottky gates, p-GaN gates, and metal-insulator-semiconductor (MIS) gates using dielectrics such as Al2O3, AlN, SiN, or SiO₂, suffer from : High interface trap density (Dit) at the oxide/semiconductor interface; Subthreshold swing limited to approximately 60 mV/decade at room temperature; Excessive gate leakage current. And Third, buffer-related limitations further degrade performance. Conventional GaN buffers grown on foreign substrates often contain high densities of threading dislocations and carbon-related deep traps, resulting in buffer leakage, reduced breakdown voltage, and poor thermal management under high-power operation.
[0004] At present, technologies are incapable, therefore, of ensuring at once the desired accuracy of threshold voltage Vth control and tunability, reduced leakage, thermal robustness, and durability of operation, which is the critical shortcoming that the proposed invention ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor (GaN MOSHEMT) meets.
[0005] The present invention offers a range of significant advantages that overcome the limitations of traditional gallium nitride-based devices by developing a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor (GaN MOSHEMT) with integrated threshold voltage control and enhanced stability. It allows for stable and tunable threshold voltage with minimal hysteresis, early suppression of interface traps and current collapse, and improved long-term reliability under high electric field and temperature stress. In addition to superior gate control through negative capacitance operation, the present invention significantly reduces gate leakage, enhances breakdown voltage, and provides better thermal robustness compared to conventional p-GaN, MIS-HEMT, or standard-buffer gallium nitride devices. Further, the present invention delivers detailed improvements in switching efficiency, power handling, and device durability, thereby promoting higher performance, greater reliability, reduced power.
[0006] Accordingly, there remains a significant need for an improved ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor that overcomes the aforementioned limitations through synergistic integration of advanced gate dielectric and buffer engineering, thereby enabling more stable, efficient, and reliable device operation.
SUMMARY OF THE DISCLOSURE
[0007] The following is a summary description of illustrative embodiments of the invention. It is provided as a preface to assist those skilled in the art to more rapidly assimilate the detailed design discussion which ensues and is not intended in any way to limit the scope of the claims which are appended hereto in order to particularly point out the invention.
[0008] According to illustrative embodiments, the present disclosure focuses on a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor which overcomes the above-mentioned disadvantages or provides users with a useful or commercial choice.
[0009] An objective of the present disclosure is to develop a gallium nitride based metal-oxide-semiconductor high electron mobility transistor (GaN MOSHEMT) capable of stable normally-off operation with significantly improved threshold voltage control.
[0010] Another objective of the present disclosure is to achieve a subthreshold swing.
[0011] Another objective of the present disclosure is to provide a device structure that simultaneously minimizes interface trap density, gate leakage current, and current collapse effects.
[0012] Another objective of the present disclosure is to enhance off-state breakdown voltage and long-term reliability under high electric field and elevated temperature stress.
[0013] Another objective of the present disclosure is to incorporate an ultra-wide-bandgap buffer layer to suppress buffer-related trapping and improve thermal robustness.
[0014] Another objective of the present disclosure is to enable dynamic threshold voltage tunability while maintaining minimal hysteresis after repeated switching cycles.
[0015] Another objective of the present disclosure is to utilize a hafnium zirconium oxide layer engineered to maintain a stable orthorhombic phase, ensuring consistent negative capacitance operation.
[0016] Another objective of the present disclosure is to employ a specialized interfacial dielectric layer to act as a diffusion barrier and passivate dangling bonds at the AlGaN/gate interface.
[0017] Another objective of the present disclosure is to provide a high-performance semiconductor architecture that remains commercially feasible by utilizing a β-Ga2O3 buffer to achieve breakdown strengths comparable to more expensive substrates like GaN-on-diamond.
[0018] Yet another objective of the present disclosure is to offer a holistic solution that integrates ferroelectric gate engineering with advanced buffer design, thereby improving overall performance, efficiency, and reliability for next-generation power electronics, RF amplification, and low-power logic applications.
[0019] In light of the above, in one aspect of the present disclosure, a gallium nitride (GaN)-based metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) is disclosed herein. The transistor comprises a substrate, a buffer layer disposed over the substrate and comprising β-Ga₂O₃, a GaN channel layer disposed over the buffer layer, an AlGaN barrier layer disposed over the GaN channel layer forming a two-dimensional electron gas (2DEG) at the interface, a gate stack disposed over the AlGaN barrier layer, the gate stack comprising an interfacial dielectric layer in contact with the AlGaN barrier layer and a ferroelectric oxide layer disposed over the interfacial dielectric layer, the ferroelectric oxide layer comprising hafnium zirconium oxide (Hf₁₋ₓZrₓO₂), and a gate electrode disposed over the ferroelectric oxide layer, wherein the transistor is configured to operate in normally-off mode and exhibits a subthreshold swing of less than 60 mV/decade at room temperature.
[0020] In one embodiment, the substrate comprises silicon carbide (SiC) and the pre-defined thickness lies in the range of 3-7 µm.
[0021] In one embodiment, the nucleation layer comprises AlN and the pre-defined thickness lies in the range of 100-300 nm.
[0022] In one embodiment, the buffer layer comprises β-Ga₂O₃ and the pre-defined thickness lies in the range of 100-500 nm.
[0023] In one embodiment, the channel layer comprises GaN and the pre-defined thickness lies in the range of 100-500 nm.
[0024] In one embodiment, the barrier layer comprises AlGaN and the pre-defined thickness lies in the range of 10-50 nm.
[0025] In one embodiment, the interfacial dielectric layer comprises at least one material selected from Al₂O₃ and hexagonal boron nitride (h-BN) and the pre-defined thickness lies in the range of 1-5 nm.
[0026] In one embodiment, the ferroelectric oxide layer has a thickness in the range of 2-7 nm.
[0027] In one embodiment, the passivation layer comprises silicon nitride.
[0028] In light of the above, in one aspect of the present disclosure, a method of fabricating a ferroelectric-oxide engineered GaN MOSHEMT is disclosed herein. The method comprises forming an AlN nucleation layer over a SiC substrate, forming a β-Ga₂O₃ buffer layer over the AlN nucleation layer, growing a GaN channel layer over the β-Ga₂O₃ buffer layer, forming an AlGaN barrier layer over the GaN channel layer to induce a two-dimensional electron gas (2DEG), depositing an interfacial dielectric layer over the AlGaN barrier layer, depositing a ferroelectric Hf₁₋ₓZrₓO₂ layer over the interfacial dielectric layer, performing thermal annealing to stabilize the ferroelectric orthorhombic phase in the Hf₁₋ₓZrₓO₂ layer, forming a T-gate electrode over the ferroelectric layer, and depositing a silicon nitride passivation layer over selected regions of the device, wherein the resulting transistor is configured to provide normally-off operation with subthreshold swing below 60 mV/decade.
[0029] These and other advantages will be apparent from the present application of the embodiments described herein.
[0030] The preceding is a simplified summary to provide an understanding of some embodiments of the present invention. This summary is neither an extensive nor exhaustive overview of the present invention and its various embodiments. The summary presents selected concepts of the embodiments of the present invention in a simplified form as an introduction to the more detailed description presented below. As will be appreciated, other embodiments of the present invention are possible utilizing, alone or in combination, one or more of the features set forth above or described in detail below.
[0031] These elements, together with the other aspects of the present disclosure and various features are pointed out with particularity in the claims annexed hereto and form a part of the present disclosure. For a better understanding of the present disclosure, its operating advantages, and the specified object attained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated exemplary embodiments of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] To describe the technical solutions in the embodiments of the present disclosure or in the prior art more clearly, the following briefly describes the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description merely show some embodiments of the present disclosure, and a person of ordinary skill in the art can derive other implementations from these accompanying drawings without creative efforts. All of the embodiments or the implementations shall fall within the protection scope of the present disclosure.
[0033] The advantages and features of the present disclosure will become better understood with reference to the following detailed description taken in conjunction with the accompanying drawing, in which:
[0034] FIG. 1 illustrates a block diagram of a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device in accordance with an embodiment of the present disclosure; and
[0035] FIG. 2 illustrates a flow chart of a method, outlining the sequential steps for fabricating a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device in accordance with an embodiment of the present disclosure.
[0036] Like reference, numerals refer to like parts throughout the description of several views of the drawing.
[0037] The ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device is illustrated in the accompanying drawings, which like reference letters indicate corresponding parts in the various figures. It should be noted that the accompanying figure is intended to present illustrations of exemplary embodiments of the present disclosure. This figure is not intended to limit the scope of the present disclosure. It should also be noted that the accompanying figure is not necessarily drawn to scale.
DETAILED DESCRIPTION OF THE DISCLOSURE
[0038] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure.
[0039] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without some of these specific details.
[0040] Various terms as used herein are shown below. To the extent a term is used, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0041] The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.
[0042] The terms “having”, “comprising”, “including”, and variations thereof signify the presence of a component.
[0043] Referring now to FIG. 1 to FIG. 2 to describe various exemplary embodiments of the present disclosure. FIG. 1 illustrates a block diagram of a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device 100, in accordance with an embodiment of the present disclosure.
[0044] The device 100 comprises a substrate 102, a nucleation layer 104, a buffer layer 106, a channel layer 108, a barrier layer 110 and a gate stack 120. The gate stack 120 further comprises an interfacial layer 112, a ferroelectric layer 114, a gate electrode 116 and a passivation layer 118.
[0045] The substrate of a pre-defined thickness is configured to transfer heat. In the preferred embodiment, the substrate 102 comprises silicon carbide (SiC) and the thickness lies in the range of 3-7 µm. Silicon carbide acts like a highly efficient heat sink for the transistor. When the device 100 operates, the silicon carbide substrate 102 generates heat during switching and conduction by quickly drawing heat away from the active layers above it and dispersing it effectively. Unlike conventional silicon substrates that start degrading at high temperatures, the silicon carbide substrate 102 remains stable and functional even at those temperatures. The silicon carbide substrate 102 provides a rigid, stable foundation that doesn't warp, crack, or deform easily during high-temperature processing steps or during actual device operation so the layers grown on top maintain their precise alignment and properties over the device's 100 lifetime.
[0046] The nucleation layer 104 of a pre-defined thickness is configured to reduce the leakage disposed over the substrate 102. In the preferred embodiment, the nucleation layer 104 comprises AlN and the thickness lies in the range of 100-300 nanometers. The AlN nucleation layer 104 acts as a transition zone or buffer between the substrate 102 and the layers above. The nucleation layer 104 helps accommodate the lattice mismatch gradually, reducing the formation of defects like dislocations and cracks that would otherwise propagate upward and degrade device performance.
[0047] The buffer layer 106 of a pre-defined thickness is configured to offer a higher breakdown strength and better heat control disposed over the nucleation layer 104. In the preferred embodiment, the buffer layer 106 comprises beta-phase gallium oxide (β-Ga₂O₃) with a thickness in range of 100-500 nanometers. The incorporation of beta-phase gallium oxide as the buffer material represents a significant innovation over conventional GaN or AlGaN buffer structures. Beta-gallium oxide exhibits an ultra-wide bandgap approximately larger than gallium nitride which enables higher breakdown voltages and enhanced blocking capability. Additionally, beta-phase gallium oxide provides improved thermal conductivity compared to traditional buffer materials. The buffer layer 106 serves to further reduce threading dislocation density, provide strain management, enhance breakdown voltage through its wide bandgap, and improve overall device thermal performance.
[0048] The channel layer 108 of a pre-defined thickness is disposed over the buffer layer 106. In the preferred embodiment, the channel layer 108 comprises GaN and the thickness lies in the range of 100-500 nanometers. The GaN channel layer 108 is where electrons flow when the device 100 is turned on. When voltage is applied to a gate 116, electrons travel through the channel layer 108 from the source to the drain, allowing the device 100 to conduct electricity and perform its switching or amplification functions. Within the preferred embodiment, at its upper interface, the two-dimensional electron gas (2DEG) is formed when a barrier layer 110 is subsequently deposited. The 2DEG serves as the primary conduction channel of the HEMT device, exhibiting high electron mobility.
[0049] The barrier layer 110 of a pre-defined thickness is formed over the channel layer 108. In the preferred embodiment, the barrier layer 110 comprises aluminum gallium nitride (AlGaN) and the thickness lies in the range of 10-50 nanometers. The AlGaN barrier layer 110 acts as an insulating barrier that prevents electrons from escaping upward toward the gate. It confines the conducting electrons to the GaN channel region where they're needed. Without this barrier layer 110, electrons would spread out randomly, reducing current density and device efficiency. Additionally, the AlGaN/GaN heterojunction creates strong piezoelectric and spontaneous polarization fields that induce the formation of a high-density 2DEG at the interface, even without intentional doping. The thickness and composition of the barrier layer 110 are carefully optimized to maximize 2DEG density while maintaining good gate control and minimizing gate leakage.
[0050] The interfacial layer 112 of a pre-defined thickness is deposited over the barrier layer 110 in regions where the gate electrode is subsequently formed. In the preferred embodiment, the interfacial layer 112 comprises one of hexagonal boron nitride (h-BN) or Al₂O₃ and the thickness lies in the range of 1-5 nanometers. The interfacial layer 112 serves several critical functions in the device 100 operation. The interfacial layer 112 provides a high-quality interface with minimal trap density, reducing threshold voltage hysteresis and improving device stability. The interfacial layer 112 acts as a barrier to prevent direct contact between the ferroelectric oxide and the AlGaN barrier, which could otherwise lead to interface degradation and increased leakage. When Al₂O₃ is employed, it provides excellent dielectric properties and chemical stability.
[0051] The ferroelectric layer 114 is formed over the interfacial layer 112 of a pre-defined thickness. In the preferred embodiment the ferroelectric layer 114 comprises hafnium zirconium oxide with the chemical formula Hf₁₋ₓZrₓO₂ and the thickness lies in the range of 2-7 nanometers. The ferroelectric layer 114 represents the key innovation that enables negative capacitance operation and sub-60 mV/dec subthreshold swing. Following deposition, a critical annealing step is performed to stabilize the orthorhombic phase of the material, which exhibits ferroelectric behavior. One of the biggest challenges with GaN transistors is that they're typically normally-on (depletion mode), conducting current even with zero gate voltage, which is dangerous for power electronics. The ferroelectric layer 114 solves this by being programmed with polarization pointing away from the channel, which depletes the 2DEG and keeps the device 100, off at zero gate voltage.
[0052] The gate electrode 116 is formed over the ferroelectric layer 114. In the preferred embodiment, the gate electrode 116 comprises a T-gate electrode of metallic compound selected for appropriate work function and good adhesion to the underlying oxide stack. The gate electrode 116 is essentially the switch that turns the device 100 on and off. When voltage is applied to the gate electrode 116, it creates an electric field that penetrates downward through the ferroelectric layer 114, interfacial dielectric layer 112, and AlGaN barrier layer 110 to reach the 2DEG in the GaN channel layer 108.
[0053] In one embodiment of the present invention, a passivation layer 118 comprising silicon nitride (Si₃N₄) deposited over exposed device regions, including the areas between gate and source/drain contacts and over the gate electrode 116 itself, as indicated in the figure. The passivation layer 118 is configured to act as a robust shield protecting the underlying layers from environmental damage. The passivation layer 118 prevents moisture, oxygen, contaminants, dust, and corrosive chemicals from reaching the sensitive semiconductor layers and metal contacts beneath. Without the passivation layer 118 protection, exposure to humidity or air could cause oxidation, corrosion, or chemical reactions that degrade electrical properties, increase leakage currents, and eventually cause the device to fail.
[0054] The device 100 is configured to provide reduced interface trap density at the interface between the interfacial dielectric layer 112 and the AlGaN barrier layer 108 and reduced hysteresis compared to conventional MIS-HEMTs.
[0055] FIG. 2 illustrates flow chart of a method 200, outlining the sequential steps fabricating a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device 100, in accordance with an embodiment of the present disclosure.
[0056] At step 202, the process involves formation of an aluminium nitride nucleation layer 104 over a substrate. The AlN nucleation layer 104 is deposited over the substrate 102 using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) technique.
[0057] At step 204, a beta-gallium oxide buffer layer 106 is deposited over the AlN nucleation layer 104. The beta-gallium oxide buffer layer 106 may be grown using MOCVD, pulsed laser deposition (PLD), or atomic layer deposition (ALD) technique.
[0058] At step 206, a gallium nitride channel layer 108 is grown over the buffer layer 106. The gallium nitride (GaN) channel layer 108 is epitaxially grown over the buffer layer 106 using MOCVD or HVPE (hydride vapor phase epitaxy) technique.
[0059] At step 208, an aluminum gallium nitride barrier layer 110 is formed to induce the two-dimensional electron gas. The AlGaN barrier layer 110 is deposited using MOCVD technique with TMAl, TMGa, and NH₃ precursors.
[0060] At step 210, an interfacial dielectric layer 112 is deposited over the barrier layer 110. The interfacial dielectric layer 112 is deposited using atomic layer deposition (ALD) at temperatures between 200°C and 350°C. For Al₂O₃, trimethylaluminum and water are used as precursors in sequential, self-limiting surface reactions.
[0061] At step 212, a ferroelectric hafnium zirconium oxide layer 114 is deposited over the interfacial dielectric layer 112. The ferroelectric hafnium zirconium oxide layer 114 is deposited using atomic layer deposition with alternating cycles of hafnium and zirconium precursors.
[0062] At step 214, the orthorhombic phase is stabilized in the HfZrO₂ layer 114 through thermal annealing. The wafer undergoes rapid thermal annealing (RTA) at temperatures between 400°C and 800°C, preferably between 500°C and 700°C, for durations ranging from 10 seconds to 5 minutes. The annealing may be performed in an inert atmosphere such as nitrogen (N₂) or argon (Ar), or in forming gas (N₂/H₂ mixture).
[0063] At step 216, a gate electrode 116 is formed over the oxide stack. Following deposition, the gate electrode 116 is patterned using photolithography and etched using reactive ion etching (RIE) or wet chemical etching to define the gate geometry
[0064] At step 218, the device 100 is passivated by using Plasma Enhanced Chemical Vapor Deposition (PECVD) which is to deposit a silicon nitride layer 118 to prevent surface oxidation and current collapse.
[0065] In the best mode of operation of the present invention, the device 100 operates in an optimized and structured manner to ensure accurate threshold voltage control and tunability, reduced leakage, thermal robustness, and durability of operations. An AlN nucleation layer 104 of 200 nm thickness is formed over a SiC substrate layer 102 of 5 µm thickness, providing a foundational interface for subsequent layer deposition. A β-Ga₂O₃ buffer layer 106 of 300 nm thickness is formed over the AlN nucleation layer 104 to facilitate lattice matching and strain management. A GaN channel layer 108 of 300 nm thickness is grown over the β-Ga₂O₃ buffer layer 106, serving as the primary conduction pathway. An AlGaN barrier layer 110 of 30 nm thickness is formed over the GaN channel layer 108 to induce a two-dimensional electron gas (2DEG) at the heterointerface, which enables high-mobility electron transport. An interfacial dielectric layer 112 of 3 nm thickness is deposited over the AlGaN barrier layer 110, comprising at least one of Al₂O₃ and hexagonal boron nitride (h-BN), to provide electrical isolation and interface quality enhancement. A ferroelectric hafnium zirconium oxide (Hf₁₋ₓZrₓO₂) layer 114 of 5 nm thickness is deposited over the interfacial dielectric layer 112, which serves as the gate dielectric with switchable polarization properties. Thermal annealing is performed to stabilize an orthorhombic ferroelectric phase in the Hf₁₋ₓZrₓO₂ layer 114, ensuring reliable ferroelectric behavior and hysteresis characteristics. A gate electrode 116 is formed over the ferroelectric oxide layer 114 to enable voltage-controlled modulation of the channel conductivity. A passivation layer 118 is deposited over regions of the device to protect exposed surfaces and reduce surface state effects.
[0066] The present invention achieves significant technical effects by employing a multilayer gate stack comprising both an interfacial dielectric and a ferroelectric oxide, which together substantially reduce gate leakages while simultaneously minimizing interface trap density. This dual-layer approach provides superior long-term reliability under bias temperature stress, hot carrier injection, and time-dependent dielectric breakdown conditions and precise and stable threshold voltage control through the ferroelectric layer. Perhaps most significantly, the present invention provides a holistic solution that simultaneously addresses multiple performance limitations rather than optimizing individual characteristics in isolation. The synergistic combination of ferroelectric gate stack, engineered interfacial layer, and wide-bandgap buffer provides comprehensive improvements in threshold voltage control, gate leakage, breakdown voltage, thermal management, subthreshold characteristics, and long-term reliability within a single integrated device structure.
[0067] While the invention has been described in connection with what is presently considered to be the most practical and various embodiments, it will be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.
[0068] A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments disclosed in this specification, units and algorithm steps may be implemented by electronic hardware, computer software, or a combination thereof.
[0069] The foregoing descriptions of specific embodiments of the present disclosure have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described to best explain the principles of the present disclosure and its practical application, and to thereby enable others skilled in the art to best utilize the present disclosure and various embodiments with various modifications as are suited to the particular use contemplated. It is understood that various omissions and substitutions of equivalents are contemplated as circumstances may suggest or render expedient, but such omissions and substitutions are intended to cover the application or implementation without departing from the scope of the present disclosure.
[0070] Disjunctive language such as the phrase “at least one of X, Y, Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present.
[0071] In a case that no conflict occurs, the embodiments in the present disclosure and the features in the embodiments may be mutually combined. The foregoing descriptions are merely specific implementations of the present disclosure, but are not intended to limit the protection scope of the present disclosure. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present disclosure shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
, Claims:I/We Claim:
1. A ferroelectric-oxide engineered gallium nitride (GaN) metal-oxide-semiconductor high electron mobility transistor (MOSHEMT) device 100, the device (100) comprising:
a substrate (102) of a pre-defined thickness and configured to transfer heat;
a nucleation layer (104) of a pre-defined thickness and configured to reduce the leakage disposed over the substrate (102);
a buffer layer (106) of a pre-defined thickness and configured to offer a higher breakdown strength and better heat control disposed over the nucleation layer (104);
a channel layer (108) of a pre-defined thickness disposed over the buffer layer (106);
a barrier layer (110) disposed over the channel layer (108), the barrier layer (110) having a pre-defined thickness and forming a two-dimensional electron gas (2DEG) at the interface between the channel layer (108) and the barrier layer (110);
a gate stack (120) disposed over the barrier layer (110), the gate stack (120) further comprises:
an interfacial dielectric layer (112) of pre-defined thickness in contact with the barrier layer (110);
a ferroelectric oxide layer (114) of pre-defined thickness disposed over the interfacial dielectric layer (112);
a gate electrode (116) disposed over the ferroelectric oxide layer (114), and a passivation layer (118) configured to thermal stability over regions of the device, wherein the device (100) is configured to operate in normally-off mode and exhibits a subthreshold swing of less than 60 mV/decade at room temperature.
2. The device (100) as claimed in claim 1, wherein the substrate (102) comprises silicon carbide (SiC) and the pre-defined thickness lies in the range of 3-7 µm.
3. The device (100) as claimed in claim 1, wherein the nucleation layer (104) comprises AlN and the pre-defined thickness lies in the range of 100-300 nm.
4. The device (100) as claimed in claim 1, wherein the buffer layer (106) comprises β-Ga₂O₃ and the pre-defined thickness lies in the range of 100-500 nm and is configured to enhance breakdown voltage and thermal conductivity compared to conventional GaN buffer layers.
5. The device (100) as claimed in claim 1, wherein the channel layer (108) comprises GaN and the pre-defined thickness lies in the range of 100-500 nm.
6. The device (100) as claimed in claim 1, wherein the barrier layer (110) comprises AlGaN and the pre-defined thickness lies in the range of 10-50 nm.
7. The device (100) as claimed in claim 1, wherein the interfacial dielectric layer (112) comprises at least one material selected from Al₂O₃ and hexagonal boron nitride (h-BN) and the pre-defined thickness lies in the range of 1-5 nm.
8. The device (100) as claimed in claim 1, wherein the ferroelectric oxide layer (114) has a thickness in the range of 2-7 nm and is configured to operate in a negative capacitance regime to enable the subthreshold swing of less than 60 mV/decade.
9. The device (100) as claimed in claim 1, further comprising a silicon nitride (Si₃N₄) passivation layer (118) covering regions surrounding the T-gate electrode (116) and access areas between the gate and source/drain electrodes.
10. A method (200) for fabricating a ferroelectric-oxide engineered gallium nitride metal-oxide-semiconductor high electron mobility transistor device (100), the method (200) comprising:
forming an AlN nucleation layer (104) over a SiC substrate layer (102);
forming a β-Ga₂O₃ buffer layer (106) over the AlN nucleation layer (104);
growing a GaN channel layer (108) over the β-Ga₂O₃ buffer layer (106);
forming an AlGaN barrier layer (110) over the GaN channel layer (108) to induce a two-dimensional electron gas (2DEG);
depositing an interfacial dielectric layer (112) over the AlGaN barrier layer (110), the interfacial dielectric layer (112) comprising at least one of Al₂O₃ and hexagonal boron nitride (h-BN);
depositing a ferroelectric hafnium zirconium oxide (Hf₁₋ₓZrₓO₂) layer (114) over the interfacial dielectric layer (112);
performing thermal annealing to stabilize an orthorhombic ferroelectric phase in the Hf₁₋ₓZrₓO₂ layer (114);
forming a gate electrode (116) over the ferroelectric oxide layer (114); and
depositing a passivation layer (118) over regions of the device, wherein the resulting device (100) is configured to operate in normally-off mode and exhibits a subthreshold swing of less than 60 mV/decade at room temperature.