FIELD OF INVENTION

The present invention relates to a Full Custom Application Specific IC (ASIC) design for controlling a 3-phase Sensor Based Brushless DC motor taking inputs from sensors. The ASIC of the present invention employs Majority Voting Logic principle for the assertion of the 9 sensor inputs and implements a truth table for commutation operation. The ASIC controls the drive switches of DC motors. The ASIC of the present invention employs PWM architecture based operation and operates on ±15V dual supply for the analog blocks and 5Vdc for the digital blocks. The ASIC implements the torque control loop in a servo-control system from the triple Hall sensors input and with majority polling.

BACKGROUND AND PRIOR ART

The Brushless DC (BLDC) Motor has a rotating permanent magnet (rotor). The rotor is surrounded by equally spaced windings (stator), which are fixed. Current through the stator windings produces a magnetic field of arbitrary magnitude and direction. The interplay between the net stator field and the magnetic field of the rotor generates a back electromagnetic force and Torque. The stator windings' energizing > (the output current and voltage control) sequence (Commutation), determine the various modes of operation of a Brushless DC motor. The Commutation of the BLDC motor is of two types, Hall Sensor Based Commutation, Sensor-less Commutation. Based on the current and voltage control methods the Speed & Torque of a BLDC motor can be harnessed. Based on the application, a BLDC motor can be configured for Open Loop and Closed Loop Operation.

Any general BLDC motor control ASIC device, employs FPGA based direction, torque/speed control and commutation of a BLDC motor or employ separate ICs for control operations and driver mechanism. These methods, though, find their acceptance in satisfying the functional requirements; the design complexity involved in realizing the application is very high. This directly translates to a proportionate increase in power, area and more importantly cost.

The present disclosure, BE5062, 3-phase Majority Voting Logic Brushless DC motor Control ASIC is custom designed for a 3 phase Sensor Based Brushless DC motor control, optimized for area, power and reduced system complexity, without sacrificing the functional requirements, for extreme conditions of operation. It integrates the analog block for Torque/Direction Control and digital block for rotor position sensing, implementing commutation sequence, on a single monolithic IC device.

The ASIC, senses the Motor coil current. The sense voltage is processed through a polarity switched Amplifier. The error signal between the Programmable current Command voltage and the current sense voltage is processed in a high gain Amplifier. The PWM function is derived from a programmable dual polarity triangular wave generator and the error signal. The PWM signal is time delayed for generating a dead-band pulse. The delay is programmable through a single external capacitor. The three Logic inputs required for the 120° electrical commutation is derived from 9 input Hall sensor signals by a Majority Voting Logic circuit having Schmitt trigger input buffers. The commutation logic generates the six outputs according to the commutation truth table.

US2004088623 (Al) titled "Digital signaling voting scheme" describes a digital voting scheme in a modular uninterruptible power supply (UPS) for a multiple device system in which fail-safe protection is required. The voting circuit includes a comparator for comparing a decision output signal and cumulative effect of decision output signals of the voting circuits arranged in parallel modules with a reference threshold signal (VREF). It also includes an avalanche detecting circuit detects the avalanche point and generates a clear cut majority decision control at this point.

US2010005373 (Al) titled "Majority voting logic circuit for dual bus width" describes a circuit to determine whether to invert a bus, where the bus is operable having a plurality of widths. The circuit comprises of a comparison circuitry to receive a current value and next value for the bus and individually compare the current and new values for each of the said bits on the bus to determine whether the value of the bits has changed. The voting circuit connected to comparison circuitry determines the bus inversion values based upon whether the number of bits that have changed have exceeded the value that depends upon the indication of the bus width.

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 illustrates the block diagram of the 3-phase Majority Voting Logic Brushless DC motor Control ASIC.

Figure 2 illustrates the physical design view of the Application Specific Integrated Circuit

Figure 3 illustrates the Pin Diagram of the packaged 3-phase Majority Voting Logic Brushless DC motor Control ASIC with marked terminals.

Figure 4 illustrates the conventional TTL 2 input AND gate architecture.

Figure 5 illustrates the present invention of TTL 2 input AND gate design optimized for area and power.

Figure 6 illustrates a novel delay generation technique used to delay the PWM signal. Dead band pulse is generated by taking XOR output of PWM and delayed PWM.

Figure 6 is a temperature compensated delay generation scheme using the current charge and discharge method. The delay is programmable through an external capacitor element.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Figure 1 describes the primary embodiment of the present disclosure, which is a 3-phase Majority Voting Logic Brushless DC motor Control ASIC 100 integrating analog and digital blocks. The Analog block comprises of Differential Buffer Amplifier (DBA) 101, Polarity Switching Amplifier (PSA) 102, Error Amplifier (EA) 103, PWM comparator 104 and a Triangular Wave Generator 105. The Digital block consists of Schmitt Trigger Input Buffers 106 for the hall sensor inputs, Majority Voting Logic 107, Commutation Logic 108, Pass/Invert block 109, a Dead-Band Pulse generator 110 and a Delay Block 111. It also integrates an uncommitted comparator 112 and an uncommitted operational amplifier ( op_amp) 113 that can be used, independently, for any other operations that may require these Comparator and Operational Amplifier.

Figure 2 illustrates a physical design of the ASIC. The physical design topography of the ASIC exhibits innovation in its layout by incorporating layer isolations and protection guards required for providing higher current drive capability to the devices through a process of fabrication. The chip size of the integrated circuit is approximately estimated as 4.8 mm against 4.1mm and includes 44 pads in the design.

Figure 3 illustrates the pin configuration of an ASIC device fabricated in 40V/4um bipolar process. The tested die is attached to a substrate of lead frame and connected by gold bond wires from the bond pads to the external leads and then encapsulated to form a 44pin device. The device is packaged as a 44 pin CQFP and involves a bipolar process. The input pins of the digital block of the ASIC are the 9 Hall sensor Inputs HAB1 5, HAB2 6, HAB3 7, HBC1 8, HBC2 9, HBC3 10, HCA1 11, HCA2 12, HCA3 13 which correspond to 106a-106i respectively. The Shut Down pin SD 19, PWMIN 16, DEL 17 for delay programming, P/I 20 correspond to 110b, 110a, Ilia, and 109a respectively. Similarly, the analog inputs of the ASIC are SENSEHI 35, SENSELO 34, DBAOUT 36, POLSWITCH 37, EA- 39, CMD 40, EA_39, OFFSET 38, FT 2, OPIN+ 31, OPIN- 32, COMPIN- 28, COMPIN+ 29, DBAOFF 33 correspond to 101a, 101b, lOld, 102a, 103b, 103a, 103c, 105a, 113a, 113b, 112a, 112b and 101c respectively. The digital block outputs are A 26, B 25, C 24, D 23, E 22, F 21, DBP 18 correspond to 109b, 109c, 109d, 109e, 109f, 109g and 110c respectively.

The analog block outputs DBAOUT 36, PSOUT 41, EAOUT 42, PWMOUT 1, COMPOUT 27 and OPOUT 30 correspond to lOld, 102b, 103d, 104a, 112c and 113c respectively. lOOd and lOOf indicate the grounding for the pin. VCC 44,, VEE 43, VDD 14 corresponds to 100a, 100b and 100c respectively are the supplies of the device.

Figure 4 shows the conventional TTL gate architecture of a 2 input AND gate 301-312. The conventional TTL gates require high current drives and draw high quiescent currents. From figure 4 we can see that conventional TTL gates use resistors to fix the current drives in the gate. The quiescent current required for each gate is very high. For low current operation, the values of resistors required are too high, thereby occupying large area. Use of resistors; make the gates prone to temperature and supply variations.

Figure 5 shows the present invention of TTL two input AND gate design optimized for area and power 351-363. The resistors in conventional TTL gates shown in Figure 4 are replaced by current sources compensated for supply and temperature variations to operate at low currents. These gates are operated with regulated supply voltage instead of VDD. The gates designed using the above methodology are Inverter, three input OR gate, three input AND gate, two input OR gate, two input AND gate, two input XOR gate which were used to implement the digital block.

Figure 6 shows a novel delay generation technique used to delay the PWM signal 381-383. The delay generation is accomplished using a current charge and discharge method. The current source 12 is turned ON and OFF based on the PWM logic level. The voltage across the capacitor 382 is fed to a Schmitt Trigger. The Schmitt Trigger output changes state as the voltage across the capacitor reaches it upper threshold point UTP and lower threshold LTP based on 12's ON/OFF condition. The capacitor along with the UTP and LTP, determine the delay generated. The Schmitt Trigger output 383 corresponds to the delayed PWM signal 381.The delay generated is programmable through 11 la by the Capacitor which is external to the ASIC.

In the present invention 100, the Differential Buffer Amplifier 101 senses the voltage across the sense resistor and feeds it to the polarity-switching amplifier 102. The polarity-switching amplifier 102 acts as inverting and non-inverting based on PWM signal. The external switch controlling the Polarity-Switching Amplifier 102 is either open or grounded based on the PWM logic level. The High Gain Error Amplifier 103 functions to amplify the difference between the command voltage and the current sense voltage. The polarity of the command decides the direction of motor rotation and the magnitude controls the torque. The error voltage generated is fed to a PWM Comparator 104 which compares the error with a triangle wave generated by the reference Triangle Wave Generator 105. The PWM Comparator 104 with built in hysteresis, generates the PWM signal with a duty cycle range of 0%-100%. The 9-Hall sensor outputs are fed to Majority Voting Logic 107 circuit through Schmitt Trigger buffers 106. The Majority Voting Logic 107 executes the polling to ensure accurate determination of the rotor position. The Commutation Logic 108 generates six outputs according to a Commutation Truth Table. The inputs to the Commutation Truth Table are PWM, Mask Bit and three Majority Voting Logic 107 outputs HAB 5-7, HBC 8-10, HCA 11-13. The PASS/INVERT Block 109 will pass or invert commutation logic outputs depending on the P/120 signal. The shutdown input when asserted, forces the six Commutation Logic outputs (A through F) to logic 'Off, irrespective of all other inputs. The shutdown bit is OR'd with the dead band pulse to generate the mask bit, which is fed to the commutation logic, block 107.

The following are Features of the present device:

• Direction and Torque control through external command
• Majority Voting Logic to assert the inputs and to ensure fail-safe Commutation
• Complementary four Quadrant control
• Programmable PWM frequency
• 120° Electrical Commutation
• Programmable Dead band
• Wide operating temperature range of -55° to 125°C
• An uncommitted Opamp and a Comparator

The fabricated 3-phase Majority Voting Logic Brushless DC motor Control ASIC finds application in Servo Control Electronics.

Finally, while the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the claims.

WE CLAIM

1. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 used in servo control electronics for direction and torque control capable of operating in a wide operating temperature range of -55°C to 125°C, programmable dead-band, integrating analog and digital blocks wherein:

(a) The Analog block is further comprised of:

i. A Digital Buffer Amplifier 101 (DBA); ii. A Polarity Switching Amplifier (PSA) 102; iii. An Error Amplifier (EA) 103;

iv. A Pulse Width Modulator (PWM) comparator 104; and v. A Triangular Wave Generator 105;

(b) The Digital block is further comprised of:
i. One or more Schmitt trigger input buffers 106;
ii. Majority voting logic 107;
iii. Commutation logic 108;
iv. A pass and invert block 109;
v. A dead band pulse generator 110;
vi. A delay block 111;
vii. An uncommitted comparator 112; and
viii. An uncommitted operational amplifierll3.

2. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1, where the coil current converted voltage is offset compensated by a Differential Buffer Amplifier 101 and processed by Polarity Switching amplifier 102 for polarity selection of the sense voltage in the analog block.

3. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in claim 1 wherein the High Gain Error Amplifier 103 compares this voltage with an external command voltage to generate the error signal.

4. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1, wherein the analog block further compares the error signal with a dual polarity triangular wave to generate a PWM wave with duty cycle proportional to the error generated, thereby controlling the Direction and Torque of the BLDC motor in a closed loop operation.

5. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1 which senses the rotor position through the Hall Sensor Inputs wherein these inputs are received by Schmitt Trigger Buffers 106 and fed to the Majority Voting Logic 107 said Schmitt Trigger Buffers 106 being used to provide sufficient noise margin.

6. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in claim 1 which includes a Majority Voting Logic 107 which executes polling of the hall sensor inputs received for assertion of the Hall sensor inputs fed to Commutation Logic Block 108 for accurate determination of the rotor position

7. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1 which includes a Commutation Logic Block 108 which implements the look-up table sequence for 120° electrical commutation of the motor.

8. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1, including a drive polarity selection option P/I Block 109, to select the outputs wherein:

(a) Said outputs are set as active High when the Pass Signal is obtained; and

(b) Said outputs are set as low when the Invert signal is obtained; To drive the High Side and Low Side switches.

9. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1, where an innovative low power logic gate design is implemented in the digital block optimized for power and area.

10. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1, including a Dead-Band Pulse 110 generator to prevent simultaneous turn-on of the High Side and Low Side switches wherein the delay Block 111 which delays the PWM signal uses a novel delay generation technique as shown in Figure 6. The delay is programmable through an external capacitor element.

11. An improved monolithic three phase sensor based Brushless DC Motor Controller Integrated Circuit (IC) device 100 as claimed in Claim 1, wherein the ASIC is fabricated in a 40V/4um Bipolar Process and assembled in a 44 pin Ceramic Quad Flat package.