Claims:
We claim:
1. A method for fabricating a 3-Dimensional (3D) Slow Wave Structure (SWS), comprising:
performing on a first surface of each of a first wafer and a second wafer, steps of:
forming a pattern of helical channel (306) and longitudinal channel (305) of a Slow Wave Structure (SWS) on a first material (302) deposited on the first surface;
forming a pattern of the helical channel (306) on a second material (304) , wherein the second material (304) is disposed on the first material (302);
etching the first surface by using the second material (304) as hard mask to form one or more trenches of a first predefined depth defining the helical channel (306) in the first wafer and the second wafer, wherein the second material (304) is removed upon said etching; and
etching the first surface by using the first material (302) as hard mask to form one or more trenches of a second predefined depth defining the helical channel (306) and the longitudinal channel (305) in the first wafer and the second wafer, wherein the first material (302) is removed upon said etching; and
bonding the first surface of each of the first wafer and the second wafer to form the 3-Dimensional (3D) SWS.

2. The method as claimed in claim 1, wherein the one or more trenches of the first predefined depth and the one or more trenches of the second predefined depth of each of the first wafer and the second wafer is coated with a metal, for the bonding.

3. The method as claimed in claim 1, wherein each of the first wafer and the second wafer are one of Silicon (Si) substrate or a glass substrate.

4. The method as claimed in claim 1, wherein the first surfaces of the first wafer and the second wafer are deposited with a metal for performing the bonding.

5. The method as claimed in claim 1, wherein the bonding is performed using one or more compressive techniques associated with bonding.

6. The method as claimed in claim 1, wherein the etching is performed either a dry etching process or a wet etching process, or a combination thereof, so as to enable selective etching.

7. The method as claimed in claim 1, wherein each of the first material (302) and the second material (304) is selected from a plurality of masking materials, and wherein the first material (302) is different from the second material (304).

8. The method as claimed in claim 1, wherein the pattern on the first material and the pattern on the second material is formed by performing photolithography.

9. A 3-Dimensional (3D) Slow Wave Structure (SWS), comprises:
a first wafer; and
a second wafer, wherein, the 3D SWS is fabricated by:
performing, on a first surface of each of the first wafer and the second wafer, steps of:
forming a pattern of helical channel (306) and longitudinal channel (305) of a Slow Wave Structure (SWS) on a first material (302) deposited on the first surface;
forming a pattern of the helical channel (306) on a second material (304) , wherein the second material (304) is disposed on the first material (302);
etching the first surface of each of the first wafer and the second wafer by using the second material (304) as hard mask to form one or more trenches of a first predefined depth defining the helical channel (306) in the first wafer and the second wafer, wherein the second material (304) is removed upon said etching; and
etching the first surface of each of the first wafer and the second wafer by using the first material (302) as hard mask to form one or more trenches of a second predefined depth defining the helical channel (306) and the longitudinal channel (305) in the first wafer and the second wafer, wherein the first material (302) is removed upon said etching; and
bonding the first surface of each of the first wafer and the second wafer to form the 3-Dimensional (3D) SWS.

10. The 3D SWS as claimed in claim 9, wherein the one or more trenches of the first predefined depth and the one or more trenches of the second predefined depth of each of the first wafer and the second wafer is coated with a metal, for the bonding.

11. The 3D SWS as claimed in claim 9, wherein each of the first wafer and the second wafer is either of Silicon (Si) substrate or of glass substrate.

12. The 3D SWS as claimed in claim 9, wherein the first surfaces of the first wafer and the second wafer are deposited with a metal for performing the bonding.

13. The 3D SWS as claimed in claim 9, wherein the bonding is performed using one or more compressive techniques associated with the bonding.

14. The 3D SWS as claimed in claim 9, wherein the etching is performed using either a dry etching process or a wet etching process, or a combination thereof, so as to enable selective etching.

15. The 3D SWS as claimed in claim 9, wherein each of the first material (302) and the second material (304) is selected from a plurality of masking materials, and wherein the first material (302) is different from the second material (304).

16. The 3D SWS as claimed in claim 9, wherein the pattern on the first material and the pattern on the second material is formed by performing photolithography.

Dated this 26th Day of March, 2019

R. Ramya Rao
IN/PA-1607
Of K & S Partners
Agent for the Applicant

, Description:TECHNICAL FIELD
The present subject matter is related in general to fabrication technology, more particularly, but not exclusively, to a 3-Dimensional (3D) Slow Wave Structure (SWS) and a fabrication method for the SWS.

BACKGROUND
A Slow Wave Structure (SWS) is a transmission path, configured to reduce the group velocity in a transmission line. An SWS may be implemented in Terahertz (THz) sources where radiation is transmitted at THz frequencies. In a microwave tube, an SWS may be used to generate or to amplify Radio Frequency (RF) and microwave signals at high power over a large bandwidth. An SWS may comprise a helical channel and a longitudinal channel, for transmission of radiation. Micro Electro Mechanical System (MEMS) technologies may be used to fabricate 3-Dimensional (3D) SWS. Fabrication may be performed on metal substrates to obtain a multi-bonded substrate for building 3D SWS structure with the desired size. Such fabrication, also referred to as the metal fabrication, includes one or more processes performed on the substrates for building or assembling SWS. These processes may include cutting, bending, etching, photolithography, binding, assembling and so on. Through fabrication, trenches may be formed in the substrates using one or more these processes, subsequent to which bonding of a plurality of substrates may be performed to manufacture the 3D SWS with hollow channels, i.e., the helical channel and the longitudinal channel.

An existing fabrication method for manufacturing 3D SWS includes initially the use of a photoresist to form trenches in the first substrate to define the helical channel. The longitudinal channel may be defined in a second substrate by forming trenches using a deposited material and a photoresist. The bonding of the first substrate with the helical channel and the second substrate with the longitudinal channel is performed to obtain the first part of the 3D SWS. A similar process is performed on another set of a first substrate and a second substrate to obtain the second half of the 3D SWS. Subsequently, bonding of the first part and the second part is performed to obtain the 3D SWS with hollow channels. This method of fabrication requires more than two substrates for manufacturing the 3D SWS. Furthermore, this method involves multiple bonding processes and planarization of substrates prior to bonding. This leads to increase in the complexity and the cost of the fabrication process.

The information provided in this Background section, prior to the description of the instant invention, is only for enhancement of understanding of the general background of the instant invention, and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

SUMMARY
In an embodiment, the present disclosure relates to a method for fabricating a 3-Dimensional (3D) Slow Wave Structure (SWS). The method includes performing on a first surface of each of a first wafer and a second wafer the steps of forming a pattern of helical channel and longitudinal channel of a Slow Wave Structure (SWS) on a first material deposited on the first surface,; forming a pattern of the helical channel on a second material, wherein the second material is disposed on the first material; etching the first surface by using the second material as hard mask to form one or more trenches of a first predefined depth defining the helical channel in the first wafer and the second wafer, wherein the second material is removed upon said etching; and etching the first surface by using the first material as hard mask to form one or more trenches of a second predefined depth defining the helical channel and the longitudinal channel in the first wafer and the second wafer, wherein the first material is removed upon said etching. The method further includes the step of bonding the first surface of each of the first wafer and the second wafer to form the 3D SWS.

In an embodiment, the present disclosure relates to 3D SWS comprising a first wafer and a second wafer. The 3D SWS is fabricated by performing, on a first surface of each of the first wafer and the second wafer, the steps of forming a pattern of helical channel and longitudinal channel of a Slow Wave Structure (SWS) on a first material deposited on the first surface,; forming a pattern of the helical channel on a second material, wherein the second material is disposed on the first material; etching the first surface of each of the first wafer and the second wafer by using the second material as hard mask to form one or more trenches of a first predefined depth defining the helical channel in the first wafer and the second wafer, wherein the second material is removed upon said etching; and etching the first surface of each of the first wafer and the second wafer by using the first material as hard mask to form one or more trenches of a second predefined depth defining the helical channel and the longitudinal channel in the first wafer and the second wafer, wherein the first material is removed upon said etching. Fabricating the SWS further includes bonding the first surface of each of the first wafer and the second wafer to form the 3D SWS.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to reference like features and components. Some embodiments of system and/or methods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which:

Figures 1 illustrates a flowchart showing an exemplary method for fabricating a 3D SWS, in accordance with some embodiments of present disclosure;

Figure 2 illustrates a flowchart showing an exemplary method for defining channels of a 3D SWS, in accordance with some embodiments of present disclosure; and

Figures 3a-3n illustrate an exemplary process for fabricating a 3D SWS, in accordance with some embodiments of present disclosure.

It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
In the present document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the present subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

While the disclosure is susceptible to various modifications and alternative forms, a specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the spirit and the scope of the disclosure.

The terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.

The terms “includes”, “including”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device or method that includes a list of components or steps, does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “includes… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.

In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.

The present disclosure teaches a 3D SWS and fabrication method for manufacturing the 3D SWS. The method proposed in the present disclosure uses a minimal number of substrates and fabrication processes, thereby reducing cost and complexity of the fabrication process. In the present disclosure, the first material and the second material, along with a photoresist, are used for defining the helical channel and the longitudinal channel of the SWS, in each of two substrates. The fabrication process, including the steps of photolithography and etching, is performed for defining the helical channel and the longitudinal channel. Further, a bonding process may be performed on the two substrates to build the 3D SWS.

In an embodiment of the present disclosure, the fabrication of the 3D SWS may be performed by a fabrication module. The fabrication module is configured to create an integrated circuit that may be implemented in electrical devices and electronics devices. The fabrication module may be a tool or a device which may be configured to perform the fabrication method proposed in the present disclosure. One or more modules, known to a person skilled in the art, may be configured to perform the steps of the present disclosure.

Figures 1 illustrates a flowchart showing an exemplary method for fabricating the 3D SWS, in accordance with some embodiments of the present disclosure.

In block 101, the fabrication module may be configured to perform the steps of photolithography and etching on the first surface of each of a first wafer and a second wafer. The first wafer and the second wafer may be made of a material selected from a group comprising Silicon (Si) substrate and/or a glass substrate. In an embodiment, the first wafer may be referred to as first substrate and the second wafer may be referred to as a second substrate. By performing the steps of photolithography and etching, the helical channel and the longitudinal channel of the 3D SWS may be defined in the first wafer and the second wafer. Figure 2 illustrates a flowchart showing an exemplary method for defining channels, i.e., the helical channel and the longitudinal channel of the 3D SWS.

In block 201, the fabrication module may be configured to form a pattern of the helical channel and the longitudinal channel on a first material deposited on the first surface. One or more techniques, known to a person skilled in the art, may be implemented for forming the pattern on the first material. In an embodiment, the pattern may be formed by performing photolithography. For the photolithography, a photoresist may be deposited on the first material. The pattern of the helical channel and the longitudinal channel may be formed by suitably irradiating the photoresist. The portion of the first material, which is not protected by the photoresist, is removed to form the pattern. The photoresist may be removed upon said photolithography. One or more techniques, known to a person skilled in the art, may be used for forming the pattern of the helical channel and the longitudinal channel, using photolithography.

In block 202, the fabrication module may be configured to form a pattern of the helical channel on a second material disposed on the first material upon defining the helical channel and the longitudinal channel at block 201. One or more techniques, known to a person skilled in the art, may be implemented for forming the pattern on the second material. In an embodiment, the pattern of the helical channel may be formed by performing photolithography. For photolithography, a photoresist may be deposited on the second material. The pattern of the helical channel may be formed by suitably irradiating the photoresist. The portion of the second material, which is not protected by the photoresist, is removed to form the pattern. The photoresist may be removed upon said photolithography. One or more techniques, known to a person skilled in the art, may be used for forming the pattern of the helical channel, using photolithography.

In block 203, the fabrication module may be configured to etch the first surface by using the second material as hard mask. By said etching, one or more trenches may be formed in the first wafer and the second wafer. Etching is the process used for cutting or removing parts of a metal surface which are not protected by hard mask, to form a design. For forming said one or more trenches, parts on the first surface, which are not protected by the second material, are etched out. Here, the second material acts as the hard mask. By this, the one or more trenches with a first predefined depth may be formed to define the helical channel of the SWS. In an embodiment, the first predefined depth may be 300 µm from the first surface. One or more techniques, known to a person skilled in the art, may be used for the etching. In an embodiment, the etching may be selective, and selective etching may be achieved by using the second material as the hard mask. The (one or more) techniques for performing the etching may include, but are not limited to, dry etching and wet etching.

In block 204, the fabrication module may be configured to remove the second material upon performing the etching in block 203. One or more techniques, known to a person skilled in the art, may be implemented for removing the second material.

In block 205, the fabrication module may be configured to etch the first surface by using the first material as hard mask to form one or more trenches in the first wafer and the second wafer. For forming said one or more trenches, those parts on the first surface, which that are not protected by the first material, are etched out. Here, the first material acts as the hard mask. By this, the one or more trenches of a second predefined depth may be formed to define the helical channel and the longitudinal channel of the SWS. In an embodiment, the first predefined depth may be 100 µm from the first surface. The first material may be removed upon performing said etching. In an embodiment, the etching may be selective and the selective etching may be achieved by using the first material as the hard mask.

In block 206, the fabrication module may be configured to remove the first material upon performing the etching in block 205. One or more techniques, known to a person skilled in the art, may be implemented for removing the first material.

In an embodiment, the first material and the second material may be selected from a plurality of masking materials. In an embodiment, the first material may be different from the second material. In an embodiment, the plurality of masking materials may include, but are not limited to, Silicon-di-oxide (SiO2), Aluminium oxide (Al2O3), Silicon nitride (Si3N4) and such. Each of the first wafer and the second wafer may be selected from the plurality of masking materials.

Referring back to Figure 1, upon performing steps of the photolithography and the etching on the first surface of each of the first wafer and the second wafer, the fabrication module may be configured to bond the first surface of each of the first wafer and the second wafer to form the 3D SWS. In an embodiment, the bonding may be performed using one or more compressive techniques associated with bonding. In an embodiment, techniques such as a thermo-compression technique, eutectic bonding methods and such, may be used for performing the bonding.

In an embodiment, the one or more trenches of the first predefined depth and the one or more trenches of the second predefined depth of each of the first wafer and the second wafer may be coated with a metal, for performance of the bonding. In an embodiment, the metal may be deposited by performing electroplating on the first surfaces of the first wafer and the second wafer. In an embodiment, the metal may be gold.

As illustrated in Figures 1 and 2, the methods 100 and 101 may include one or more blocks for executing processes in the present disclosure. The methods 100 and 101 may be described in the general context of computer-executable instructions. Generally, computer-executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types.

The order in which the methods 100 and 101 are described may not be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

Figures 3a-3n illustrate an exemplary process for fabricating the 3D SWS, in accordance with some embodiments of present disclosure.

Figure 3a shows an exemplary substrate 300 with first surface 301. The substrate 300 may be one of a semiconductor or an electrical insulator used for manufacturing the 3D SWS. In an embodiment, the substrate 300 may be a Si substrate or a glass substrate. The process of fabrication may be performed on the first surface 301 of the substrate 300. The substrate 300 may be used as the first wafer and the second wafer for fabricating the 3D SWS. Consider that for fabricating the 3D SWS, the substrate 300 is used as the first wafer 300a with first surface 301a and as the second wafer 300b with first surface 301b.

Figures 3b-3n illustrate the process of fabrication on the first wafer 300a.

Initially, for the fabrication, the first surface 301a of the first wafer 300a is deposited with the first material 302. Figure 3b shows a cross-section view of the first wafer 300a, upon deposition of the first material 302. In an embodiment, the first material 302 may be selected from plurality of masking materials known to a person skilled in the art. Upon depositing the first material 302, a photoresist 303 may be deposited on the first material 302. Figure 3c shows a side view of the first wafer 300a, upon deposition of the photoresist 303 on the first material 302. The photoresist 303 may be deposited such that patterns of the helical channel and the longitudinal channel are formed on the first material 302. The photoresist 303 is deposited on a portion of the first material 302 apart from portion forming the pattern. During the photolithography, when photoresist 303 is suitably irradiated, that portion covered by the photoresist 303 is protected, and the portion of the first material 302 exposed to the light may be removed (by etching). By this, the pattern of the helical channel and the longitudinal channel may be formed. Upon forming the pattern on the first material 302, the photoresist 303 may be removed. Figure 3d shows a side view of the first wafer 300a with the pattern on the first material 302, upon removal of the photo-resist 303.

Further, upon the first material 302 with the pattern of the helical channel and the longitudinal channel, is deposited the second material 304. Figure 3e shows a side view of the first wafer 300a, upon deposition of the second material 304 on the first material 302. In an embodiment, the second material 304 may be selected from a plurality of masking materials. Upon depositing the second material 304, photoresist 303 may be deposited on the first material 302. Figure 3f shows a side view of the first wafer 300a, upon deposition of photoresist 303 on the second material 304. The photoresist may be deposited such that the pattern of the helical channel is formed on the second material 304. The photoresist 303 is deposited on a portion of the second material 304, excluding that portion which forms the pattern of the helical channel. During photolithography, when the photoresist 303 is suitably irradiated, the portion covered by the photo resist 303 is protected and the portion of the second material 304 that is irradiated may be removed. By this, the pattern of the helical channel is formed. Upon forming the pattern on the second material 304, the photoresist 303 may be removed. Figure 3g shows a side view of the first wafer 300a with the pattern on the second material 304, upon removal of the photoresist 303.

Further, the second material 304 is used as the hard mask to form the one or more trenches 305a-305b of the first predefined depth in the first wafer 300a. Said one or more trenches 305a-305b may be formed by performing etching on the first surface 301a. By the etching, that portion on the first wafer 300a, which is not covered by the second material 304, is etched out. Figure 3h shows the first wafer 300a with the one or more trenches 305a-305b of the first predefined depth. Upon forming the one or more trenches 305a-305b with the first predefined depth, the second material 304 may be removed. Figure 3i shows a side view of the first wafer 300a with the one or more trenches 305a-305b, upon removal of the second material 304. The one or more trenches 305a-305b of the first predefined depth are formed to define the hollow channel in the first wafer 300a. The hollow channel defines the helical channel in the first wafer 300a. Figure 3j shows a top view of the first wafer 300a with the one or more trenches 305a-305b defining the helical channel 306.

Further, the first material 302 is used as the hard mask to form the one or more trenches 307a-307c of the second predefined depth in the first wafer 300a. Said one or more trenches 307a-307c may be formed by performing etching on the first surface 301a. By the etching, that portion on the first wafer 300a, which is not covered by the first material 302, is etched out. Figure 3k shows a side view of the first wafer 300a with the one or more trenches 307a-307c of the second predefined depth. Upon forming the one or more trenches 307a-307c with the second predefined depth, the first material 302 is removed. Figure 3l shows a side view of the first wafer 300a with the one or more trenches 307a-307c, upon removal of the first material 302. The one or more trenches, 307a-307c of the second predefined depth, are formed to define hollow channels in the first wafer 300a. The hollow channel defines the helical channel 306 and the longitudinal channel on the first surface 301a in the first wafer 300a. Figure 3m shows a top view of the first wafer 300a with the one or more trenches 307a-307c defining the helical channel 306 and the longitudinal channel 308.

The process illustrated in Figures 3b-3m is performed on the second wafer 300b as well. By this, the second wafer 300b comprising the helical channel 306 and the longitudinal channel 308 on the first surface 301b of the second wafer 300b is obtained.

In the present disclosure, upon obtaining the first wafer 300a and the second wafer 300b, each with the helical channel 306 and the longitudinal channel 308, the bonding process may be performed. In the bonding process, the first surface 301a of the first wafer 300a and the first surface 301b of the second wafer 300b are bonded to form the 3D SWS. One or more techniques, known to a person skilled in the art, may be used for the bonding. Figure 3n shows the 3D SWS with the helical channel 306 and the longitudinal channel 308, formed by bonding the first wafer 300a and the second wafer 300b.

Advantages
An embodiment of the present disclosure provisions a method for fabricating a 3D SWS with a minimal number of substrates and a single bonding process. The proposed fabrication includes a dual mask and a single bonding step, through which the complexity and the cost of fabrication are reduced.

An embodiment of the present disclosure uses masking materials instead of photoresist, by which selective etching may be performed on a substrate.

The operations described may be implemented as a method, system, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The described operations may be implemented as code maintained in a “non-transitory computer readable medium”, where a processor may read and execute the code from the computer readable medium. The processor is at least one of a microprocessor and a processor capable of processing and executing the queries. A non-transitory computer readable medium may include media such as a magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, DVDs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), etc. Further, non-transitory computer-readable media may include all computer-readable media except for a transitory. The code implementing the described operations may further be implemented in hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application-Specific Integrated Circuit (ASIC), etc.).

Still further, the code implementing the described operations may be implemented in “transmission signals”, where transmission signals may propagate through space or through a transmission media, such as, an optical fibre, copper wire, etc. The transmission signals in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signals in which the code or logic is encoded is amenable to being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a non-transitory computer readable medium at the receiving and transmitting stations or devices. An “article of manufacture” includes non-transitory computer readable medium, hardware logic, and/or transmission signals in which code may be implemented. A device in which the code implementing the described embodiments of operations is encoded may include a computer-readable medium or hardware logic. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the invention, and that the article of manufacture may include a suitable information-bearing medium known in the art.

The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the invention(s)” unless expressly specified otherwise.

The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise.

The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.

A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the invention.

When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the invention need not include the device itself.

The illustrated operations of Figures 1 and 2 show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified, or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units.

Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Referral numerals:
Reference Number Description
300 Substrate
300a First wafer
300b Second wafer
301 First surface of substrate
301a First surface of first wafer
301b First surface of second wafer
302 First material
303 Photoresist
304 Second material
305a-305b One or more trenches of first predefined depth
306 Helical channel
307a-307c One or more trenches of second predefined depth
308 Longitudinal channel