DESC:FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENT RULES, 2003
COMPLETE SPECIFICATION
(See Section 10 and Rule 13)

Title of Invention:
A BATTERY PACK ASSEMBLY FOR MANAGING MODULE PARALLELING

APPLICANT:
EXPONENT ENERGY PVT. LTD.
An Indian entity having address as:
No.76/2, Site No.16, Khatha No.69, Singasandra Village, Bengaluru (Bangalore) Urban, BENGALURU, KARNATAKA 560068
The following specification particularly describes the invention and the manner in which it is to be performed.

CROSS-REFERENCE TO RELATED APPLICATIONS AND PRIORITY
The present application claims priority from the Indian patent application, having application number 202341023019, filled on 29th March 2023, incorporated herein by a reference.
TECHNICAL FIELD
The present disclosure relates to a field of batteries and battery modules. More specifically, the present invention relates to a battery assembly architecture
BACKGROUND
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present disclosure that are described or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements in this background section are to be read in this light, and not as admissions of prior art. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to implementations of the claimed technology.
In the field of battery architecture, preferably for electric vehicles (EVs), a battery assembly (also termed as, a battery pack/module or an energy storage system) comprises various components and connections. Each component of the battery assembly adds impedance into the overall battery system. Further in an application of high-capacity battery packs, a large number of battery modules needs to be connected to operate as a high voltage battery pack. Problem with the current battery architecture field is that today’s battery systems are required to be robust in terms of energy output as well as size. For higher energy output, ‘cell paralleling’ technique is used in the industry. In this method, to have a higher capacity battery pack from cells of fixed capacity, the cells have to be connected in parallel to each other. Each cell also needs voltage monitoring to ensure the cell remains in its rated operating conditions. Further, the rating of the parallel connection must be adequate to handle current imbalance due to piece-to-piece variations of the pack built due to variations in internal resistance of cells, busbar/conducting strip resistance, fastening mechanisms for example bolting, welding, clamping etc.
Further in the application of battery pack built with multiple cells in series and parallel combination, to ensure that all cell voltages are measured, conventional industrial practice involves connection of parallel cells using cell to cell welding using nickel strips, plated copper or aluminium busbars or bolting them together with busbars. However, the welding of cells makes a permanent connection, which has drawbacks that the cells become non-serviceable. Which means that any failure in a single cell leads to scrapping of the whole set of parallel cells or the entire battery pack. Further, bolting of the cells makes a semi-permanent connection, which has a drawback of low packaging density of the battery pack. Further, welding and bolting of cell connections leads to a fixed end voltage as they share the same potential busbar or strip of conductor. Another drawback of both these methods is that the primary current of the parallel cells flows through the entire busbar, which can lead to damage to the entire set of cells. Further, there is no way of limiting or arresting any faulty current. Further, using the plurality of busbars increases the complexity of the circuitry.
Further another method to ensure monitoring voltages of all the cells is to use individual voltage measurement devices with all the cells which are in parallel string. This would increase the number of active electronics to be used in the battery pack, resulting in increasing the weight, cost, and complexity of the battery pack.
Another approach in the prior art is to use electronic mechanisms, control circuits attached to each module to control the current and other parameters of the battery. However, this approach increases the cost of batteries as electronic components are costly. Further, the complexity of the circuit also increases.
Yet another approach is to use current sensors at midpoint and endpoint and using smart disconnecting units which are controlled by the algorithms run by the battery control unit. However, this approach also increases cost of the battery system, number of sensors to be used and overall cost of operation. Further, this approach does not help in preventing the primary current passing through the entire circuit as well as does not help in scaling of the battery pack design. Here also, as the number of components increases, the impedance and current imbalance in the circuitry increases.
Thus, there is this long-standing need for a system and method for managing module paralleling in a multi-cell battery management system for larger capacity cells, by avoiding parallel permanent connections. Further, it is required to keep the current imbalance as low as possible. Further, it is desired that the scalability and modularity of the parallel system must be enabled for battery packs, since the power requirements in the EV industry and many other applications are evolving day by day.
SUMMARY
This summary is provided to introduce concepts related to the field of cell/module paralleling in the battery assembly architecture, and more particularly, the present application discloses a battery assembly architecture with a fault management circuit. This summary is not intended to identify the essential features of the claimed subject matter nor is it intended for use in determining or limiting the scope of the claimed subject matter.
In one implementation, a battery pack assembly for managing module paralleling is disclosed. The assembly may comprise a plurality of battery modules arranged in a predetermined manner to form a battery pack. In a specific embodiment, the plurality of battery modules may be arranged in parallel to for the battery pack. Further, each battery module from the plurality of battery modules may comprise a plurality of cells arranged in a predetermined manner. In a specific embodiment, the plurality of cells may be arranged in a single series connection to form a battery module. Further, the assembly may comprise a plurality of harnesses and an interface printed circuit board (PCB). The interface PCB may comprise one or more cell connectors. Each cell connector from one or more cell connectors may be connected with a different battery module from the plurality of battery modules through the plurality of harnesses. Further, each cell connector from one or more connectors may comprise one or more poles. Furthermore, each pole from the one or more poles of a cell connector may be parallelly connected with each cell from the plurality of cells of a battery module corresponding to the cell connector through the plurality of harnesses.
In another implementation, a method for assembling a battery pack for managing module paralleling is disclosed. The method may comprise one or more steps of arranging a plurality of cells in a single series connection to form a battery module. Further, the method may comprise one or more steps of arranging a plurality of battery modules in a predetermined manner to form a battery pack. Further, the method may comprise one or more steps of connecting each module from the plurality of battery modules to a cell connector from one or more cell connectors of an interface PCB. Further, the method may comprise one or more steps of connecting each cell of each battery module parallelly with one or more poles of a corresponding cell connector of the interface PCB. Furthermore, the method may comprise one or more steps of connecting one or more poles of each cell connector from one or more cell connectors with one or more poles of another cell connector of the interface PCB through one or more conductive traces.
The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.
BRIEF DESCRIPTION OF DRAWINGS
The detailed description is described with reference to the accompanying figures. In the Figures, the left-most digit(s) of a reference number identifies the Figure in which the reference number first appears. The same numbers are used throughout the drawings to refer to the like features and components.
Figure 1 illustrates a block diagram of a battery pack assembly (100) for managing module paralleling, in accordance with an embodiment of the present subject matter.
Figure 2A illustrates a block diagram showing connections of one or more cell connectors (203) of an interface PCB (103) corresponding to a plurality of battery modules (102a, 102b), in accordance with an embodiment of the present subject matter.
Figure 2B illustrates a block diagram showing one or more cell connectors (203) with their corresponding one or more poles (P1, P2, P3, …, Pn), in accordance with an embodiment of the present subject matter.
Figure 3 illustrates a block diagram (300) of the battery pack assembly (100) with detailing of one or more conductive traces on the interface PCB (103), in accordance with an embodiment of the present subject matter.
Figure 4 illustrates a flowchart (400) describing a method for assembling a battery pack for managing module paralleling, in accordance with an embodiment of the present subject matter.
It should be noted that the accompanying figures are intended to present illustrations of exemplary embodiments of the present disclosure. These figures are not intended to limit the scope of the present disclosure. It should also be noted that accompanying figures are not necessarily drawn to scale.
DETAILED DESCRIPTION
Before the present system and method are described, it is to be understood that this disclosure is not limited to the system and its arrangement as described, as there can be multiple possible embodiments which are not expressly illustrated in the present disclosure. The present disclosure overcomes one or more shortcomings of the prior art and provides additional advantages discussed throughout the present disclosure. Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed disclosure. It is also to be understood that the terminology used in the description is for the purpose of describing the versions or embodiments only and is not intended to limit the scope of the present application.
The terms “comprise”, “comprising”, “include(s)”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, system or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or system or method. In other words, one or more elements in a system or apparatus preceded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or apparatus.
Reference throughout the specification to “various embodiments,” “some embodiments,” “one embodiment,” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in various embodiments,” “in some embodiments,” “in one embodiment,” or “in an embodiment” in places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the various embodiments disclosed herein, ‘a battery assembly’ may be interchangeably read and/or interpreted as ‘a battery module’ or ‘a battery pack’ ‘an energy storage system’ or ‘an energy storage apparatus’ or the like. Further, ‘an adhesive’ may be interchangeably read and/or interpreted as ‘a glue’ or ‘a sealant’ or the like. A ‘a battery cell’ may further be interchangeably read and/or interpreted as a ‘cell’ or a ‘storage cell’ or an ‘energy storage cell’ or an ‘energy storage device’ or the like.
Referring to Figure 1, a block diagram of a battery pack assembly (100) for managing module paralleling, is illustrated in accordance with an embodiment of the present subject matter. The block diagram illustrates a high-level view showing connections from a plurality of battery modules (101a, 101b) through a plurality of harnesses (102a (H1), 102b (H2)) to an interface PCB (103). The battery pack assembly (100) comprises a plurality of cells, the plurality of battery modules (101a, 101b), the plurality of harnesses (102a, 102b), and the interface printed circuit board (PCB) (103). The plurality of battery cells may be arranged in a predetermined manner to form a battery module (M1, M2). In a specific implementation, the plurality of cells may be arranged in a single serial connection to form the battery module (M1, M2). The plurality of battery modules (101a, 101b) are arranged in a predetermined manner to form a battery pack (201) (as illustrated in Figure 2). In a related implementation, the plurality of battery modules (101a, 101b) may be arranged in a parallel manner to form the battery pack (201). The one end of the plurality of harnesses (102a, 102b) may be connected to each cell of the plurality of cells of each battery module of the plurality of battery modules (101a, 101b). Further, the plurality of harnesses (102a, 102b) may be connected to the plurality of cells of the battery module using a connection method, such as but not limited to, bolting, soldering, welding, clamping or a combination thereof. The plurality of harnesses (102a, 102b) may correspond to the voltage sensing wires. In another embodiment, the plurality of cells in each module of the plurality of battery modules (101a, 101b) are in the same number. Further, the plurality of cells in each battery module may be connected to each other using a single series connection. In one embodiment, the plurality of cells comprise equal parameters of energy supply or storage such as, but not limited to, size, structure and chemical composition, voltage capacity or more. In a related embodiment, the plurality of cells, in the battery module, may be identical in their physical, electrical and energy content (with acceptable levels of tolerance and batching). Further one or more parameters of each cell of each battery module (M1) of the battery pack (201) are similar to the parameters of each cell in other battery modules (M2, …Mn) of the same battery pack (201).
In one embodiment, the interface PCB (103) may be formed from a material, such as but not limited to, glass-fibre (FR4 – rigid) or polyamide (flex) or a combination thereof. Further, the plurality of battery modules (101a, 101b) may be parallelly connected with the interface PCB (103) through the plurality of harnesses (102a, 102b). Further, the battery pack assembly (100) may comprise a plurality of PCBs, which may be configured to provide electrical and logical connections of various components of the battery back (201).
Now referring to the Figure 2A, a block diagram showing connections of one or more cell connectors (203) of the interface PCB (103) corresponding to the plurality of battery modules (102a, 102b), is illustrated in accordance with an embodiment of present subject matter. Along with the interface PCB (103) and the battery pack (201), the battery pack assembly (100) comprises a battery management system (BMS) (202).. The interface PCB (103) comprises one or more cell connectors (203) adapted to connect with a corresponding battery module from the plurality of battery modules (M1, M2, …, Mn). Further, each cell connector from the one or more cell connectors (203) may be connected with a different battery module from the plurality of battery modules (M1, M2, …, Mn) through the plurality of harnesses (102a, 102b). Further, each cell connector from one or more cell connectors (203) of the interface PCB (103) may be connected with the BMS (202). The number of cell connectors from the one or more cell connectors (203) in the interface PCB (103) is equal to the number of battery modules (M1, M2, …, Mn) in the battery pack (201). Furthermore, each cell connector, from one or more cell connectors (203), corresponding to a battery module is configured to be identical with other cell connectors corresponding to the other battery modules of the plurality of battery modules (102a, 102b).
In one non-limiting embodiment, the battery management system (BMS) (202) may be used to control the entire operation. Further, the battery pack assembly (100) may comprise a plurality of sensors such as temperature sensors, voltage and current sensors. Further, the plurality of sensors may continuously monitor the various parameters of the battery and send data to the BMS (202). The BMS (202) may further process the received data and generate orders to effectively control the operation of the battery and the vehicle. Further, the BMS (202) may be configured to send alerts to the vehicle users about any damage to the battery.
Referring to Figure 2B, a block diagram presenting one or more cell connectors (203) with their corresponding one or more poles (P1, P2, P3,…, Pn), is illustrated in accordance with an embodiment of present subject matter. Each cell connector (203a, 203b,…, 203n) comprises one or more poles (P1, P2, P3,…, Pn). Further, each pole from the one or more poles (P1, P2, P3,…, Pn) of a cell connector (C1) is parallelly connected with each cell of the battery module (M1) corresponding to the cell connector (C1) through the plurality of harnesses (102a, 102b). The number of poles in each cell connector (C1 or C2) is equal to the number of cells connected in each battery module (M1, M2) corresponding to the cell connector (C1 or C2). Further, the number of poles may be configured to be equal with the number of cells of a corresponding battery module for maintaining right connections of voltage and energy levels. Furthermore, the cell connector (C1) correspond to a battery module (M1) is identical with other cell connectors (C2, …, Cn) corresponding to other battery modules (M2, …, Mn) of the battery pack (201).
Now referring to Figure 3, a block diagram (300) of the battery pack assembly (100) with detailing of one or more conductive traces on the interface PCB (103), is illustrated in accordance with an embodiment of present subject matter. The block diagram (300) may comprise one or more cell connectors (203a, 203b, 203n), the interface PCB (103), the plurality of battery modules (101a, 101b) and the plurality of harnesses (102a, 102b). In one embodiment, the plurality of harnesses (102a, 102b) from the plurality of cells of the battery module from the plurality of battery modules (101a, 101b) may be connected to the plurality of poles (P1, P2, P3, …, Pn) of each cell connector from the one or more cell connectors (203a, 203b, …, 203n) of the interface PCB (103). Further, one or more poles (P1, P2, P3, …, Pn) of the cell connector (C1) may be connected with one or more poles (P1, P2, P3, …, Pn) of another cell connector (C2) of the interface PCB (103) through one or more conductive traces. Further, the one or more conductive traces may comprise copper traces or any other electric signal conductive material. In one embodiment, a width of the one or more conductive traces defined to be equivalent to a fusing current. The one or more conductive traces are designed to fuse a conductive trace in case of a current passes through the conductive trace, having a value greater than the fusing current. The fusing current may be calculated based on one or more, but not limited to, impedance difference in the parallel battery modules, an absolute magnitude of a primary current, impedance of the plurality of harnesses and the interface PCB (103) for the corresponding plurality of cells. In one embodiment, the primary current may correspond to a current that passes from the plurality of battery modules (101a, 101b) to a load and from the charger. In one embodiment, the fusing current may correspond to the current difference of the primary current with a tolerance stack up of impedance on each parallel plurality of harnesses (102a, 102b).
In another embodiment, a method of incorporating the one or more conductive traces on the interface PCB (103) may comprise following steps. At first step, a tolerance stacks up of impedances on each parallel plurality of harnesses (102a, 102b) may be identified. Further in the next step, a worst-case current difference between a primary current and impedance on each parallel string of harnesses may be calculated. Further in the next step, a fusing current for the interface PCB (103) may be identified by taking reference from the calculated worst-case current difference. The fusing current may be considered as an allowed current which can pass from the plurality of harnesses (102a, 102b) and the interface PCB (103). Further in the next step, one or more conductive traces are incorporated on the interface PCB (103). Further, width of the one or more conductive traces on the interface PCB (103) may be defined based on the identified fusing current. In one embodiment, one or more conductive traces are designed to be fused at the fusing current. In one embodiment, the one or more conductive traces may be designed to fuse a conductive trace once a current having a unit greater than the identified fusing current, passes through the one or more conductive traces via the plurality of harnesses. In another embodiment, the fusing of the conductive traces may occur due to battery module resistance either due to cell degradation or cell-to-cell interconnection failure. In both cases, the fusing of trace disconnects the parallel wire strings and prevents the faulty cell/connection from damaging other cells parallel to it.
In another embodiment, the interface PCB (103) may be configured to accommodate any number of battery modules (101a, 101b) in parallel, as long as the number of cells and the capacity of cells used in the parallel battery module are the same.
In an exemplary scenario, in case of degradation of either cell or module, may lead to unbalancing of the primary current path and the module impedance, which may cause the sharing of unequal current in the plurality of battery modules (101a, 101b), which in turn resulting in unequal current passing through the interface PCB (103), Thus the one of the corresponding conductive trace of the interface PCB (103) may get fuse to disconnect the current flowing through the whole interface PCB (103).
Now, after designing the interface PCB (103) based on the above calculation, module paralleling operation may be possible by the following method. In this method the BMS (202) may be continuously monitoring the current levels in the circuit using various sensors. Further, the current levels may be maintained as per design considerations. Now, if the current level crosses the fusing current level, the conductive traces may get fused. As soon as the traces get fused, the parallel strings of the faulty cell or connections may get disconnected. Because of this operation, the remaining cells and connections parallel to faulty connections may be prevented from any damage.
In another embodiment, the fusing current may comprise an imbalance current difference or worst current difference. In one embodiment, the fusing current may be calculated to limit the current allowed to be passing through the interface PCB (103). Further, the current passing through the interface PCB (103) may correspond to the fusing current. In another embodiment, the current passing through the plurality of harnesses (102a, 102b) may correspond to the fusing current. In one embodiment, the fusing current passes through the plurality of harnesses (102a, 102b) or the interface PCB (103) may be used to correct the difference in the primary current. In another embodiment, the plurality of harnesses (102a, 102b) may be configured to be of fixed cross section that may be configured to handle the calculated module current difference or fusing current. Further, a thickness of the one or more conductive traces may be defined to be equivalent to the fusing current. In another embodiment, the one or more conductive traces may be designed to be fused at the fusing current. In one embodiment, the one or more conductive traces may be designed to fuse a conductive trace once a current having a unit greater than the fusing current passes through the one or more conductive traces via the plurality of harnesses (102a, 102b). Further, the fusing of the conductive trace may enable to disconnect a parallel wire corresponding to a cell from the other plurality of parallel wires corresponding to the other cells. In another embodiment, the fusing of the conductive trace may prevent a faulty cell or connection from damaging other parallel cells in the battery module (201). Furthermore, the interface PCB (103) may be connected to the BMS (202).
Now referring to Figure 4, a flow diagram (400) describing a method for assembling a battery pack for managing module paralleling, is illustrated in accordance with an embodiment of the present subject matter. The method steps to be performed are as follows:
In step 401, the method (400) enables arranging a plurality of cells in a single series connection to form a battery module (101).
In step 402, the method (400) enables arranging a plurality of battery modules (101a, 101b) in a predetermined manner to form a battery pack (201).
In step 403, the method (400) enables connecting each module from the plurality of battery modules (101a, 101b) to a cell connector, from one or more cell connectors (203) of an interface PCB (103).
In step 404, the method (400) enables connecting each cell of each battery module (M1, M2, …, Mn) parallelly with one or more poles (P1, P2, P3, …, Pn) of a corresponding cell connector (C1, C2, …, Cn).
In step (405), the method (405) enables connecting one or more poles (P1, P2, P3, …Pn) of each cell connector (Cl) from one or more cell connectors (203a, 203b, …, 203n) with one or more poles (P1, P2, P3,…,Pn) of another cell connector (C2) of the interface PCB (103) through one or more conductive traces.
The embodiments illustrated above, especially related to a battery pack assembly (100) for managing module paralleling with current limiting interface PCB (103), may provide, but not limited to, following technical advancements:
• The interface PCB (103) can accommodate any number of battery modules in parallel as long as the number of series cells and capacity of cells used is the same.
• Currents through parallel battery modules do not get disproportionately distributed due to the interface PCB (103).
• Interchanging or swapping connections of Cell to PCB connector do not impact the functionality of the connections or the interface PCB (103).
• The system reduces the need for adding any active electronics for keeping each parallel battery module separate, thereby reducing the component count and hence number of failure modes.
• Reduces current imbalance in parallel modules which may be asymmetrical due to internal deviations from the nominal parameters.
• Increases serviceability of parallel modules by avoiding permanent connections.
• Increases modularity of the parallel system by enabling scalability by nominal change in the interface PCB (103). By nominal change in the PCB, the number of parallel connections can be increased as the system demands.
• The current limit can be increased and reduced by controlling the fusing current of the PCB by changing the trace thickness and width.
• The shape and size of the PCB and its integration with the parallel modules can be tuned based on system packaging design.
• Enables parallel cell connections in the battery assembly.
• Enables parallel module connections in the battery assembly.
• Series connected voltage supplies with parallel strings for supplying higher current.
Various modifications to the embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. However, one of ordinary skill in the art will readily recognize that the present disclosure is not intended to be limited to the embodiments illustrated but is to be accorded the widest scope consistent with the principles and features described herein.
The foregoing description shall be interpreted as illustrative and not in any limiting sense. A person of ordinary skill in the art would understand that certain modifications could come within the scope of this disclosure.
The embodiments, examples and alternatives of the preceding paragraphs or the description and drawings, including any of their various aspects or respective individual features, may be taken independently or in any combination. Features described in connection with one embodiment are applicable to all embodiments, unless such features are incompatible.
,CLAIMS:We Claim:
1. A battery pack assembly (100) for managing module paralleling, characterized in that, the battery pack assembly (100) comprises:
a plurality of battery modules (101a, 101b) arranged in a predetermined manner to form a battery pack (201), wherein each battery module from the plurality of battery modules (101) comprises a plurality of cells arranged in a predetermined manner;
a plurality of harnesses (102a, 102b); and
an interface printed circuit board (PCB) (103), wherein the interface PCB (103) comprises one or more cell connectors (203), wherein each cell connector from one or more cell connectors (203) is connected with a different battery module from the plurality of battery modules (101a, 101b), through the plurality of harnesses (102a, 102b);
wherein each cell connector from one or more cell connectors (203) comprises one or more poles (P1, P2, P3,…, Pn); wherein each pole from the one or more poles (P1, P2, P3,…, Pn) of a cell connector (C1) is parallelly connected with each cell from the plurality of cells of a battery module (M1) corresponding to the cell connector (C1), through the plurality of harnesses (102a, 102b).
2. The battery pack assembly (100) as claimed in claim 1, wherein one or more poles (P1, P2, P3,…, Pn) of a cell connector (C1), from one or more cell connectors (203) of the interface PCB (103), are connected with one or more poles (P1, P2, P3,…, Pn) of another cell connector (C2) of the interface PCB (103), through one or more conductive traces; wherein the one or more conductive traces may comprise copper traces.
3. The battery pack assembly (100) as claimed in claim 1, wherein number of poles in each cell connector (C1 or C2) is similar to the number of cells in corresponding battery module (M1, M2).
4. The battery pack assembly (100) as claimed in claim 1, wherein the battery pack assembly (100) comprises a battery management system (BMS) (202), wherein each cell connector, from one or more cell connectors (203) of the interface PCB (103), is connected with the BMS (202).
5. The battery pack assembly (100) as claimed in claim 1, wherein the plurality of battery modules (101a, 101b) is parallelly connected with the interface PCB (103), through the plurality of harnesses (102a, 102b).
6. The battery pack assembly (100) as claimed in claim 1,
wherein the plurality of cells, in each battery module, is connected to each other using a single series connection;
wherein number of cells in each battery module of the battery pack (201) are similar to the number of cells in other modules of the same battery pack (201);
wherein each cell from the plurality of cells in a battery module comprises one or more parameters from one of size of cells, structure of cells, chemical composition of cells, voltage capacity of cells, physical characteristics of cells, electrical characteristics of cells, energy content of cells, level of tolerance and a combination thereof;
wherein one or more parameters of each cell from the plurality of cells in the battery module are same;
wherein the parameters of one or more cells of each battery module (M1) of the battery pack (201) are similar to the parameters of one or more cells in other battery modules (M2, …Mn) of the same battery pack (201).
7. The battery pack assembly (100) as claimed in claim 1, wherein number of cell connectors (203) in the interface PCB (103) is equal to the number of battery modules (101a, 101b) in the battery pack (201); wherein a cell connector (C1) corresponding a battery module (M1) is identical with other cell connectors (C2,…Cn) corresponding to other battery modules (M2,…Mn) of the battery pack (201).
8. The battery pack assembly (100) as claimed in claim 1, wherein the plurality of harnesses (102a, 102b) corresponds to voltage sensing wires.
9. The battery pack assembly (100) as claimed in claim 1, wherein the battery pack assembly (100) comprises one or more PCBs, wherein one or more PCBs are configured to provide electrical and logical connections to multiple components of the battery pack assembly (100).
10. The battery pack assembly (100) as claimed in claim 2,
wherein width of one or more conductive traces is defined to be equivalent to a fusing current;
wherein one or more conductive traces is designed to fuse a conductive trace in case of a current, passes through the conductive trace, having a value greater than the fusing current;
wherein the fusing current is calculated based on one of impedance difference in the parallel battery modules (M1, M2, …Mn), an absolute magnitude of a primary current, impedance of the plurality of harnesses (102a, 102b) and the interface PCB (103), and a combination thereof;
wherein the primary current corresponds to a current pass from the plurality of cells/modules to a load and from a charger;
wherein the fusing current corresponds to a current difference of the primary current with a tolerance stack up of impedance on each parallel plurality of harnesses (102a, 102b).
11. A method (400) for assembling a battery pack (201) for managing module paralleling, characterized in that, the method (400) comprising:
arranging (401) a plurality of cells in a single series connection to form a battery module (101);
arranging (402) a plurality of battery modules (101a, 101b) in a predetermined manner to form a battery pack (201);
connecting (403) each module, from the plurality of battery modules (101a, 101b) to a cell connector, from one or more cell connectors (203) of an interface PCB (103);
connecting (404) each cell of each battery module (M1, M2, …Mn), parallelly with one or more poles (P1, P2, P3, …, Pn) of a corresponding cell connector (C1, C2, …Cn); and
connecting (405) one or more poles (P1, P2, P3, …, Pn) of each cell connector (C1), from one or more cell connectors (203a, 203b, …203n), with one or more poles (P1, P2, P3,…, Pn) of another cell connector (C2) of the interface PCB (103), through one or more conductive traces.
12. The method (400) as claimed in claim 11, the method (400) comprises incorporating one or more conductive traces on the interface PCB (103) by:
identifying tolerance stacks up of impedances on each parallel plurality of harnesses (102a, 102b);
calculating a worst-case current difference between a primary current and impedance on each parallel plurality of harnesses (102a, 102b);
identifying a fusing current for the interface PCB (103) by taking reference from the calculated worst-case current difference;
incorporating one or more conductive traces on the interface PCB (103), wherein width of one or more conductive traces is defined based on the identified fusing current, wherein one or more conductive traces is designed to fuse a conductive trace in case of a current, passes through the conductive trace, having a value greater than the fusing current.

Dated this 29th Day of March 2023