Claims:I/We claim:
1. A bio-plausible neuron (200) comprising:
a mode selection multiplexer (201),
a control multiplexer (101), and
a primitive spike generation circuit (102);
wherein the mode selection multiplexer (201) is connected to the control multiplexer (101), wherein the mode selection multiplexer (201) is configured to manage a mode of operation of the bio-plausible neuron (200) based on an input signal and a phasic input;
wherein the control multiplexer (101) is connected to the mode selection multiplexer (201) and the primitive spike generation circuit (102), wherein the control multiplexer (101) is configured to generate a control signal based on at least one of the mode of operation and the input signal;
wherein primitive spike generation circuit (102), wherein the primitive spike generation circuit (102) is configured to generate a spike pattern based on a supply voltage and the control signal.
2. The bio-plausible neuron (200), as claimed in claim 1, wherein generation of the spike pattern is controlled based on sizing of at least one transistor in the primitive spike generation circuit (102).
3. The bio-plausible neuron (200), as claimed in claim 1, wherein the bio-plausible neuron (200) operates in a phasic mode if the phasic input is high, wherein the bio-plausible neuron (200) operates in a bursting mode if the phasic input is low.
4. The bio-plausible neuron (200), as claimed in claim 1, wherein the control signal is generated based on the input signal, if the mode selection multiplexer (201) passes the input signal to the control multiplexer (101).
5. The bio-plausible neuron (200), as claimed in claim 3 and claim 4, wherein the mode selection multiplexer (201) passes the input signal to the control multiplexer (101) if the bio-plausible neuron (200) operates in the bursting mode.
6. The bio-plausible neuron (200), as claimed in claim 3 and claim 4, wherein the mode selection multiplexer (201) passes the input signal to the control multiplexer (101) if the bio-plausible neuron (200) operates in the phasic mode and if the input signal is low.
7. The bio-plausible neuron (200), as claimed in claim 1, wherein the control signal is low, if the mode selection multiplexer (201) blocks the input signal from reaching the control multiplexer (101).
8. The bio-plausible neuron (200), as claimed in claim 1 and claim 7, wherein the mode selection multiplexer (201) blocks the input signal from reaching the control multiplexer (101) if the bio-plausible neuron (200) operates in the phasic mode and if the input signal is high.
9. The bio-plausible neuron (200), as claimed in claim 1, wherein a value of the supply voltage is one of four predefined voltage values, wherein the four predefined voltage values are set based on a transistor technology used in the bio-plausible neuron (200).
10. The bio-plausible neuron (200), as claimed in claim 1, wherein the phasic input is high if value of the phasic input is 1.8 volts, wherein the phasic input is low if value of the phasic input is 0 volts, wherein the high phasic input and the low phasic input is achieved by applying either a fixed voltage or pulse trains with predefined duty cycles.
11. The bio-plausible neuron (200), as claimed in claim 1, wherein the input signal is high if value of the input signal is either 1.8 volts or 1 volt, wherein the input signal is low if value of the input signal is 0 volts, wherein the high input signal and the low input signal is achieved by applying either a fixed voltage or a pulse train with a predefined duty cycle.
12. A bio-plausible neuron (300) comprising:
a mode selection multiplexer (301), wherein the mode selection multiplexer (301) comprises a NAND gate (302) and a 2 x 1 multiplexer (303);
a control multiplexer (304), wherein the control multiplexer (302) is a 2 x 1 multiplexer; and
a primitive spike generation circuit (305), wherein the primitive spike generation circuit (305) comprises a first switch (306), a second switch (307), a first inverter (308), and a second inverter (309);
wherein the mode selection multiplexer (301) is connected to the control multiplexer (304), and configured to select, by the 2 x 1 multiplexer (303), a mode of operation of the bio-plausible neuron (300), wherein the selection is based on an input signal and a phasic input, wherein the input signal and the phasic input are provided as inputs to the NAND gate (302);
wherein the control multiplexer (304) is connected to the mode selection multiplexer (301) and the primitive spike generation circuit (305), wherein the control multiplexer (304) is configured to generate a control signal based on at least one of the mode of operation and the input signal;
wherein the primitive spike generation circuit (305), wherein the primitive spike generation circuit (305) is configured to generate a spike pattern based on a supply voltage and the control signal.
13. The bio-plausible neuron (300), as claimed in claim 12, wherein the bio-plausible neuron (300) operates in a phasic mode if the phasic input is high, wherein the bio-plausible neuron (200) operates in a bursting mode if the phasic input is low.
14. The bio-plausible neuron (300), as claimed in claim 12, wherein the control signal is generated based on the input signal if the control multiplexer (304) selects the output of the mode selection multiplexer (301), wherein the control multiplexer (304) selects the output of the mode selection multiplexer (301) if the 2 x 1 multiplexer (303) selects the input signal.
15. The bio-plausible neuron (300), as claimed in claim 13 and claim 14, wherein the 2 x 1 multiplexer (303) selects the input signal if either a first condition or a second condition is satisfied; wherein the first condition is satisfied if the bio-plausible neuron (200) operates in the bursting mode, wherein the second condition is satisfied if the bio-plausible neuron (200) operates in the phasic mode and the input signal is low.
16. The bio-plausible neuron (300), as claimed in claim 12, wherein the control signal is low, if the control multiplexer (304) selects a signal connected to a ground; wherein the control multiplexer (304) selects the signal connected to a ground if the 2 x 1 multiplexer (303) selects the ground signal.
17. The bio-plausible neuron (300), as claimed in claim 13 and claim 16, wherein the 2 x 1 multiplexer (303) selects the signal connected to the ground if the bio-plausible neuron (300) operates in the phasic mode and if the input signal is high.
18. The bio-plausible neuron (300), as claimed in claim 12, wherein down strokes are generated in the spike pattern if the first switch (306) is turned ON, wherein the first switch (306) is turned ON if the control signal is low.
19. The bio-plausible neuron (300), as claimed in claim 18, wherein an output of the first switch (306) is high when the first switch (306) is turned ON, wherein the second inverter (309) inverts the output of the first switch (306) to generate the down strokes.
20. The bio-plausible neuron (300), as claimed in claim 12, wherein upstrokes are generated in the spike pattern if the second switch (307) is turned ON, wherein the second switch (307) is turned ON if the control signal is high, wherein an inverted version of the control signal is generated by the first inverter (308) to turn ON the second switch (307).
21. The bio-plausible neuron (300), as claimed in claim 20, wherein an output of the second switch (307) is low when the second switch (307) is turned ON, wherein the second inverter (309) inverts the output of the second switch (307) to generate the upstrokes.
22. The bio-plausible neuron (300), as claimed in claim 12, wherein the phasic input is high if value of the phasic input is 1.8 volts, wherein the phasic input is low if value of the phasic input is 0 volts, wherein the high phasic input and the low phasic input is achieved by applying either a fixed voltage or a pulse train with a predefined duty cycle, wherein selection of application of either the fixed voltage or the pulse train is performed using an input provided to a multiplexer.
23. The bio-plausible neuron (300), as claimed in claim 12, wherein the input signal is high if value of the input signal is either 1.8 volts or 1 volt, wherein the input signal is low if value of the input signal is 0 volts, wherein the high input signal and the low input signal is achieved by applying either of a fixed voltage or a pulse train with a predefined duty cycle.
24. The bio-plausible neuron (300), as claimed in claim 12, wherein a value of the supply voltage is one of four predefined voltage values, wherein selection of one of the four predefined voltage values is performed using a 4 x 1 multiplexer.
25. A bio-plausible neuron (200) comprising:
a mode selection multiplexer (201), wherein the mode selection multiplexer (201) comprises a first inverter, a first transmission gate, and a second transmission gate;
a control multiplexer (101), wherein the control multiplexer (101) comprises a second inverter, a third transmission gate, and a fourth transmission gate; and
a primitive spike generation circuit (102), wherein the primitive spike generation circuit (102) comprises a first switch, a second switch, a third inverter, and a fourth inverter;
wherein the mode selection multiplexer (201) is connected to the control multiplexer (101), wherein an input signal at the first inverter allows selection of a mode of operation of the bio-plausible neuron (200), wherein the input signal at the first inverter is generated based on an input signal and a phasic input;
wherein the control multiplexer (101) is connected to the mode selection multiplexer (201) and the primitive spike generation circuit (102), wherein the control multiplexer (101) generates a control signal based on at least one of the input signal and a selection of either the first transmission gate or the second transmission gate;
wherein primitive spike generation circuit (102), wherein the primitive spike generation circuit (102) is configured to generate a spike pattern based on a supply voltage and the control signal.
26. The bio-plausible neuron (200), as claimed in claim 25, wherein the bio-plausible neuron (200) operates in a phasic mode if the phasic input is high, wherein the bio-plausible neuron (200) operates in a bursting mode if the phasic input is low.
27. The bio-plausible neuron (200), as claimed in claim 25, wherein an output signal at the first inverter controls the selection of either the first transmission gate or the second transmission gate;
wherein the first transmission gate is selected if the output signal at the first inverter is high, wherein the output signal at the first inverter is high if the input signal is high and the phasic input is high;
wherein the second transmission gate is selected if the output signal at the first inverter is low, wherein the output signal at the first inverter is low if at least one of: the input signal is high and the phasic input is low, input signal is low and the phasic input is low, and the input signal is low and the phasic input is high.
28. The bio-plausible neuron (200), as claimed in claim 27, wherein the control signal is low if the control signal is generated if the first transmission gate is selected.
29. The bio-plausible neuron (200), as claimed in claim 27, wherein the control signal is generated based on the input signal if the second transmission gate is selected.
30. The bio-plausible neuron (200), as claimed in claim 25, wherein a value of the supply voltage is one of four predefined voltage values, wherein the four predefined voltage values are set based on a transistor technology used in the bio-plausible neuron (200).
31. The bio-plausible neuron (200), as claimed in claim 25, wherein the control signal is provided as an input to the first switch and an inverted version of the control signal is provided to the second switch, wherein the third inverter generates the inverted version of the control signal.
32. The bio-plausible neuron (200), as claimed in claim 31, wherein output of the first switch is high when the first switch is turned ON, wherein the first switch is turned ON if the control signal at the input of the first switch is low, wherein the output of the first switch is inverted by the fourth inverter to generate down strokes in the spike pattern.
33. The bio-plausible neuron (200), as claimed in claim 31, wherein output of the second switch is low when the second switch is turned ON, wherein the second switch is turned ON if the inverted version of the control signal at the input of the second switch is low, wherein the output of the second switch is inverted by the fourth inverter to generate upstrokes in the spike pattern.
34. The bio-plausible neuron (200), as claimed in claim 25, wherein the phasic input is high if value of the phasic input is 1.8 volts, wherein the phasic input is low if value of the phasic input is 0 volts, wherein the high phasic input and the low phasic input is achieved by applying either a fixed voltage or pulse trains with predefined duty cycles.
35. The bio-plausible neuron (200), as claimed in claim 25, wherein the input signal is high if value of the input signal is either 1.8 volts or 1 volt, wherein the input signal is low if value of the input signal is 0 volts, wherein the high input signal and the low input signal is achieved by applying either a fixed voltage or a pulse train with a predefined duty cycle.
36. The bio-plausible neuron (200), as claimed in claim 25, wherein generation of the spike pattern is controlled based on sizing of at least one transistor in the primitive spike generation circuit (102).
, Description:TECHNICAL FIELD
Embodiments herein relate to neuromorphic computing, and more particularly to electronic circuits that model bio-plausible neurons, which can generate spiking patterns mimicking biological neurons.

BACKGROUND
Currently, bio-plausible neurons are modeled based on equations, which include differentials and integrals. In order to implement the differentials and integrals, capacitors are used. The capacitors can occupy a significant portion of chip area. In order to perform machine learning operations or operations which require artificial intelligence capability, a neuromorphic chip or computing equipment needs to include innumerable neurons. Since the inclusion of capacitances in the neuromorphic chip or computing equipment consumes significant chip area, the number of neurons that can be included in the neuromorphic chip or computing equipment is reduced. This prevents utilization of the bio-plausible neurons for performing the machine learning operations.

OBJECTS
The principal object of the embodiments herein is to disclose a bio (biological)-plausible neuron, which can be employed in neural networks or architectures for performing machine learning operations and operations requiring artificial intelligence capability.
Another object of the embodiments herein is to utilize electronic circuits for modeling the bio-plausible neuron (neuron circuit), wherein the neuron circuit can generate spike trains (which mimic the responses of biological neurons) of a plurality of varieties (patterns) based on variation of input parameters and an input signal fed to the neuron circuits.
Another object of the embodiments herein is to optimize the neuron circuit by employing a minimum number of transistors for generating the spikes, wherein the optimization allows increasing the number of neuron circuits that can be included in a neuromorphic chip, wherein increasing the number of neuron circuits allows utilizing the neuromorphic chip for performing machine learning operations of high complexity.
Another object of the embodiments herein is to enable the neuron circuit to generate specific spiking patterns at runtime based on specific requirements.

SUMMARY
Accordingly, the embodiments provide multi-type spike generating neuron circuit for modeling a bio-plausible neuron. The spike generating neuron circuit is an electronic circuit, which can be employed as neurons in neural network processors for performing neuromorphic computing, machine learning operations, and/or tasks requiring artificial intelligence capabilities. The multi-type spike generating neuron circuit can mimic the responses of biological neurons. In an embodiment, the components of the multi-type spike generating neuron circuit can employ signal shaping techniques for obtaining the multi-type spiking output.
In an embodiment, the multi-type spike generating neuron circuit includes a control multiplexer and a primitive spike generation circuit. The control multiplexer and a primitive spike generation circuit comprises of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The primary functionality of the control multiplexer is to allow or block an input signal, at the input terminals of the multi-type spike generating neuron circuit, from passing on to the primitive spike generation circuit. The selection of whether to allow or block the input signal is based on the type of spiking train that is intended by a user and the output of the multi-type spike generating neuron circuit. The primitive spike generation circuit is a signal shaping circuit, which allows generating a particular pattern of spiking train based on input parameters and the input signal, wherein one of the input parameters is the type of spike that needs to be generated.
When a specific input signal is provided to the multi-type spike generating neuron circuit, the control multiplexer and the primitive spike generation circuit form a push-pull loop system, which generates an output spiking train, which mimics the response of a biological neuron. The spiking pattern at the output of the multi-type spike generating neuron circuit can be controlled by appropriately sizing the MOSFETs and/or logic gates in the multi-type spike generating neuron circuit. These MOSFETs assist in generating the desired spiking patterns.
These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.

BRIEF DESCRIPTION OF FIGURES
Embodiments herein are illustrated in the accompanying drawings, through out which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the drawings, in which:
FIG. 1 depicts a multi-type spike generating neuron circuit, according to embodiments as disclosed herein;
FIG. 2 depicts a multi-type spike generating neuron circuit with phasing and burst mode selection capability, according to embodiments as disclosed herein;
FIG. 3 depicts a digital equivalent circuit of the multi-type spike generating neuron circuit with phasing and burst mode selection capability, according to embodiments as disclosed herein;
FIG. 4 is a block level depiction of the multi-type spike generating neuron circuit with phasing and burst mode selection capability, according to embodiments as disclosed herein;
FIG. 5 depicts a block level representation of the multi-type spike generating neuron circuit for generating specific spiking patterns at runtime, according to embodiments as disclosed herein; and
FIGS. 6a-6j are graphs depicting the generation of different spike patterns using the multi-type spike generating neuron circuit, according to embodiments as disclosed herein.

DETAILED DESCRIPTION
The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
Embodiments herein disclose electronic circuits for modeling bio-plausible neurons, which mimic responses of biological neurons. The bio-plausible neurons are employed in neural networks for performing artificial intelligence and machine learning operations. The bio-plausible neuron models can generate spikes of multiple varieties based on variation of input parameters specifying a specific type or pattern of spike that needs to be generated and input signals. The bio-plausible neuron models are optimized using a minimum number of transistors for increasing the number of neurons that can be in a neuromorphic chip, which in turn allows utilizing the neuromorphic chip for performing machine learning operations of high complexity. The bio-plausible neuron models generate specific types of spiking patterns at runtime based on specific requirements.
Referring now to the drawings, and more particularly to FIGS. 1 through 6, where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments.
FIG. 1 depicts a multi-type spike generating neuron circuit 100, according to embodiments as disclosed herein. The multi-type spike generating neuron circuit 100 can be employed as a neuron in a neural network. The multi-type spike generating neuron circuit 100 can be considered as a model of a bio-plausible neuron. The different types (patterns) of spikes generated by the multi-type spike generating neuron circuit 100 can mimic the responses of biological neurons. As depicted in FIG. 1, the multi-type spike generating neuron circuit 100 comprises a control multiplexer 101 and a primitive spike generation circuit 102. The combination of the control multiplexer 101 and the primitive spike generation circuit 102 is the basic building block of a neuron circuit, which can be used in a neural network for performing neuromorphic computing, machine learning, and artificial intelligence operations.
The elements of the multi-type spike generating neuron circuit 100 comprises of a plurality of p-type and n-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). In an embodiment, the multi-type spike generating neuron circuit 100 comprises of 12 MOSFETs. The control multiplexer 101 includes a MP-1 MOSFET (MP signifies p-type MOSFET), a MN-1 MOSFET (MN signifies n-type MOSFET), a MP-2 MOSFET, MN-2 MOSFET, a MP-3 MOSFET, and a MN-3 MOSFET. The MP-1 MOSFET and the MN-1 MOSFET pair act as an inverter.
The input to the inverter is a signal SW. The signal SW is actually the output of the primitive spike generation circuit 102, i.e., Voutp. The inverted version of the SW (SW bar) is fed to the MP-2 MOSFET and the MN-2 MOSFET pair (transmission gate), and the MP-3 MOSFET and the MN-3 MOSFET pair (transmission gate). The select lines of the control multiplexer 101 are the MP-2 MOSFET and the MN-2 MOSFET pair, and the MP-3 MOSFET and MN-3 MOSFET pair. Thus, the control multiplexer 101 can be interpreted as a 2 x 1 multiplexer.
The primary functionality of the control multiplexer 101 is to allow a signal Vin, at the input of the multi-type spike generating neuron circuit 100, to pass to the primitive spike generation circuit 102. If the inverted version of the SW signal is high, then the pair of MP-3 MOSFET and the MN-3 MOSFET is selected. The MP-3 MOSFET and the MN-3 MOSFET pass the input signal to the primitive spike generation circuit 102. On the other hand, if the inverted version of the SW signal is low, then the pair of MP-2 MOSFET and the MN-2 MOSFET is selected. This blocks the input signal from reaching the primitive spike generation circuit 102, thereby isolating the primitive spike generation circuit 102 from the control multiplexer 101.
The primitive spike generation circuit 102 includes a MP-4 MOSFET, a MN-4 MOSFET, a MP-5a MOSFET, MP-5b MOSFET, a MP-7 MOSFET, and a MN-7 MOSFET. The MP-4 MOSFET and the MN-4 MOSFET pair act as an inverter. The MP-7 MOSFET and the MN-7 MOSFET pair act as an inverter. The signal at the input of the primitive spike generation circuit 102 is the CNT signal. Considering the behavior of the control multiplexer 101, the input signal, Vin, is the CNT signal when the pair of MP-3 MOSFET and the MN-3 MOSFET is selected based on the output of the primitive spike generation circuit 102. The output of the primitive spike generation circuit 102, i.e., Voutp, is provided as an input to the control multiplexer 101, which in turn passes the input signal Vin to the primitive spike generation circuit 102.
When the multi-type spike generating neuron circuit 100 receives a specific input, i.e., Vin, the control multiplexer 101 and the primitive spike generation circuit 102 form a push-pull loop system. The push-pull loop system generates an output spike train, which mimics the response of a biological neuron. The output spike train can be represented as VSPIKE, which is the neuron output. The output of the primitive spike generation circuit 102, i.e., Voutp, is the inverted version of the output spike train. The neuron spike pattern can be controlled by appropriate sizing the MP-4, MN-4, MP-5a, MP-5b, MP-7, and MN-7 MOSFETs. The MOSFETs allow creating the desired spike patterns. In an embodiment, the size of the p-type MOSFETs (MP-4, MP-5a, MP-5b and MP-7) in the primitive spike generation circuit 102 is at least double, compared to size of the n-type MOSFETs (MN-4 and MN-7. The size of the MOSFETs (p-type and n-type)can be chosen based on frequency response required for a particular manufacturing technology node.
When the CNT signal is high, the MOSFET MP-5a is OFF and the MOSFET MP-5b is ON. It is to be noted that the MOSFET MP-5a is OFF and the MOSFET MP-5b act as switches and are operating in the saturation region and the cut-off region. The input to the MOSFET MP-5b is an inverted version of the CNT signal, as the CNT signal passes through the inverter comprising of the MP-4 MOSFET and the MN-4 MOSFET pair. When the MOSFET MP-5a is OFF and the MOSFET MP-5b is ON, the output of the primitive spike generation circuit 102, i.e., Voutp, is low. Correspondingly, the VSPIKE will be high. This is because the output of the primitive spike generation circuit 102 is inverted by the inverter comprising of the MP-7 MOSFET and the MN-7 MOSFET pair.
In an embodiment, the operation of the multi-type spike generating neuron circuit 100 can be described by considering that VSPIKE is low. When VSPIKE is low, the output of the primitive spike generation circuit 102, i.e., Voutp, is high. When Voutp, is ‘high’, Voutp is VDD. If Voutp is VDD, it is implied that the MOSFET MP-5a is ON and the MOSFET MP-5b is OFF. The MOSFET MP-5a and the MOSFET MP-5b cannot be ON or OFF at the same time as the signals at the input terminals of the MOSFET MP-5a and the MOSFET MP-5b are complimentary to each other. It is to be noted that the actual voltage at the output of the primitive spike generation circuit 102 (Voutp) is close to VDD (rather than VDD).
When Voutp is VDD, the lower path of the control multiplexer 101 is selected. This is because the signal SW is Voutp. The signal is inverted by the MOSFET MP-1 and the MOSFET MN-1. Therefore, the MOSFETs in the lower path (comprising of MOSFETs MP-3 and MN-3) of the control multiplexer 101 are selected (turned ON). Thus, the signal at the input terminal of the multi-type spike generating neuron circuit 100, Vin, is passed to the primitive spike generation circuit 102 through the MOSFETs in the lower path. This implies that the multi-type spike generating neuron circuit 100, i.e., the bio-plausible neuron is polling for the input.
The above mentioned states of the MOSFETs can be retained until there is no signal at the input terminal of the multi-type spike generating neuron circuit 100, i.e., Vin is 0. When the voltage at the input terminal of the multi-type spike generating neuron circuit 100 is high, i.e., Vin is VDD, the voltage at the input terminal of the primitive spike generation circuit 102, i.e., CNT, is VDD; When CNT is VDD, the MOSFET MP-5a is switched OFF and the MOSFET MP-5b is switched ON. However, the MOSFET MP-5b may not detect the change (transition of CNT from 0 to VDD) at its input terminal. This is because, the signal CNT has to pass through the inverter comprising of the MOSFET MP-4 and the MOSFET MN-4. Therefore, for a small time period, which is the propagation delay of the inverter, the MOSFET MP-5a and the MOSFET MP-5b are switched OFF.
In an embodiment, the time period is the propagation delay of the MOSFET MP-4 and the MOSFET MN-4 and a fall time of the inverter comprising of the MOSFET MP-4 and the MOSFET MN-4. The fall time is the time period required for the voltage at the output of the inverter, comprising of the MOSFET MP-4 and the MOSFET MN-4, to fall from the voltage VDD to 0. Once the MOSFET MP-5b is switched ON, and a discharge path is created through the drain and source terminals of the MOSFET MP-5b, the voltage at the output terminal of the primitive spike generation circuit 102, Voutp, falls from VDD to 0. When the output of the primitive spike generation circuit 102 is low or the voltage at the output terminal of the primitive spike generation circuit 102 is 0 (close to 0), the VSPIKE transitions from 0 to VDD. The transition of VSPIKE from 0 to VDD represents the UP STROKE of a spike at the output terminal of the multi-type spike generating neuron circuit 100.
When Voutp transitions from VDD to 0, the signal SW is low. As signal SW is inverted by the MOSFET MP-1 and the MOSFET MN-1, the, the MOSFETs in the upper path of the control multiplexer 101, i.e., MOSFET MP-2 and MOSFET MN-2 are selected. Thus, the signal at the input terminal of the multi-type spike generating neuron circuit 100 is isolated from the primitive spike generation circuit 102 and the signal CNT is low (voltage at the input terminal of the primitive spike generation circuit 102 is 0).
Therefore, the MOSFET MP-5a is switched ON and the MOSFET MP-5b is switched OFF. Therefore, the MOSFET MP-5a creates a path through its source and drain terminals for charging the output of the primitive spike generation circuit 102. Thus, the voltage at the output terminals of the primitive spike generation circuit 102 is VDD, i.e., Voutp is VDD. However, the voltage at the output terminals of the primitive spike generation circuit 102 is not pulled to VDD immediately, as the MOSFET MP-5b is not switched OFF due to the propagation delay of the inverter comprising of the MOSFET MP-4 and the MOSFET MN-4 and a rise time of the inverter comprising of the MOSFET MP-4 and the MOSFET MN-4. The rise time of the inverter is a time period required for the voltage at the output of the inverter to rise from 0 to VDD. During this time period, the MOSFET MP-5a and the MOSFET MP-5b are ON.
When the MOSFET MP-5b is switched OFF, and the charging path is created through the drain and source terminals of the MOSFET MP-5a, the voltage at the output terminal of the primitive spike generation circuit 102 rises from 0 to VDD. When the output of the primitive spike generation circuit 102 is high or the voltage at the output terminal of the primitive spike generation circuit 102 is VDD (close to VDD), the VSPIKE transitions from VDD to 0. The transition of VSPIKE from VDD to 0 represents the DOWN STROKE of the spike at the output of the multi-type spike generating neuron circuit 100.
The operation of the multi-type spike generating neuron circuit 100 can be depicted in a state table as follows:
State Vin SW CNT MP5a MP5b Voutp VSPIKE
A 0 0 0 (GND) ON OFF 1 0
B 0 1 0 (Vin) ON OFF 1 0
C 1 1 1 (Vin) OFF ON 1?0 0?1
D 1 0 0 (GND) ON OFF 0?1 1?0
Table 1: State table of the multi-type spike generating neuron circuit 100
When Vin is 0, the multi-type spike generating neuron circuit 100 stays in a stable and constant state B with Voutp at 1 (VDD or high) and VSPIKE at 0 (GND or low). If the multi-type spike generating neuron circuit 100 is initially at state A, there will be a transition to state B. This is because Voutp is forced to 1 when SW is 0. Thereafter, SW is forced to 1. Since Vin is 0, the multi-type spike generating neuron circuit 100 remains in state B, until Vin is set to 1.
When Vin set to 1, feedback state of the multi-type spike generating neuron circuit 100 is activated. The multi-type spike generating neuron circuit 100 moves from state B to state C. Since SW is 1, Vin is propagated to CNT. Hence, CNT is 1. This can turn MP-5a OFF and MP-5b ON. The Voutp transits from 1 to 0. This forces SW to 0, thereby switching the multi-type spike generating neuron circuit 100 from state C to state D. Since SW is 0, the Vin is not propagated to CNT. Hence, CNT is GND. This can turn MP-5a ON and MP-5b OFF. The Voutp transits from 0 to 10. This forces SW to 1, thereby switching the multi-type spike generating neuron circuit 100 from state D to state C.
The Voutp and VSPIKE can switch between 0 and 1. As long as Vin is set to 1, the switching continues. The 0?1 transition in VSPIKE represents an upstroke of a neuron and the 1?0 transition in VSPIKE represents a down stroke of the neuron.
The inverter comprising of the MOSFET MP-4 and the MOSFET MN-4 is the primary spike shaping element in the bio-plausible neuron model. The design of the MOSFETs MP-4 and MN-4 prevents instantaneous transitions in VSPIKE from VDD to 0 or from 0 to VDD. The design involves appropriate sizing of the MOSFETs MP-4 and MN-4 of the inverter, which is necessary for ensuring that the multi-type spike generating neuron circuit 100 can generate a spike train with a desired spike shape.
It may be noted that the voltage at the output terminals of the primitive spike generation circuit 102 and the voltage at the output terminals of the multi-type spike generating neuron circuit 100 is lower than VDD as most of the elements (MOSFETs) in the control multiplexer 101 and the primitive spike generation circuit 102 are not able to undergo a full-output voltage swing between VDD and 0. This can act as an advantage to the bio-plausible neuron model (multi-type spike generating neuron circuit 100), as the switching power of the overall bio-plausible neuron model is reduced.
The refractory period of the neuron (bio-plausible neuron), which defines the time interval between consecutive spikes is controlled by an inherent propagation delay of the control multiplexer 101 circuit. Therefore, the spiking frequency that can be obtained using the obtained with multi-type spike generating neuron circuit 100 can be maximized for the circuitry for any manufacturing technology node. The spiking frequency can also be reduced, if necessary, by using varactor elements. The multi-type spike generating neuron circuit 100 can be considered as a basic model of the bio-plausible neuron to generate neuron responses of multiple types.
FIG. 2 depicts a multi-type spike generating neuron circuit 200 with phasing and burst mode selection capability, according to embodiments as disclosed herein. The multi-type spike generating neuron circuit 200 includes the components of the multi-type spike generating neuron circuit 100. Additionally, the multi-type spike generating neuron circuit 200 includes a multiplexer and a NAND gate. The combination of the multiplexer and the NAND gate can be considered as a mode selection multiplexer 201. The mode selection multiplexer 201 can be used for enabling the multi-type spike generating neuron circuit 200 to operate in a particular mode, and, thereby, allow generating a particular type of output spike response. The multi-type spike generating neuron circuit 200 includes the control multiplexer 101 and the primitive spike generation circuit 102. The operation and functionality of the control multiplexer 101 and the primitive spike generation circuit 102, in the multi-type spike generating neuron circuit 200, is identical to that discussed in FIG. 1. The mode selection multiplexer 201 can enable the multi-type spike generating neuron circuit 200 to operate in the phasic mode or the burst mode. Therefore, the multiplexer 201 can be referred to as a phasic/burst mode select multiplexer 201.
The mode selection multiplexer 201 can be considered as a 2 x 1 multiplexer. The select line allows selecting the phasic mode or the burst mode of operation. In an embodiment, the phasic/burst mode select multiplexer 201 includes a plurality of n-type and p-type MOSFETs. As depicted in FIG. 2, the mode selection multiplexer 201 includes an inverter comprising of a MOSFET MP-8 and a MOSFET MN-8. The select line enables a MOSFET MP-9 and a MOSFET MN-9 pair (transmission gate) or a MOSFET MP-10 and a MOSFET MN-10 pair (transmission gate). The select line signal is an inverted version of a MODE signal.
The inputs to the NAND gate are a control phasic input signal PHASIC and an input signal. The output of the NAND gate is the MODE signal. The input signal Vin can be provided to the control multiplexer 101 and the primitive spike generation circuit 102 of the multi-type spike generating neuron circuit 200 through the mode selection multiplexer 201. When the signal PHASIC is low, the operation of the multi-type spike generating neuron circuit 200 is reduced to that of the multi-type spike generating neuron circuit 100. When the signal PHASIC is low, the output of the NAND gate is always high, irrespective of the state of the input signal Vin. The output of the NAND gate, i.e., the MODE signal, is high.
When the MODE signal is high, the output of the inverter, comprising of the MOSFET MP-8 and the MOSFET MN-8, will be low. As such, the pair of MOSFET MP-10 and the MOSFET MN-10 is selected. Thus, the input signal Vin is propagated to the control multiplexer 101 and the primitive spike generation circuit 102. Thus, in this scenario (PHASIC is low) the operation of the multi-type spike generating neuron circuit 200 is reduced to that of the multi-type spike generating neuron circuit 100. The multi-type spike generating neuron circuit 200 can generate a regular bursting or spiking pattern.
When the signal PHASIC is high and the input signal Vin is low, the operation of the multi-type spike generating neuron circuit 200 is reduced to that of the multi-type spike generating neuron circuit 100. This is because the output of the NAND gate will continue to be high, as long as the input signal Vin is low. The multi-type spike generating neuron circuit 200 will operate in the state B of the multi-type spike generating neuron circuit 100, wherein Vin is low (0). When the signal PHASIC is high and the input signal Vin is high, the output of the NAND gate, i.e., the MODE signal, will be low. When the MODE signal is low, the output of the inverter, comprising of the MOSFET MP-8 and the MOSFET MN-8, will be high. As such, the pair of MOSFET MP-9 and the MOSFET MN-9 is selected. The output of the mode selection multiplexer 201 will be low and the input signal Vin will not be propagated to the control multiplexer 101 and the primitive spike generation circuit 102. This is because the mode selection multiplexer 201 blocks the input signal Vin when the MODE signal is low.
PHASIC Vin MODE MODE
(Compliment) OUTPUT of 201 OPERATION MODE
0 0 1 0 Vin BURSTING
0 1 1 0 Vin BURSTING
1 0 1 0 Vin PHASIC
1 1 0 1 GND (0) PHASIC
Table 2: Truth Table of operation of multi-type spike generating neuron circuit 200
Based on the truth table, the following relationships can be derived:
Equation 1: MODE=(PHASIC.VIN) ¯
Equation 2: Output (201)=PHASIC.MODE+ VIN.(MODE) ¯
However, when the signal PHASIC is high and the input signal Vin transitions from low to high, the input signal Vin will be propagated to the control multiplexer 101 and the primitive spike generation circuit 102 for a small time period. The time period is equal to the propagation delay of the NAND gate and the fall time of the output of the NAND gate to fall from high to low. During this time period, the pair of MOSFET MP-10 and the MOSFET MN-10 will continue to be selected. Until the output of the NAND gate becomes low, i.e., the MODE signal becomes low, the input signal Vin will be propagated to the control multiplexer 101 and the primitive spike generation circuit 102. When the pair of MOSFET MP-9 and the MOSFET MN-9 is selected after the time period (propagation delay), the input signal Vin is blocked. Thus, Vin is propagated to the primitive spike generation circuit 102 for a short time period. The time period can be dictated by the propagation delay for transformation of Vin from low to high. The transformation produces phasic spiking behavior of neurons.
FIG. 3 depicts a digital equivalent circuit 300 of the multi-type spike generating neuron circuit 200 with phasing and burst mode selection capability, according to embodiments as disclosed herein. The functionality and the operation of the digital equivalent circuit 300 are identical to that of the multi-type spike generating neuron circuit 200. As depicted in FIG. 3, the digital equivalent circuit includes a NAND gate 302, a first 2 x 1 multiplexer 303, a second 2 x 1 multiplexer 304, a first switch 306, a second switch 307, a first inverter 308, a second inverter 309, and a voltage supply (VDD). The first 2 x 1 multiplexer 303 is an equivalent of the mode selection multiplexer 201. The first 2 x 1 multiplexer 303 performs the functionalities of the MOSFET MP-8, the MOSFET MN-8, the MOSFET MP-9, the MN-9, the MOSFET MP-10, and the MOSFET MN-10. The second 2 x 1 multiplexer 304 is an equivalent of the control multiplexer 101. The second 2 x 1 multiplexer 304 performs the functionalities of the MOSFET MP-1, the MOSFET MN-1, the MOSFET MP-2, the MOSFET MN-2, the MOSFET MP-3, and the MOSFET MN-3.
The first inverter 308, the first switch 306 (labeled as SWITCH 1) and the second switch 307 (labeled as SWITCH 2) and the second inverter 309, are equivalent of the primitive spike generation circuit 102. The first switch 306, the second switch 307, the first inverter 308, and the second inverter 309, can be an considered as a primitive spike generation circuit 305. The first inverter 308 is an equivalent of the MOSFET MP-4, and the MOSFET MN-4. The first switch 306 is an equivalent of the MOSFET MP-5a and the second switch 307 is an equivalent of the MOSFET MP-5b. The second inverter 309 is an equivalent of comprises the MOSFET MP-7 and the MOSFET MN-7. The voltage supply is the voltage VDD.
FIG. 4 is a block level depiction of the multi-type spike generating neuron circuit 200 with phasing and burst mode selection capability, according to embodiments as disclosed herein. As depicted in FIG. 4, the NEURON block can be considered as either the multi-type spike generating neuron circuit 200 (depicted in FIG. 2) or the digital equivalent circuit 300 of the multi-type spike generating neuron circuit 200 (depicted in FIG. 3). Additionally, a VDD scaling block and a pulse generator unit can be employed. The VDD scaling block can scale the supply voltage of the multi-type spike generating neuron circuit 200. The VDD scaling block can scale the supply voltage at four predefined levels. The four predefined levels can be set based on the technology (nanometer). The pulse generator unit can generate pulses, which can be provided as the control phasic input signal PHASIC to the NAND gate of the multi-type spike generating neuron circuit 200. The pulses can be a fixed voltage or a pulse train, wherein duty cycle of the pulse train can be controlled.
FIG. 5a depicts a block level representation of the multi-type spike generating neuron circuit 200 for generating particular types of spikes at runtime, according to embodiments as disclosed herein. As depicted in FIG. 5a, the block level representation of the multi-type spike generating neuron circuit 200 or the digital equivalent circuit 300 comprises of two additional multiplexers. The NEURON BASIC BLOCK represents the multi-type spike generating neuron circuit 200 or the digital equivalent circuit 300.
The INPUT pin can be used for providing the input signal Vin to the VIN terminal of the NEURON BASIC BLOCK. The voltage levels applied at the INPUT pin can be varied based on the spike pattern that needs to be generated. In an embodiment, the voltage levels applied at the INPUT pin can be 1.8 volts, 1 volt, 0 volts, or a periodic pulse train.
The TYPE pin is used for selecting a type of input that needs to be provided to the PHASIC terminal of the NEURON BASIC BLOCK. The type of input provided to the PHASIC terminal can be varied. The input that is provided to the PHASIC pin can represent the PHASIC input. In an embodiment, the PHASIC input applied at the PHASIC terminal can be voltage levels, such as 1.8 volts or 0 volts, a single pulse, or a periodic pulse train with variable duty cycle. A multiplexer can be used for selecting the voltage level or pulse that needs to be applied at the PHASIC terminal based on the input provided at the TYPE pin. The pulse generator unit generates pulses, which can be used for shaping the spike train to obtain a particular type of spike pattern.
The VDDSEL pin is used for selecting a scaled voltage level that needs to be derived from a power supply selection circuit (VDD scaling block) and applied to the VDD terminal of the NEURON BASIC BLOCK. The input to the VDDSEL pin is always high, i.e., a voltage of is always drawn from the VDD scaling block. In an embodiment, scaled voltage levels applied at the VDDSEL pin can be V1, V2, V3 and V4. The scaled voltage levels are the scaled versions of VDD. The voltages V1, V2, V3 and V4 can be drawn from the VDD scaling block. A multiplexer can be used for selecting the scaled voltage level that needs to be applied at the VDDSEL pin.
In an embodiment, based on the input at the TYPE pin and the output of the pulse generator unit at runtime, the multi-type spike generating neuron circuit 200 can generate at least one type of spiking train comprising, but not limited to, regular spiking or tonic spiking, phasic spiking, tonic bursting, phasic bursting, fast spiking (involving spike frequency adaptation), mixed mode (involving bursting and spiking) Depolarizing After-Potential (DAP) spiking, spike latency, inhibition induced spiking, inhibition induced bursting, rebound spiking, rebound bursting, Bi-stable (involving resting and tonic spiking), and so on. The different types of spiking trains mimic the responses of the biological neurons.
FIG. 5b depicts a power supply selection circuit for obtaining different scaled variations of a supply voltage, according to embodiments as disclosed herein. The power supply selection circuit can be in the VDD scaling block. The VDD scaling block can provide voltages V1, V2, V3 and V4, wherein either one of the four voltages can be selected by a MUX based on the VDDSEL input. The voltages V1, V2, V3 and V4 are scaled versions of voltage VDD. The voltages V1, V2, V3 and V4, are VDD1, VDD2, VDD3 and VDD4 respectively.
FIGS. 6a-6j are graphs depicting the generation of different spike patterns using the multi-type spike generating neuron circuit 200, according to embodiments as disclosed herein. In an embodiment, the different types of spike patterns can be obtained using (MOSFET) 180 nm technology. The different types of spike patterns can be obtained by varying the combinations of input applied at the TYPE pin (PHASIC terminal of the NEURON BASIC BLOCK), the INPUT pin (VIN terminal of the NEURON BASIC BLOCK) and the VDDSEL pin (VDD terminal of the NEURON BASIC BLOCK). The following table depicts the combinations of inputs applied to the terminals VDD, Vin, and PHASIC, of the NEURON or NEURON BASIC BLOCK for generating the different types of spiking patterns.
Spike Type VDD (V) PHASIC (V) Vin (V)
Tonic Spiking 1.8 0 1.8
Phasic Spiking 1.8 1.8 1.8
Tonic Bursting 1.8 Periodic Pulse Wave 1.8
Phasic Bursting 1.8 Single Pulse 1.8
Fast spiking
1.3 0 1.8
Mixed Mode 1.8 Pulse train with Duty Cycle >50% 1.8
DAP 1 0 1
Spike Latency 1.1 0 1.8
Inhibition-induced spiking 1.8 1.8 0
Inhibition-induced bursting 1.8 1.8 Periodic Pulse Wave
Table 1
The different input combinations are depicted for 180 nm technology. The input values are represented in voltages. These values are specific to a technology node and its supported VDD voltages. Additional voltage levels can be determined using regressive analysis. In 45 nm technology, the VDD voltage levels can be scaled to 0.8 volts, 0.57 volts, 0.48 volts, and 0.44 volts. The power consumption involved in generating the spike patterns in 45 nanometer technology can be reduced be 0.06 Pico-Joules/spike.
As depicted in FIG. 6a, the multi-type spike generating neuron circuit 200 generates a regular spiking train or tonic spiking train. The spiking pattern (VSPIKE) includes periodic spikes, which have been generated in response to an input (Vin). As depicted in FIG. 6b, the multi-type spike generating neuron circuit 200 generates a phasic spiking pattern. The phasic spiking pattern includes a single spike in response to the input.
As depicted in FIG. 6c, the multi-type spike generating neuron circuit 200 generates a tonic bursting train. The spiking pattern comprises periodic bursts of spikes in response to the input. As depicted in FIG. 6d, the multi-type spike generating neuron circuit 200 generates a phasic bursting train. The spiking pattern comprises of a single burst of spikes, which is generated in response to the input. As depicted in FIG. 6e, the multi-type spike generating neuron circuit 200 can generate a fast spiking train in response to the input. The frequency of generation of spikes, i.e., spiking frequency, is adapted by varying the voltage applied to the VDD terminal of the NEURON/NEURON BASIC BLOCK. The spiking frequency can be varied over a time period.
As depicted in FIG. 6f, the multi-type spike generating neuron circuit 200 can generate a spiking pattern which comprises of bursts and periodic spikes. It can be referred to as mixed mode, wherein there is an initial burst of spikes, which is followed by periodic generation of spikes. As depicted in FIG. 6g, the multi-type spike generating neuron circuit 200 can generate a DAP spiking pattern in response to the input. The spiking pattern may experience a period of super-excitability after a spike, instead of a refractory period. As depicted in FIG. 6h, the multi-type spike generating neuron circuit 200 can generate a spiking pattern, in which a spike is generated as a response to the input after a certain period of time has elapsed. This involves a spike latency, wherein the spike latency is inversely proportional to the input current. The strength of the input is encoded in the timing of the spike.
As depicted in FIG. 6i, the multi-type spike generating neuron circuit 200 can generate a spiking pattern which involves inhibition-induced spiking. Inhibition-induced type of spiking can be observed in organisms. . Inhibition-induced spiking activates h-current and deactivates calcium T-current, which leads to tonic spiking. This spiking pattern is generated when the input is low. The train of spikes is halted when the input is high. This can be achieved by inverting inputs in the synapse and applied to the multi-type spike generating neuron circuit 200. . As depicted in FIG. 6j, the multi-type spike generating neuron circuit 200 can generate a spiking pattern which involves inhibition-induced bursting. The inhibition-induced bursting is similar to inhibition-induced spiking. A plurality of bursts of spikes is generated during the time period when the input is low. This can be achieved by inverting inputs in the synapse and applied to the multi-type spike generating neuron circuit 200. The generation of the bursts of spikes begins when the input transitions from high to low. The spiking train may be useful for analyzing the sleep rhythms.
The embodiments disclosed herein can be implemented through at least one software program running on at least one hardware device and performing network management functions to control the network elements. The network elements shown in FIG. 1 include blocks which can be at least one of a hardware device, or a combination of hardware device and software module.
The embodiments disclosed herein describe methods and systems for modeling a bio-plausible neuron using electronic circuits, which can be employed in neural networks or architectures for performing machine learning operations and operations requiring artificial intelligence capability. The embodiments avoid utilizing capacitors in the bio-plausible neuron model, which leads to massive savings in the neuromorphic computing chip area. The embodiments aim at exploiting the intrinsic capacitance present in transistors (MOSFETs in particular), to model various bio-plausible neural spike-types. This electronic bio-plausible neuron model eliminates the requirement of having standalone capacitors in every neuron circuit, which makes the electronic neuron model one of the smallest bio-plausible neuron.
Therefore, it is understood that the scope of the protection is extended to such a program and in addition to a computer readable means having a message therein, such computer readable storage means contain program code means for implementation of one or more steps of the method, when the program runs on a server or mobile device or any suitable programmable device. The method is implemented in a preferred embodiment through or together with a software program written in example Very high speed integrated circuit Hardware Description Language (VHDL), or any other programming language, or implemented by one or more VHDL or several software modules being executed on at least one hardware device. The hardware device can be any kind of portable device that can be programmed. The device may also include means, which could be, for example, a hardware means, for example, an Application-specific Integrated Circuit (ASIC), or a combination of hardware and software means, for example, an ASIC and a Field Programmable Gate Array (FPGA), or at least one microprocessor and at least one memory with software modules located therein. The method embodiments described herein could be implemented partly in hardware and partly in software. Alternatively, the invention may be implemented on different hardware devices, e.g. using a plurality of Central Processing Units (CPUs).
The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the scope of the embodiments as described herein.