DESC:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003S

COMPLETE SPECIFICATION
[SEE SECTION 10, RULE 13]

A BUFFER MODELLING SYSTEM AND
A METHOD THEREOF

BHARAT ELECTRONICS LIMITED
WITH ADDRESS:
OUTER RING ROAD, NAGAVARA, BANGALORE 560045, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

TECHNICAL FIELD
[1] The present invention relates generally data processing systems and specifically to buffer modelling.

BACKGROUND
[2] 100 gigabit Ethernet (100 GbE) is a version and series of Ethernet that for transmission of data at a speed of 100 gigabits per second. 100 GbE is under the IEEE 802.3ba standard to provide high-speed data transfer between long distance channels and nodes. The primary use of 100 GbE is for direct communication between switches. 100 GbE provides highest data transmission speeds and maintains support and integration with existing Ethernet interfaces. In copper mode fiber, 100 GbE may reach a distance of 10 meters. In single mode fiber, it may be extended to 60 miles. 100 GbE modulation scheme divides bandwidth into two polarized streams. Each stream is further broken down into two streams of 25 Gbps each.
[3] In a conventional system as disclosed in CN104660461A, a test instrument based on communication is provided. The test instrument includes an optical module, a caching unit, a main unit and a logical processing unit. The optical module is used for receiving serial optical signals and converting the optical signals into parallel 10*10G electrical signals and then carrying out exchange with the FPGA.
[4] In another conventional system as disclosed in WO2014063599A1, a method for a device is provided. The method includes receiving frames from different interfaces, and converting the received frames into those of a uniform bit width and maintaining a buffer address that is already written into and a currently idle buffer address in a buffer; receiving the currently idle buffer address, generating a write and/or read instruction regarding the buffer, and correspondingly performing a write and/or read operation, so as to write , received and processed by an IPC, into the currently idle buffer, or read from the buffer; performing bit width conversion and format encapsulation on the read according to the read request, and performs outputting through a corresponding interface.
[5] In yet another conventional system as disclosed in US20170046298A1, an asynchronous first-in first-out (AFIFO) buffer apparatus is provided. The AFIFO buffer apparatus includes an AFIFO buffer and a rate circuit. The AFIFO buffer receives an input from a first processing circuit operating under a first clock and transmits an output to a second processing circuit operating under a second clock, where the first clock is asynchronous to the second clock. The rate circuit actively controls a transfer rate of the input regardless of a water level of the AFIFO buffer, and further adaptively applies compensation to the transfer rate according to the water level of the AFIFO buffer.
[6] In yet another conventional system as disclosed in US6985977B2, a system and a method for transferring data to a device using double buffered data transfers is provided. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. The data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer.
[7] Thus, there is a need for an improved buffer modelling system for high-speed applications.

SUMMARY
[8] This summary is provided to introduce concepts related to buffer modelling. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[9] In an embodiment of the present invention, a buffer modelling system is provided. The buffer modelling system includes a receiver and a transmitter. The receiver includes a data buffer and a control buffer. The data buffer is configured to store a plurality of data packets received from a transceiver. The data packets are stored in a continuous manner within the data buffer. The control buffer is configured to store a plurality of control information corresponding to the stored data packets. The transmitter includes a First In First Out (FIFO) register, the data buffer, and the control buffer. The FIFO is configured to store the data packets in a continuous manner based on the control information. The FIFO receives a transmitter ready signal as a read request signal. The FIFO transmits the data packets to a transceiver when the transmitter ready signal is at a high level. The buffer modelling system achieves full throughput with flow control without loss of any of the data packets.
[10] In another embodiment of the present invention, a buffer control method is provided. The buffer control method includes storing a plurality of data packets received from a transceiver in a data buffer in a continuous manner. The method further includes storing a plurality of control information corresponding to the stored data packets in a control buffer. The method further includes storing the data packets in a continuous manner in a First In First Out (FIFO) register based on the control information. The FIFO receives a transmitter ready signal as a read request signal. The data packets are transmitted by the FIFO to a transceiver when the transmitter ready signal is at a high level. The buffer modelling method achieves full throughput with flow control without loss of any of the data packets.
[11] In an exemplary embodiment, the control information is written simultaneously and in the control buffer in a continuous manner while storing the data packets in the data buffer.
[12] In another exemplary embodiment, the data packets are written simultaneously in the FIFO register in a continuous manner while storing the data packets in the data buffer.
[13] In another exemplary embodiment, the data buffer and the control buffer are equal in size for buffer flow control. Here, underflow is decided based on the control buffer and overflow is decided based on the data buffer.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[14] Reference will be made to embodiments of the invention, examples of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.
[15] Figure 1 illustrates a schematic block diagram of a buffer system in accordance with an embodiment of the present invention.
[16] Figures 2 and 3 illustrate a buffer modelling approach in accordance with embodiments of the present invention.
[17] Figure 4 illustrates a schematic block diagram of a test setup for analyzing performance of a buffer modelling system in accordance with an embodiment of the present invention.
[18] Figure 5 shows results of the test setup of Figure 4.
[19] Fig. 6 is a flowchart illustrating a buffer modelling method in accordance with an embodiment of the present invention.
[20] It should be appreciated by those skilled in the art that any block diagram herein represents conceptual views of illustrative systems embodying the principles of the present invention. Similarly, it will be appreciated that any flow chart, flow diagram, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
[21] The various embodiments of the present invention provide a buffer modelling system and a buffer modelling method.
[22] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[23] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.
[24] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[25] References in the present invention to “embodiment” or “embodiment” mean that a particular feature, structure, characteristic, or function described in connection with the embodiment or the embodiment is included in at least one embodiment or embodiment of the invention. The appearances of the phrase “in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[26] In an embodiment of the present invention, a buffer modelling system is provided. The buffer modelling system includes a receiver and a transmitter. The receiver includes a data buffer and a control buffer. The data buffer is configured to store a plurality of data packets received from a transceiver. The data packets are stored in a continuous manner within the data buffer. The control buffer is configured to store a plurality of control information corresponding to the stored data packets. The transmitter includes a First In First Out (FIFO) register, the data buffer, and the control buffer. The FIFO is configured to store the data packets in a continuous manner based on the control information. The FIFO receives a transmitter ready signal as a read request signal. The FIFO transmits the data packets to a transceiver when the transmitter ready signal is at a high level. The buffer modelling system achieves full throughput with flow control without loss of any of the data packets.
[27] In another embodiment of the present invention, a buffer control method is provided. The buffer control method includes storing a plurality of data packets received from a transceiver in a data buffer in a continuous manner. The method further includes storing a plurality of control information corresponding to the stored data packets in a control buffer. The method further includes storing the data packets in a continuous manner in a First In First Out (FIFO) register based on the control information. The FIFO receives a transmitter ready signal as a read request signal. The data packets are transmitted by the FIFO to a transceiver when the transmitter ready signal is at a high level. The buffer modelling method achieves full throughput with flow control without loss of any of the data packets.
[28] In an exemplary embodiment, the control information is written simultaneously and in the control buffer in a continuous manner while storing the data packets in the data buffer.
[29] In another exemplary embodiment, the data packets are written simultaneously in the FIFO register in a continuous manner while storing the data packets in the data buffer.
[30] Referring now to Figure 1, a schematic block diagram of a buffer system is shown in accordance with an embodiment of the present invention. The buffer system includes a receiver module (101) and a transmitter module (102). The receiver module (101) includes a receiver (112) and a receiver of a transceiver (114). The transmitter module (102) includes a transmitter (116) and a transmitter of a transceiver (118).
[31] At the receiver module (101), the transceiver (114) receives the ethernet data from an optical module. The transceiver (114) transmits the ethernet data to the receiver (112). The receiver (112) transmits the ethernet data to the processing module (not shown in Figure 1).
[32] The receive clock (RX_CLOCK) speed is 390.625MHZ. The RX_DATA (512 bits) is sampled at the rising edge of RX_CLOCK, when the RX_VALID is high. RX_STARTOFPKT assertion indicates the starting of the packet and RX_ENDOFPKT assertion indicates the end of the packet. Since Ethernet packets of random size may be received, the last RX_DATA may not contain the full 512 bits. The RX_EMPTY field indicates the number of empty bytes in the RX_DATA, when RX_ENDOFPKT is asserted.
[33] At the transmitter module (102), the transmitter (116) receives the processed ethernet data from the processing module. When the transceiver (118) sends a high signal on the TX_READY signal, the transmitter (116) transmits the processed ethernet data to the transceiver (118).
[34] The transmit clock (TX_CLOCK) speed is 390.625MHZ. The TX_DATA (512 bits) is sampled at the rising edge of TX_CLOCK, when the TX_VALID is high. TX_STARTOFPKT assertion indicates the starting of the packet and TX_ENDOFPKT assertion indicates the end of the packet. Since Ethernet packets of random size may be transmitted, the last TX_DATA may not contain the full 512 bits. The TX_EMPTY field indicates the number of empty bytes in the TX_DATA, when TX_ENDOFPKT is asserted. To enable the flow control, receiver logic asserts the TX_READY signal, indicating the receiver is ready to receive the data (103). Once the TX_READY signal is asserted, the transmitter logic should immediately give the next 512-bit data on the TX_DATA signal in the same cycle of TX_READY signal.
[35] Referring now to Figure 2, a buffer modelling approach is shown in accordance with an embodiment of the present invention. The buffer modelling approach achieves full throughput up to 100Gbps.
[36] For 1G and 10G Ethernet, the control information such as Packet length, starting address of the packet and the ending address of the packet may be written in the buffer during the cycles between the packets. But for 100G Ethernet, the data comes continuously for every packet (201, 202, and 203). Therefore, the control information writing in the buffer (same as that of data) reduces the throughput. To consider this effect a simple approach is proposed, which makes use of two buffers, one for the data (204) and other for the control information (205) of the data. When packets are received, the data is written into a data buffer (220) in continuous locations (206). After receiving the last byte of the packet (which is indicated by the RX_ENDOFPKT), the control information of the packet is written to the control memory (207). While writing the control information into the control buffer (222), the next packet data also is be written to the data memory. For 64-byte Ethernet packets, where start of packet and the end of packet is asserted in the same clock cycle, the data buffer (220) and the control buffer (222) are written simultaneously (208, 209).
[37] Referring now to Figure 3, a buffer modelling to achieve full throughput when the receiver is not ready (flow control enabled) is shown in accordance with an embodiment of the present invention.
[38] Whenever the application or processing module has a packet to transmit, the data is written into the data buffer (220) in continuous locations (206). Once the packet is ended, the control information of the packet is written to the control memory (207). While writing the control information into the control buffer (222), the next packet data also is written to the data memory. The TRASMIT MODULE reads the control buffer (222) and if any packet presents, it reads the data buffer (220) and writes into the FIFO buffer (301).
[39] The read request signal of the FIFO buffer is connected to the TX_READY signal (and negation of the FIFO empty signal) (302). Therefore, whenever TX_READY signal is asserted, then only data is read from the FIFO and TX_DATA, TX_STARTOFPKT, TX_ENDOFPKT and TX_EMPTY is asserted (303). This read data is latched by the receiver during the next TX_READY signal (304, 305). Therefore, application is writing the data to the data buffer (220) and the control buffer (222), while the TRANSMIT MODULE is writing the data to the FIFO buffer in parallel, which is read and sent to the TX MAC whenever the TX_READY signal is asserted. In this way, even for non-continuous channels, without affecting the throughput, packet may be sent at the full rate of 100Gbps.
[40] In operation, the data buffer (220) stores the data packets (PKT1 - PKTn) received from the transceiver (114). The data packets (PKT1 - PKTn) are stored in a continuous manner within the data buffer (220). The control buffer (222) stores the control information (PKT1 control info – PKTn control info) corresponding to the stored data packets (PKT1 - PKTn). The FIFO (320) register stores the data packets (PKT1 - PKTn) in a continuous manner based on the control information (PKT1 control info – PKTn control info). The FIFO (320) receives the transmitter ready (TX_READY) signal as the read request signal (RD_REQ). The FIFO (320) transmits the data packets (PKT1 - PKTn) to the transceiver (118) when the transmitter ready (TX_READY) signal is at a high level. The buffer modelling system achieves full throughput with flow control and without loss of any of the data packets (PKT1 - PKTn).
[41] Figure 4 illustrates a schematic block diagram of a test setup for analyzing performance of the buffer modelling in accordance with an embodiment of the present invention. The test setup includes the 100G Ethernet analyzer connected to a custom hardware. Figure 5 shows results of the test setup of Figure 4.
[42] Referring now to Figure 6, a flowchart illustrating a buffer modelling method is shown in accordance with an embodiment of the present invention.
[43] At step 602, the data packets (PKT1 - PKTn) received from the transceiver (114) are stored in the data buffer (220) in a continuous manner.
[44] At step 604, the control information (PKT1 control info – PKTn control info) corresponding to the stored data packets (PKT1 - PKTn) is stored in the control buffer (222).
[45] At step 606, the processing module processes the data to generate the processed data.
[46] At step 608, the data packets (PKT1 - PKTn) are stored in a continuous manner based on the corresponding control information (PKT1 control info – PKTn control info) in the FIFO (320).
[47] At step 610, the transmitter ready (TX_READY) signal is received as the read request (RD_REQ) signal for the FIFO (320).
[48] At step 612, the data packets (PKT1 - PKTn) are transmitted to the transceiver (118) by the FIFO (320) when the transmitter ready (TX_READY) signal is at a high (1) level.
[49] In an embodiment of the present invention, a method of buffering and processing of high-speed data (100Gbps) to achieve full throughput in Ethernet communication is provided. The method includes two buffers of equal length in which one is data buffer (220) to store the received data packets and the second one is the control buffer (222) to store the control information (address and length) of the received data packets. Two buffers of equal length are used to store the data and control information coming from the packet processing module and a FIFO to handle the flow control in transmit path. The data buffer (220) and control buffer (222) are equal in size for buffer flow control wherein underflow is decided based on the control buffer (222) and overflow is decided based on data buffer (220). In an example, writing the data into the buffers is performed concurrently. Also, the packet writing in data buffer (220) and FIFO is simultaneous and the packet reading from the FIFO is conditional based on transmitter readiness as the flow control.
[50] In an exemplary embodiment, the buffer modelling is used for the Ethernet standards namely 10 Mbps to 400Gbps which receives or transmits the data with different word sizes at MAC layer. For 100Gbps Ethernet standard, the Ethernet frames are transmitted and received at MAC layer in the form of words of 512 bit with a clock frequency of 390.625MHz. The method of buffering and processing of high-speed data (100Gbps) is developed to achieve full throughput in Ethernet communication. In this, two types of buffers are used to store the received data in Rx Data Buffer and its memory address & length in RX Control Buffer. Similarly, TX Data Buffer and TX Control Buffer are used to transmit the stored Ethernet Data. Here FIFO Buffer is also used to control the flow control. The method maintains the continuous data packet handling at 100Gbps rate with minimum IFG (Inter Frame Gap) approximately single byte and helps to achieve 100Gbps full throughput without any loss of packet.
[51] Advantageously, the present invention provides a buffer modelling for 100G Ethernet. The buffer modelling may be used for any packet-based applications where the data comes in continuous clock cycles. The Ethernet packets for the 100Gbps come continuously in the immediate clock cycle, once a packet reception is completed. Whereas for 1G and 10G Ethernet, there are enough number of cycles between every packet. Therefore, the buffer modelling for 100Gbps Ethernet has designed in such a way that, full throughput of 100Gbps is achieved. The proposed architecture for buffer modelling uses two buffers (one for data memory and the other for control memory). In addition to this, FIFO is used to handle the flow control from the receiver while achieving the full data rate.
[52] The method of buffering provided in the present invention maintains the continuous data packet handling at 100Gbps rate with minimum IFG approximately single byte and helps to achieve 100Gbps full throughput without any loss of packet.
[53] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:We claim:

1. A buffer modelling system, comprising:
a receiver (112) comprising:
a data buffer (220) configured to store a plurality of data packets (PKT1 - PKTn) received from a transceiver (114), wherein the data packets (PKT1 - PKTn) are stored in a continuous manner within the data buffer (220); and
a control buffer (222) configured to store a plurality of control information (PKT1 control info – PKTn control info) corresponding to the stored data packets (PKT1 - PKTn); and
a transmitter (116) comprising:
the data buffer (220);
the control buffer (222); and
a First In First Out (FIFO) register (320) configured to:
store the data packets (PKT1 - PKTn) in a continuous manner based on the corresponding control information (PKT1 control info – PKTn control info),
receive a transmitter ready (TX_READY) signal as a read request (RD_REQ) signal, and
transmit the data packets (PKT1 - PKTn) to a transceiver (118) when the transmitter ready (TX_READY) signal is at a high (1) level, thereby achieving full throughput with flow control without loss of any of the data packets (PKT1 - PKTn).

2. The buffer modelling system as claimed in claim 1, wherein the control information (PKT1 control info – PKTn control info) is written simultaneously in the control buffer (222) in a continuous manner while storing the data packets (PKT1 - PKTn) in the data buffer (220).

3. The buffer modelling system as claimed in claim 1, wherein the data packets (PKT1 - PKTn) are written simultaneously in the FIFO (320) in a continuous manner while storing the data packets (PKT1 - PKTn) in the data buffer (220).

4. The buffer modelling system as claimed in claim 1, wherein the data buffer (220) and the control buffer (222) are equal in size for buffer flow control, and wherein underflow is decided based on the control buffer (222) and overflow is decided based on the data buffer (220).

5. A buffer modelling method comprising:
storing a plurality of data packets (PKT1 - PKTn) received from a transceiver (114) in a data buffer (220) in a continuous manner;
storing a plurality of control information (PKT1 control info – PKTn control info) corresponding to the stored data packets (PKT1 - PKTn) in a control buffer (222);
storing the data packets (PKT1 - PKTn) in a continuous manner based on the corresponding control information (PKT1 control info – PKTn control info) in a First In First Out (FIFO) register (320);
receiving a transmitter ready (TX_READY) signal as a read request (RD_REQ) signal for the FIFO (320); and
transmitting the data packets (PKT1 - PKTn) to a transceiver (118) by the FIFO (320) when the transmitter ready (TX_READY) signal is at a high (1) level, thereby achieving full throughput with flow control without loss of any of the data packets (PKT1 - PKTn).

6. The buffer modelling method as claimed in claim 5, comprising:
writing the control information (PKT1 control info – PKTn control info) in the control buffer (222) in a continuous manner simultaneously while storing the data packets (PKT1 - PKTn) in the data buffer (220).

7. The buffer modelling method as claimed in claim 5, comprising:
writing the data packets (PKT1 - PKTn) in a continuous manner simultaneously while storing the data packets (PKT1 - PKTn) in the data buffer (220).

8. The buffer modelling method as claimed in claim 5, wherein the data buffer (220) and the control buffer (222) are equal in size for buffer flow control, and wherein underflow is decided based on the control buffer (222) and overflow is decided based on the data buffer (220).

Dated this 1st day of April, 2019

For BHARAT ELECTRONICS LIMITED,
By their Agent,

(D. Manoj Kumar)
Patent Agent No.: IN/PA-2110
KRISHNA & SAURASTRI ASSOCIATES LLP