FORM 2

THE PATENTS ACT  1970
(39 of 1970)
&
THE PATENTS RULES  2003

COMPLETE SPECIFICATION
(See section 10  rule 13)

“A clock synchronization and distribution method and system during card switchover in a redundant transmission system”

Tejas Networks Limited
2nd floor  GNR Tech Park  46/4  Garbebhavi Palya 
Kudlu Gate  Hosur main road 
Bangalore 560 068  Karnataka  India

The following specification particularly describes the invention and the manner in which it is to be performed.

Field of the Invention

The present invention relates to a clock recovery and synchronization. More particularly  the present invention relates to a method and system of clock recovery  synchronization and distribution during card switchover in a redundant transmission system.

Background of the Invention

Many electronic devices and systems require multiple clocking devices for operation. For example  in many automated systems  it is necessary to provide clocks in multiple locations for the proper function of various components of the systems. Often  the synchronization of these clocks is essential to accuracy and performance.

One method of providing clock synchronization is described according to IEEE Standard 1588  often referred to as the IEEE Standard Precision Time Protocol (PTP). Under this protocol  a master clock communicates with one or more slave clocks via a network link such as an Ethernet link. Periodically  the master clock transmits it’s time to the slave clocks  which adjust their clock values to the master clock time including accounting for propagation delay values between the master clock and the respective slave clocks.

Currently  the IEEE 1588 protocol and other known synchronization standards rely on frequency locking of the master and slave clocks. In particular  the master and slave clock signals are digital signals that provide a clock function via counters. If the counters of the master clock and a slave clock have the same value  the clocks are deemed synchronized and no adjustment is made. If the counters of the slave clock and master clock differ by one count  an adjustment is made at the slave counter to return the clocks to synchronization. Thus  it is not until the master and slave clocks differ by one count in time is any adjustment made. This is often referred to as the limit cycle.

Further  clock recovery algorithm based on 1588v 2 (PTP) and NTP v4 are used for recovering both frequency and timing information from a central Grand master Clock present in the network. The recovery method suggested by the Standards presents detailed Software and Hardware State machine based on Server client topology implementation.

The client state machines are run on many network nodes  which need time and frequency synchronization. On Client network equipment with a single control card  a single Client locked to the Grand master is good enough. The recovered clock is then fed to all other line cards in the system.

Most of the client network equipment today supports multiple control cards for providing Card level redundancy to protect against any control card failures. Typically In such systems  one of the card acts as Primary Control card  and other control card acts as a backup standby control card. On failure of Primary card or manual Redundancy switchover  the backup control card becomes the new primary. All the control functionality is handled by the new Primary card  including the clock recovery functionality.

1588/NTP based clock recovery solutions pose a new challenge with redundant systems at the time of switchovers. Switchovers can be due to manual action or on card failures (software or hardware). Because of the continuous packet protocol exchange happening between the network Server and the client clock modules  whenever there is a switchover the new primary needs to restart its Clock recovery State machine to lock to the network Grand master clock. The locking times of the algorithm can typically vary between 10-45 minutes  depending on the network quality. This is not acceptable in most telecom system deployment as during this time  the clock provided to the line cards are not of good quality.

There is a need for a method and apparatus that overcomes at least the shortcomings of known clock synchronization architectures.

Summary of the Invention

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments  and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

In accordance with one aspect of the present invention is a clock synchronization and distribution method during card switchover in a redundant transmission system  the method comprising: exchanging periodically timing information by a slave work card with a master device clock to synchronize the time base reference clock  precisely wherein the timing information i.e. time stamp frame comprises at least an original time stamp about the time when the slave work card clock side transmits and receives a synchronous (Sync) packet  snooping the published slave work card sync packet by a plurality of slave protect cards with the time stamp value of the master device clock and compensating the time stamp value appropriately by all the slave protect cards with the snooped sync packet time stamp value of the slave work card.

In accordance with another aspect of the present invention is a system of clock recovery and synchronization during card switchover in a redundant transmission system  the system comprising: at least one master device and a plurality of slave devices  wherein the slave devices include at least one slave work control card and at least one slave protect control card  wherein the slave work card and the slave protect cards includes a timing packet generator and a timing packet receiver  wherein the system is configured for exchanging periodically timing information by a slave work card with a master device clock to synchronize the time base reference clock  precisely  wherein the timing information i.e. time stamp frame comprises at least an original time stamp about the time when the slave work card clock side transmits and receives a synchronous (Sync) packet  snooping the published slave work card sync packet by a plurality of slave protect cards with the time stamp value of the master device clock and compensating the time stamp value appropriately by all the slave protect cards with the snooped sync packet time stamp value of the slave work card.

The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

Before undertaking the detailed description of the invention below  it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise ” as well as derivatives thereof  mean inclusion without limitation; the term “or ” is inclusive  meaning and/or; the phrases “associated with” and “associated therewith ” as well as derivatives thereof  may mean to include  be included within  interconnect with  contain  be contained within  connect to or with  couple to or with  be communicable with  cooperate with  interleave  juxtapose  be proximate to  be bound to or with  have  have a property of  or the like; and the term “controller” means any device  system or part thereof that controls at least one operation  such a device may be implemented in hardware  firmware or software  or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed  whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document  those of ordinary skill in the art should understand that in many  if not most instances  such definitions apply to prior  as well as future uses of such defined words and phrases.

Brief description of the drawings

For a more complete understanding of the present invention  and the advantages thereof  reference is now made to the following descriptions taken in conjunction with the accompanying drawings  wherein like numbers designate like objects  and in which:

Figure 1 shows a typical 1588 based clock recovery mechanism between the master entity and slave entity.

Figure 2 shows a system of clock recovery and synchronization during card switchover in a redundant transmission system according to one embodiment of the present invention.

Figure 3 shows a flow chart of a clock synchronization and distribution method during card switchover in a redundant transmission system according to one embodiment of the present invention.

Figure 4 is a diagrammatic block view of a processing system  according to various embodiments.

Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example  the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure.

Throughout the drawings  it should be noted that like reference numbers are used to depict the same or similar elements  features  and structures.

Detail description of the Invention

In the following description  for purposes of explanation and not limitation  specific details are set forth such as particular architectures  interfaces  techniques  etc. in order to provide a thorough understanding of the present invention. However  it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. That is  those skilled in the art will be able to devise various arrangements which  although not explicitly described or shown herein  embody the principles of the invention and are included within its spirit and scope. In some instances  detailed descriptions of well-known devices  circuits  and methods are omitted so as not to obscure the description of the present invention with unnecessary detail. All statements herein reciting principles  aspects  and embodiments of the invention  as well as specific examples thereof  are intended to encompass both structural and functional equivalents thereof. Additionally  it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future  i.e.  any elements developed that perform the same function  regardless of structure.

Thus  for example  it will be appreciated by those skilled in the art that block diagrams herein can represent conceptual views of illustrative circuitry embodying the principles of the technology. Similarly  it will be appreciated that any flow charts  state transition diagrams  pseudo code  and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor  whether or not such computer or processor is explicitly shown.

The functions of the various elements including functional blocks labeled or described as "computer"  "processor" or "controller" may be provided through the use of dedicated hardware as well as hardware capable of executing software in the form of coded instructions stored on computer readable medium. A computer is generally understood to comprise one or more processors  and the terms computer and processor may be employed interchangeably herein. When provided by a computer or processor  the functions may be provided by a single dedicated computer or processor  by a single shared computer or processor  or by a plurality of individual computers or processors  some of which may be shared or distributed. Such functions are to be understood as being computer-implemented and thus machine-implemented. Moreover  use of the term "processor" or "controller" shall also be construed to refer to other hardware capable of performing such functions and/or executing software  and may include  without limitation  digital signal processor (DSP) hardware  reduced instruction set processor  hardware (e.g.  digital or analog) circuitry  and (where appropriate) state machines capable of performing such functions.

Figure 1 shows a typical 1588 based clock recovery scheme or mechanism between the master entity and slave entity. Most network based synchronization protocols exchange timing messages between at least two clocks. In general  the timing protocols have similar principles with minor differences in implementation. To facilitate understanding  IEEE 1588 will be used in this example. A slave entity trying to communicate with the master with different messages as described below to retrieve clock offset and delay and eventually correct the time. The master and slave clock both have a packet generator and receiver with accurate time stamping capability. The time stamping values are the input for the clock recovery engines. In a redundant card solution  multiple slaves parallelly communicate with the master to retrieve the clock.

A master sends a message M1  e.g. Sync  to the slave. Both master and slave timestamp the message as close to the network interface as possible (t1 and t2). The timestamp generated at the master  t1  is sent to the slave as a field in the Sync message M1 to be received by slave at t2  alsot1 is optionally sent in a non-time critical message M2  e.g. Follow-up. The process is reversed with the slaved sending a message M3  e.g. Delay_req  to the master. Both master and slave timestamp the message as close to the network interface as possible  t3 and t4. The timestamp generated at the master  t4  is sent to the slave in a non-time critical message M4  e.g. Delay_Resp. Once the slave has all four timestamps t1  t2  t3  and t4  it can compute the mean propagation time and the clock offset. The timed messages  M 1 and M 3  pass through a switch that includes variable delay (jitter) that introduces uncertainty into the computation of delay and offset.

In the present invention this is achieved in a single session  per system is used to derive the clock by multiple redundant cards. The present invention assumes snooping support in the hardware. Snooping implementation’s typically comprise of replicating the original packet (from and to the master) as-is or in part to the backup cards. There can variants in snooping implementations comprising mainly of sending only the relevant information as a separate packet or a hardware signal to the backup card. Example of the variants  include sending header and timestamp value separately to the backup cards.
The present invention use two components of a typical packet based Timing and frequency slave clocks.
• Packet generator
• Packet receiver

Figure 2 shows a system of clock recovery and synchronization during card switchover in a redundant transmission system according to one embodiment of the present invention. The system includes at least one master device and a plurality of slave devices (in figure only one slave device is shown as an example). All slave devices include at least one slave work control card or slave work card and a plurality of slave protect cards.

In an operation  when the slave work control card exchanges timing information with a master device clock in order to synchronize the time base reference clock. This exchanging of information periodically between the master device and the slave work control card in order to synchronize the timing information i.e. time stamp frame between them. The time stamp frame includes at least an original time stamp about the time when the slave work card clock side transmits and recevies a synchronous (Sync) packet. Whenever a packet is generated by a Timing recovery module (not shown in figure) of the slave work card  the packet is mirrored and snooped by all the slave protect cards.

As shown in figure 2  the generated packet from the slave work card being sent directly to master device or may be any output line card  the same packet is snooped by all the slave protect cards with the time-stamp value of the slave work card. Because of fixed PDV of transmission between the slave protect cards and the slave work card  the time-stamp value is appropriately compensated and used by the slave protect card as an input to the Timing generator state machine running in Software or Hardware. The packet generators at the slave protect cards are not active  until the slave work card failures happen. The slave work card packet generator acts as a proxy for the solution. In a similar operation  while receiving the packet at the slave work card from the master device or any link cards  the time stamping is done at the ingress of the line card and then the packet is snooped to the slave protect cards along with the ingress time-stamp values. The time-stamp values are the input to the state machine being executed at the protect cards.

One application of maintaining the clock synchronization improves the mobile deployment in redundant faults scenarios. The system of clock recovery and synchronization during card switchover in a redundant transmission supports layer 1 and or layer 2 networking layer.

Figure 3 shows a flow chart of a clock synchronization and distribution method during card switchover in a redundant transmission system according to one embodiment of the present invention. The present method is used for both boundary clock as well as Slave clock redundancy.

At step 310  the method exchanges periodically timing information by a slave work card with a master device clock to synchronize the time base reference clock  precisely. The timing information i.e. time stamp frame includes at least an original time stamp about the time when the slave work card clock side transmits and receives a synchronous (Sync) packet.

At step 320  the method snoops the published slave work card sync packet by a plurality of slave protect cards with the time stamp value of the master device clock. The snooping is used to keep the clock recovery engines and software state machines of both the slave work control cards and slave protect control cards in synchronization. The snooping the published packet is sent directly to the plurality of slave protect cards along with the output line card.

At step 330  the method compensates the time stamp value appropriately by all the slave protect cards with the snooped sync packet time stamp value of the slave work card. The compensating the time stamp value appropriately between the slave protect cards and the slave work card with the fixed packet delay variation.

At step 340  the method while receiving the packet at the slave work card from the master device or any other line cards  the time stamping is done at the ingress of the line card and then the packet is snooped to the slave protect cards along with the ingress time-stamp values. The time-stamp values are the input to the state machine being executed at the protect cards.

Although the flowchart 300 includes steps 310-340 that are arranged serially in the exemplary embodiments  other embodiments of the subject matter may execute two or more steps in parallel  using multiple processors or a single processor organized as two or more virtual machines or sub-processors. Moreover  still other embodiments may implement the steps as two or more specific interconnected hardware modules with related control and data signals communicated between and through the modules  or as portions of an application-specific integrated circuit. Thus  the exemplary process flow diagrams are applicable to software  firmware  and/or hardware implementations.

FIG. 4 is a diagrammatic block view of a processing system 400 according to various embodiments. The processing system 400 may include a central processing unit (CPU) 410  which may include any digital device capable of receiving data and programmed instructions  and processing the data according to the programmed instructions. Accordingly  the CPU 410 may include a microprocessor  such as a general purpose single-chip  or a multi-chip microprocessor. In particular  the multi-chip microprocessor may be structured as a three-dimensional multi-chip package  such as a system in package (SiP)  or a chip stack multi-chip module (MCM) the chip-stack multi-chip module  and may include one or more of the redundant signal transmission systems  according to one or more of the embodiments  such as  for example  the redundant transmission system of FIG. 2. The CPU 410 is generally configured to communicate with a memory unit 420 over a suitable communications bus 430. The memory unit 420 may also be structured as a three-dimensional multi-chip package  and may include one or more of the redundant signal transmission systems  according to one or more of the embodiments. The processing system 410 may also include various other devices that are operably coupled to the bus 430  which are configured to cooperatively interact with the CPU 410 and the memory unit 420. For example  the processing system 400 may include one or more input/output (I/O) devices 440  such as a printer  a display device  a keyboard  a mouse  or other known input/output devices. The processing system 400 may also include a mass storage device 450  which may include a hard disk drive  a floppy disk drive  an optical disk device (CD-ROM)  or other similar devices. It is understood that FIG. 4 provides a simplified representation of the processing system 400. Accordingly  it is understood that other devices not shown in FIG. 4  but known in the art (such as  for example  a memory controller  and other similar devices) may nevertheless be present in the processing system 400. As the various figures have shown  there may be multiple local paths and global paths in a memory system.

The processing system 400 may also form a part of other larger systems  such as a wireless device  which may include devices such as a wireless telephone  a personal digital assistant (PDA)  or another of a variety of known wireless devices.

FIGS. 1-4 are merely representational and are not drawn to scale. Certain portions thereof may be exaggerated  while others may be minimized. FIGS. 1-4 illustrate various embodiments of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.

While various embodiments have been illustrated and described  as noted above  changes can be made without departing from the disclosure. The accompanying drawings that form a part hereof show by way of illustration  and not of limitation  various embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom.

This Detailed Description  therefore  is not to be taken in a limiting sense. Although specific embodiments have been illustrated and described herein  it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the various embodiments shown. Furthermore  although the various embodiments have described redundant signal transmission systems  it is understood that the various embodiments may be employed in a variety of known electronic systems and devices without modification. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments  and other embodiments not specifically described herein  will be apparent to those skilled in the art upon reviewing the above description.

We Claim:

1. A clock synchronization and distribution method during card switchover in a redundant transmission system  the method comprising:
exchanging periodically timing information by a slave work card with a master device clock to synchronize the time base reference clock  precisely wherein the timing information i.e. time stamp frame comprises at least an original time stamp about the time when the slave work card clock side transmits and receives a synchronous (Sync) packet;
snooping the published slave work card sync packet by a plurality of slave protect cards with the time stamp value of the master device clock; and
compensating the time stamp value appropriately by all the slave protect cards with the snooped sync packet time stamp value of the slave work card.

2. The method of claim 1  wherein the step of snooping is used to keep the clock recovery engines and software state machines of both the slave work control cards and slave protect control cards in synchronization.

3. The method of claim 1  wherein the snooping the published packet is sent directly to the plurality of slave protect cards along with the output line card.

4. The method of claim 1  further comprising:
receiving the packet at the slave work card  where time stamping is done at the ingress of the line card and then the packet is snooped to the slave protect cards along with the ingress time-stamp values  wherein the time-stamp values are the input to the state machine being executed at the protect cards.

5. The method of claim 1  wherein the step of compensating the time stamp value appropriately between the slave protect cards and the slave work card with the fixed packet delay variation.

6. A system of clock recovery and synchronization during card switchover in a redundant transmission system  the system comprising:
at least one master device; and
a plurality of slave device  wherein the slave device include at least one slave work control card and at least one slave protect control card 
wherein the slave work card and the slave protect cards includes a timing packet generator and a timing packet receiver  wherein the system is configured for:
exchanging periodically timing information by a slave work card with a master device clock to synchronize the time base reference clock  precisely wherein the timing information i.e. time stamp frame comprises at least an original time stamp about the time when the slave work card clock side transmits and receives a synchronous (Sync) packet;
snooping the published slave work card sync packet by a plurality of slave protect cards with the time stamp value of the master device clock; and
compensating the time stamp value appropriately by all the slave protect cards with the snooped sync packet time stamp value of the slave work card.

7. The system of claim 6 supports layer 1 and or layer 2 and or layer 3 networking layer.

8. The system of claim 6  wherein the timing packet generators at the protect cards are not active  until the work card failures happens.

9. The system of claim 6  wherein by maintaining the clock synchronization improves the mobile deployment in redundant faults scenarios

10. The system of claim 6  wherein the clock recovery and packet transmit engines of all the cards including work and protect cards are independently running.

Dated this the 22nd day of February  2012

Abstract

A clock synchronization and distribution method and system during card switchover in a redundant transmission system

The present invention relates to a method and system of clock recovery and synchronization during card switchover in a redundant transmission system. In one embodiment this is accomplished by exchanging periodically timing information by a slave work card with a master device clock to synchronize the time base reference clock  precisely wherein the timing information i.e. time stamp frame comprises at least an original time stamp about the time when the slave work card clock side transmits and receives a synchronous (Sync) packet  snooping the published slave work card sync packet by a plurality of slave protect cards with the time stamp value of the master device clock and compensating the time stamp value appropriately by all the slave protect cards with the snooped sync packet time stamp value of the slave work card.

Figure 3 (for publication)