A computer processor (50) that has a checker (72) for receiving an instruction. The checker comprises a scoreboard (104), an input for receiving and external replay signal (78), and decision logic (101) coupled to the scoreboard 9104) and the input (78). The decision logic determines whether the instruction executed correctly based on both the scoreboard and the external replay signal.
| # | Name | Date |
|---|---|---|
| 1 | in-pct-2002-00635-kol-priority document others.pdf | 2011-10-08 |
| 2 | in-pct-2002-00635-kol-form 5.pdf | 2011-10-08 |
| 3 | in-pct-2002-00635-kol-form 3.pdf | 2011-10-08 |
| 4 | in-pct-2002-00635-kol-form 2.pdf | 2011-10-08 |
| 5 | in-pct-2002-00635-kol-form 18.pdf | 2011-10-08 |
| 6 | in-pct-2002-00635-kol-form 1.pdf | 2011-10-08 |
| 7 | in-pct-2002-00635-kol-drawings.pdf | 2011-10-08 |
| 8 | in-pct-2002-00635-kol-description complete.pdf | 2011-10-08 |
| 9 | in-pct-2002-00635-kol-correspondence.pdf | 2011-10-08 |
| 10 | in-pct-2002-00635-kol-claims.pdf | 2011-10-08 |
| 11 | in-pct-2002-00635-kol-assignment.pdf | 2011-10-08 |
| 12 | in-pct-2002-00635-kol-abstract.pdf | 2011-10-08 |
| 13 | IN-PCT-2001-635-KOL-(26-03-2013)-FORM-27.pdf | 2013-03-26 |
| 14 | IN-PCT-2001-635-KOL-(26-03-2013)-FORM 27.pdf | 2013-03-26 |