Claims:We Claim:
1. A concatenated FEC architecture comprising:
a) polar encoder (201); and
b) turbo encoder (202)
2. The concatenated FEC architecture as claimed in claim 1, wherein said polar encoder (201) is combined with the serial to parallel converter (203), which is considered as a digital circuit, in which the input data is given serially, and read the outputs in the form of parallel manner by performing an XOR operation.
3. The concatenated FEC architecture as claimed in claim 1, wherein said turbo encoder (202) comprising the steps of:
correcting the errors in data communication through interleaver (204) and encode the corrected data using the encoder (205) to generate the encoded data 1 (210); and
comparing the encoded data 1 (210) and 2 with the optimal puncturing sequencer (208) using match puncture (207) to generate the parity data (209), which checks the received data without any loss during data transmission. , Description:TITLE OF THE INVENTION: A CONCATENATED FEC ARCHITECTURE FOR 5G MOBILE COMMUNICATIONS
FIELD OF THE INVENTION
[0001] The present invention generally relates to the field of forward error correction. More particularly, the invention relates to the architecture of concatenated forward error correction for 5G mobile communications.
BACKGROUND OF THE INVENTION
[0002] Generally, the method of Forward error correction (FEC) is used for controlling the attained error while transmitting the data, in which the transmitter sends the redundant data to the receiver for identifying the portion of data, which contains no clear errors. FEC is mainly used for correcting the errors without requiring retransmission, which permits to recover the data contained in lost packets by means of transmitting the redundant information, which are utilized to reconstruct the missing data by the receiver. In order to improve the power efficiency, the FEC channel codes are organized and also it is considered as the method of channel-based error correction coding which assists the receiver to spot the errors precisely without any relations concerning the addition of unnecessary information at the transmitter side.
[0003] FEC used for data broadcasting from a single source to several destinations. Based on the kind of similarity information, the FEC encoder can be used to add the redundancy about the information on the transmitter section, whereas the FEC decoder can be made capable of utilizing the redundancy. In wireless networks, the use of FEC is an active area of research, which works well with Multicast. Also, it does not require interaction with the video encoder and hence it is appropriate to any method of video coding whether it is stored and live video.

Prior Arts:
[0004] Indian patent application 24/DELNP/2006 describes the system for generating the packets of forward error correction, which comprises a first FEC encoder that receives data and also the system comprises the second FEC encoder which encodes the encoded data of FEC to create second FEC data. Finally, the data of second FEC get formatted as a FEC packet through FEC packet formatter.
[0005] Indian patent application 40/DELNP/2010 describes the Rate-adaptive forward error correction for optical transport systems, which provides an optical transport system (OTS) consisting a plurality of optical transponders (OTs) connected through one or more optical links. The OTS posses the rate control unit (RCU) which is adapted to configure the OTs to dynamically adjust the rates of the FEC codes based on an estimated performance margin for each link between two respective communicating OTs for optimizing the overall OTS capacity.
[0006] Indian patent application 3840/DELNP/2007 describes the adaptive forward error correction, which includes an FEC encoder and an adaptive FEC device. The FEC encoder is used for encoding the k packets of source data into n packets, where n > k. On the basis of receiving one or more feedback messages, the number of redundant packets is determined by the adaptive FEC device. Such that, these feedback messages will specify a state of the wireless network.
[0007] State of the art suffers from the following limitations:
[0008] State of the art does not consider the novel hybrid forward error correction (FEC) architecture for 5G mobile communication. The present invention comprises both turbo code and polar code to develop the hardware architecture of the FEC coding scheme for 5G systems, and also to control the errors in data transmission over communication channels by means of the concatenated error correction schemes. The framework of concatenated FEC code with necessary data processing elements is included.
OBJECTIVES OF THE INVENTION
[0009] The primary objective of the present invention is to develop the hardware architecture of the FEC coding scheme for 5G systems.
[0010] Yet another objective of the present invention is to control the errors in data transmission over communication channels by concatenated error correction schemes.
[0011] Yet another objective of the present invention comprises the framework of the concatenated FEC code with necessary data processing elements.
SUMMARY OF THE INVENTION
[0012] A main aspect of the present invention is to develop the hardware architecture of the FEC code, which comprises both turbo code and polar code, to control the error in data transmission over communication channels.
[0013] Accordingly, in one aspect of the present invention comprises the framework of the concatenated FEC code, which includes the ‘N’ number of mobile users, Sub-channel allocation, Dual interleaver & de-interleaver, Concatenated encoder & decoder, Digital modulation & demodulation, and STBC.
[0014] Another aspect of this present invention is to allocate the single channel to the multi-users with the optimization principle using Sub-channel allocation.
[0015] Another aspect of this present invention is to encode the data over the channel and passes to the dual interleaver by means of concatenated FEC encoder, which includes time and frequency interleaver.
[0016] Another aspect of this present invention allows the multiple identical analog-to-digital converters (ADCs) to process the data series at a faster rate.
[0017] Another aspect of this present invention provides the random frequency interleaving for the data transmission and passes to the digital modulation.
[0018] Another aspect of this present invention consists of STBC to provide the data transmission over channels, and STBC combiner combines the coefficients of the channels, and passes to the digital demodulation.
[0019] Another aspect of this present invention includes the demodulation which demodulates the received data into its base format, and passes to the dual de-interleaver.
[0020] Another aspect of this present invention comprises both time de-interleaver and frequency de-interleaver
[0021] Another aspect of this present invention includes both polar encoder and turb3 encoder, which are combined with the serial to parallel converter.
[0022] Another aspect of this present invention includes the serial to parallel converter that is considered as a digital circuit, in which the input data are given serially, and read the outputs in a parallel manner.
BRIEF DESCRIPTION OF DRAWINGS
[0023] The accompanying drawings, which are incorporated in, constitute a part of the specification, illustrate an embodiment of the invention, and together with the description serve to explain the principles of the invention.
[0024] Figure 1 illustrates the framework of concatenated FEC codes for the 5G mobile communication system as provided in the present invention.
[0025] Figure 2 illustrates the FEC architecture as provided in the present invention.

DETAILED DESCRIPTION OF THE INVENTION
[0026] Some embodiments of this present invention, illustrating its features, will now be discussed, and the scope of the invention is not restricted to the listed embodiments and is limited only by the appended claims. One or more specific embodiments of the present invention will be described below.
[0027] The present invention shows the framework of concatenated FEC codes for the 5G mobile communication system (100). The present invention of the hybrid forward error correction scheme comprises both turbo code and polar code. The major contribution is to develop the hardware architecture of the FEC code by combining both polar code and turbo code.
[0028] In an embodiment of the present invention, as shown in figure 1, the framework of FEC architecture (100), which comprises both the transmitter and receiver section.
[0029] Forward Error Correction is a method for controlling errors in data transmission over communication channels. The framework of the concatenated FEC code is shown in figure 1 (100), which comprises the ‘N’ number of mobile users (101), Sub-channel allocation (102), Dual interleaver (105) & de-interleaver (111), Concatenated encoder (104) & decoder (114), Digital modulation (106) & demodulation (110), and STBC (107).
[0030] Transmitter Side: When the ‘N’ numbers of mobile users (101) are presented, then the Sub-channel allocation (102) allocates the single channel to the multi-users with the optimization principle (103). The concatenated FEC encoder (104) encodes the data over the channel and passes to the dual interleaver (105), which comprises both the time (1051) and frequency interleaver (1052).
[0031] The time interleaver (1051) allows the multiple identical analog-to-digital converters (ADCs) to process the data series at a faster rate and the frequency interleaver (1052) provides the random frequency interleaving for the data transmission and passes to the digital modulation (106) and STBC (107). STBC (107) is used in MIMO (108) to provide data transmission over channels.
[0032] Receiver Side: The communication channel sends the data to the STBC combiner (109), which combines the coefficients of the channels, and passes to the digital demodulation (110). A Digital Demodulator (110) receives the modulated data from the transmitter side and demodulates it into its base format, and passes to the dual de-interleaver (111), which includes both time de-interleaver (113) and frequency de-interleaver (112). The concatenated FEC decoder (114) starts decoding the received data for error correction and given to the mobile users.
[0033] In another embodiment of the present invention, as shown in figure 2, which includes both polar encoder (201) and turbo encoder (202), which are combined with the serial to parallel converter (23). Initially, the ‘N’ number of mobile users (101) is transmitted to the first section of polar encode (201), in which every user (101) is connected in series manner, and performed by the XOR operation, and finally passes to the serial to parallel converter (203).
[0034] A serial to parallel converter (203) is considered as a digital circuit, in which the input data are given serially, and read the outputs in a parallel manner. Turbo code comprises the interleaver (204), and match puncture (207). The errors in data communication can be corrected through interleaver (204) and encode the corrected data using the encoder (205) to generate the encoded data 1.
[0035] The block of match puncture (207) compares the encoded data 1 (205) and 2 (206) with the optimal puncturing sequencer (208) to generate the parity data (209), which checks the received data without any loss during data transmission.