A CONFIGURABLE I2C INTERFACE
Field of the Invention
This invention relates to a configurable I2C interface. More particularly, the invention relates to the input/output buffers of devices connected on the I2C bus, which can switch in three different modes of operation (Standard/Fast/High-Speed).
Background of the Invention
The I2C bus is a two-wire communication bus which is used for synchronous serial data transfer. The I2C bus can transfer data at rates up to 100 kbit/s (standard mode), 400 kbit/s (fast mode), or 3.4 Mbit/s (high-speed mode). The load on the I2C bus can also vary from 1Opf to 400pf. In standard and fast mode it is easy to achieve the required data rate without altering the system design. However, when the I2C bus switches into highspeed mode, the lOs used for the standard and fast mode fail to achieve the required data rate. It therefore becomes necessary to provide additional circuitry to enable the lOs to achieve the required data rate.
The available literature [1] describes a technique for achieving the high speed data rate using an internal current source when the load on the bus is upto lOOpf, and a combination of internal and external current source when the load on the I2C bus is more than lOOpf. This technique is useful when the load on the I2C bus and its mode of operation (data rate) is fixed.
FIGURE 1 shows the system level architecture of an implementation of a 12C driver implemented according to the prior art when the bus is operating in high speed mode and the load on the bus is higher than lOOpf. Here an external current source is connected on serial data line and serial clock line each. These external current sources help to achieve the required rise and fall times of the I2C bus. However, when the load on the I2C bus becomes less than lOOpf these external current sources must be removed. This arrangement complicates the switching of bus from one mode to another.
FIGURE 2 shows the structure of a I2C system according to the prior art (when the bus is in high speed mode and the load on the I2C bus is higher than 1OOpf) when operating with two different bus supply voltages. Each time the supply voltage on the I2C bus changes, additional current sources on the I2C bus must be connected for achieving the required data rate. This requirement makes the design of 12C system very complex.
Summary of the Invention
An object of the invention is to provide I2C buffers which make the I2C bus programmable, so that the I2C bus can switches from one mode to other mode without using any external current source.
Another object of the present invention is to simplify the implementation of I2C systems that operate at different bus supply voltages.
To achieve the above objectives the invention describes two separate IO buffers, one for the serial data line (DATA BUFFER) and the other for the serial clock line (CLOCK BUFFER). The DATA BUFFER contains an inbuilt current-source and a corresponding control circuit. The in-built current source improves the rising and falling edges of the serial data line when the I2C bus switches in high speed mode and the load on the bus is higher than lOOpf.
The CLOCK BUFFER contains two in-built current sources and a corresponding control circuit. One current source is used to improve only the rising edge of the serial clock line when the I2C bus is in high speed mode, whereas the other current source improves the rising as well as the falling edges of serial clock line when the 12C bus is in high speed mode and the load on the I2C bus is greater than 1 OOpf.
The input buffer of both the DATA and the CLOCK lines contain two in-built filter circuits, one for filtering spikes of <= 10ns (high speed) and the other for filtering spikes of <=50ns (fast mode). Also a no-filter path is provided for standard mode operation. An
inbuilt multiplexer circuit is used for selecting the required path according to the desired data transfer rate.
To achieve the said objective this invention provides a configurable I2C interface
comprising:
a clock input buffer;
a data input buffer;
a clock output buffer having a first configurable drive current source;
a data output buffer having a second configurable drive current source;
a first control circuit having a select input and output connected to the
control input of said first configurable drive current source; and
a second control circuit having a select input and output connected to the
control input of said second configurable drive current source;
The said first configurable drive current source comprises a first switch-able current source and a second switch-able current source.
The said second configurable drive current source comprises a single switch-able current source.
The said first control circuit enables said first switch-able current source of the said first configurable drive current source during the rising-edge of the clock during high-speed I2C mode.
The said first control circuit enables said second switch-able current source of the said first configurable drive current source for both the rising-edge and falling-edge of the clock during high-speed I2C mode when the load capacitance is greater than lOOpf.
The said second control circuit enables said switch-able current source of the said second configurable drive current source for both the rising-edge and falling-edge of the serial data line during high-speed I2C mode when the load capacitance is greater than lOOpf.
The said clock input buffer and said data input buffer includes selectable input filters for fast and high-speed mode of operation.
The said selectable input filter include a filter for pulses less than or equal to 50 nsec width during fast mode of operation.
The said selectable input filters include a filter for pulses less than or equal to 10 nsec width during high-speed mode of operation.
The said input filters are selected by means of an input signal multiplexer.
The present invention also prides a method for improving the performance of a I2C interface comprising the steps of:
providing a clock output buffer with configurable current drive;
providing a data output buffer with configurable current drive;
sensing the desired mode of operation;
sensing the value of the capacitive loading on the clock line and the data
line; and
selecting the current drive levels of the clock output buffer and the data
output buffer based on the desired operating mode as well the sensed
capacitive loading.
The current drive for the clock output buffer is configurable for one of three current levels.
The current drive for the data output buffer is configurable for one of two current levels.
The three current drive levels for the clock output buffer are configurable by either enabling a first current source having a first current value or enabling a second current having a second current value or enabling both first and second current sources
simultaneously.
The above method also includes the step of filtering the input signals on the data input and clock input buffers.
The filtering comprises the steps of:
enabling a first input filter during fast mode of operation; and enabling a second input filter during high-speed mode of operation.
The first input filter is configured to filter pulses of width less than or equal to 50nsec, while said second filter is configured to filter pulses of width less than or equal to lOnsec.
Brief Description of the Accompanying Drawings:
The invention will now be described with reference to the accompanying drawings.
FIGURE 1 shows I2C system level architecture according to the prior art, when the I2C bus is in high speed mode and the load on the bus is higher than lOOpf.
FIGURE 2 shows the operation of the I2C system according to the prior art when using two different bus voltages, when the I2C bus is in high speed mode and the load on the bus is higher than lOOpf.
FIGURE 3 shows the block diagram of the IO buffer for the serial clock line according to the present invention.
FIGURE 4 shows the block diagram of the IO buffer for the serial data line according to the present invention.
FIGURE 5 shows the application of the DATA and CLOCK lines of the I2C bus according to the present invention.
FIGURE 6 shows the operation of the I2C system according to the present invention, when the I2C bus is in high speed mode and the load on the bus is higher than lOOpf.
FIGURE 7 shows the operation of the I2C system according to the present invention, when the I2C bus is in high speed mode and the load on the bus is higher than 1 OOpf.
Detailed Description of the Invention
FIGURE 3 shows the block diagram of an input/output buffer according to the present invention, used on the serial clock line (SCL). The I2CINEN pin of the clock buffer is used to enable/disable the input buffer of the clock line. When the I2CINEN pin high, the input buffer gets enabled and when the I2CINEN pin is low, the input buffer gets disabled. When the clock buffer is in input mode, the signal at node PAD can propagate to the node I2CIN through three different paths depending on the mode of operation. In Standard mode the path with no filter is activated. In Fast mode the path with 50ns filter is activated. In high-speed mode the path with the 10ns filter is activated.
The pins HSFEN and FMFEN of the CLOCK buffer are used to select the appropriate path through which the signal at PAD will propagate to the I2CIN pin. When both HSFEN and FMFEN are low, the path with no filter is selected. When the Pin FMFEN is high and HSFEN is low, the path with the 50ns filter is selected. When the FMFEN is low and HSFEN is high, the path with the 1 Ons filter is selected. When the bus switches from one mode to the other mode, the values of HSFEN and FMFEN pins are to be changed correspondingly in order to select the appropriate path.
The pin I2COUTEN of the clock IO buffer is used to enable/disable the output buffer of the clock IO buffer. When the I2COUTEN pin is low, the output buffer gets enabled, and when the I2COUTEN pin is high the output buffer gets disabled. The ENHS pin represents the mode of the I2C bus. When the bus is in standard/fast mode, pin ENHS is set to low and when bus switches to high-speed mode pin ENHS is set to high
The HLOAD pin represents the load on the I2C bus. When the load on the I2C bus is lOpf to lOOpf, the HLOAD pin is set to low and when the load on I2C bus becomes more than lOOpf, HLOAD is set to high.
Current sources CS1 and CS2 are used to control the rise-time of the I2C bus. The current source CS1 is controlled by control signal Al and current source CS2 is controlled by control signal A2. Both control signals Al and A2 are generated by a control logic block A. Control logic block A generates the control signal Al and A2 by using ENHS, HLOAD, I2COUTEN, I2COUT and PAD as inputs. Control signal Al is generated in such a way that it enables the current source CS1 only when the I2C bus is in high-speed mode and the load on the I2C bus is more than lOOpf. In all other states the control signal Al keeps the current source CS1 off. Control signal A2 is generated in such a way that it enables current source CS2 only during the rising of the serial clock line when the I2C bus is in high speed mode and disables the current source CS2 in the other states. The use of CS1 and CS2 reduces the rise time of the clock line and hence increases the data rate of bus so that it can achieve the data transfer rate of 3.4 Mbits/sec in high speed mode. The current source CS2 will have no impact on the fall time of serial clock line, but the use of current source CS1 increases the fall time of serial clock line, when it is enabled.
FIGURE 4 shows the block diagram of the input/output buffer used on the 12C data line. The pin functionality of the DATA buffer is similar to that of the CLOCK buffer. Also the input and output sections of DATA buffer are the same as those of the CLOCK buffer. However, the DATA buffer uses only one current source CS1 for controlling the timing parameters of the serial data line when the 12C bus switches in high speed mode and the load on the I2C bus is greater than lOOpf. Current source CS1 is controlled by signal Bl generated from the control logic B of the DATA buffer. Control logic B generates control signal Bl from input signals ENHS, HLOAD and I2COUTEN. Control signal Bl is generated in such a way that it enables current source CS1 only when the I2C bus is in high-speed mode and the load on the I2C bus is greater than lOOpf. In all other states control signal B1 keeps the current source CS1 off.
FIGURE 5 shows the system level application of the DATA and CLOCK buffer. The IO buffers used on the I2C bus are open drain devices, and hence pull-up resistors must be added on both the serial data line and the serial clock line.
Below Table 1 shows the pin configuration of IO cells for different modes. The pins ENHS, HLOAD, FMFEN and HSFEN are used to switch the I2C buffer from one mode to the other.

(Table Removed)
Table 1: Pin configuration for DATA and CLOCK buffers in different mode of I2C
FIGURE 6 shows the system level architecture of a I2C bus based on the new invention. In this architecture, except for two external pull-up resistors no external component is used on the I2C bus. The lOs used to connect the device on the I2C bus are fully programmable and can be switched from one mode to the other without making any change in the system interconnections. Any variation of load on the I2C bus from lOpf to 400pf will also not require any change in components or their interconnections.
FIGURE 7 shows the diagram of a I2C system based on the present invention using two different bus supply voltages. In this implementation only a level shifter and pull-up resistors are required when the supply voltage of the I2C bus is changed. This simplifies the system level architecture of I2C bus when multiple bus supply voltages are used.
It is believed that the present invention and many of its attendant advantages will be understood by the foregoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an exemplary embodiment thereof, it is the intention of the following claims to encompass and include such changes.

We claim:
1. A configurable I2C interface comprising:
a clock input buffer; a data input buffer;
a clock output buffer having a first configurable drive current source; a data output buffer having a second configurable drive current source; a first control circuit having a select input and output connected to the control input of said first configurable drive current source; and a second control circuit having a select input and output connected to the control input of said second configurable drive current source;
2. A configurable I2C master interface as claimed in claim 1, wherein said first
configurable drive current source comprises a first switch-able current source and
a second switch-able current source.
3. A configurable I2C master interface as claimed in claim 1, wherein said second
configurable drive current source comprises a single switch-able current source.
4. A configurable I2C master interface as claimed in claim 2, wherein said first
control circuit enables said first switch-able current source of the said first
configurable drive current source during the rising-edge of the clock during high
speed I2C mode.
5. A configurable I2C master interface as claimed in claim 2, wherein said first
control circuit enables said second switch-able current source of the said first
configurable drive current source for both the rising-edge and falling-edge of the
clock during high-speed I2C mode when the load capacitance is greater than
lOO pf.
6. A configurable I2C master interface as claimed in claim 3, wherein said second
control circuit enables said switch-able current source of the said second
configurable drive current source for both the rising-edge and falling-edge of the
serial data line during high-speed I2C mode when the load capacitance is greater
than 100pf.
7. A configurable I2C master interface as claimed in claim 1, wherein said clock
input buffer and said data input buffer include selectable input filters for fast and
high-speed mode of operation.
8. A configurable I2C master interface as claimed in claim 7, wherein said selectable
input filter include a filter for pulses less than or equal to 50 nsec width during
fast mode of operation.
9. A configurable I2C master interface as claimed in claim 7, wherein said selectable
input filters include a filter for pulses less than or equal to 10 nsec width during
high-speed mode of operation.
10. A configurable I2C master interface as claimed in claim 1, wherein said input
filters are selected by means of an input signal multiplexer.
11. A method for improving the performance of a I2C interface comprising the steps
of:
providing a clock output buffer with configurable current drive;
providing a data output buffer with configurable current drive;
sensing the desired mode of operation;
sensing the value of the capacitive loading on the clock line and the data
line; and
selecting the current drive levels of the clock output buffer and the data
output buffer based on the desired operating mode as well the sensed
capacitive loading.
12. The method for improving the performance of a I2C interface as claimed in claim
11, wherein the current drive for the clock output buffer is configurable for one of
three current levels.
13. The method for improving the performance of a I2C interface as claimed in claim
11, wherein the current drive for the data output buffer is configurable for one of
two current levels.
14. The method for improving the performance of a I2C interface as claimed in claim
12, wherein the three current drive levels for the clock output buffer are
configurable by either enabling a first current source having a first current value
or enabling a second current having a second current value or enabling both first
and second current sources simultaneously.
15. The method for improving the performance of a I2C interface as claimed in claim
11, further including the step of filtering the input signals on the data input and
clock input buffers.
16. The method for improving the performance of a I2C interface as claimed in claim
15, wherein the filtering comprises the steps of:
enabling a first input filter during fast mode of operation; and enabling a second input filter during high-speed mode of operation.
17. The method for improving the performance of a I2C interface as claimed in claim
16, wherein the first input filter is configured to filter pulses of width less than or
equal to 50nsec, while said second filter is configured to filter pulses of width less
than or equal to 1 Onsec.
18. A configurable I2C interface substantially as herein described with reference to
and as illustrated in the accompanying drawings.A method for improving the performance of a I2C interface substantially as herein
described with reference to and as illustrated in the accompanying drawings.